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drm/i915/dsc: Fix PPS register definition macros for 2nd VDSC engine
This patch fixes the PPS4 and PPS5 register definition macros that were
resulting into an incorect MMIO address.
Fixes: 2efbb2f099
("i915/dp/dsc: Add DSC PPS register definitions")
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180824014807.14681-1-manasi.d.navare@intel.com
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@ -10454,7 +10454,7 @@ enum skl_power_gate {
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_ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
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_ICL_DSC0_PICTURE_PARAMETER_SET_4_PC)
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#define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
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_ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
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_ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \
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_ICL_DSC1_PICTURE_PARAMETER_SET_4_PC)
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#define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16)
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#define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0)
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@ -10469,7 +10469,7 @@ enum skl_power_gate {
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_ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \
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_ICL_DSC0_PICTURE_PARAMETER_SET_5_PC)
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#define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
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_ICL_DSC1_PICTURE_PARAMETER_SET_5_PC, \
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_ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \
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_ICL_DSC1_PICTURE_PARAMETER_SET_5_PC)
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#define DSC_SCALE_DEC_INT(scale_dec) ((scale_dec) << 16)
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#define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0)
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