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wl18xx: add register table
Add the register table with the appropriate values for wl18xx. Signed-off-by: Luciano Coelho <coelho@ti.com> Signed-off-by: Arik Nemtsov <arik@wizery.com>
This commit is contained in:
Luciano Coelho
parent
82b890cd4e
commit
5d4a9fa692
@ -25,6 +25,8 @@
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#include "../wlcore/wlcore.h"
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#include "../wlcore/debug.h"
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#include "reg.h"
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static struct wlcore_ops wl18xx_ops = {
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};
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@ -62,6 +64,26 @@ static const struct wlcore_partition_set wl18xx_ptable[PART_TABLE_LEN] = {
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},
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};
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static const int wl18xx_rtable[REG_TABLE_LEN] = {
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[REG_ECPU_CONTROL] = WL18XX_REG_ECPU_CONTROL,
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[REG_INTERRUPT_NO_CLEAR] = WL18XX_REG_INTERRUPT_NO_CLEAR,
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[REG_INTERRUPT_ACK] = WL18XX_REG_INTERRUPT_ACK,
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[REG_COMMAND_MAILBOX_PTR] = WL18XX_REG_COMMAND_MAILBOX_PTR,
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[REG_EVENT_MAILBOX_PTR] = WL18XX_REG_EVENT_MAILBOX_PTR,
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[REG_INTERRUPT_TRIG] = WL18XX_REG_INTERRUPT_TRIG_H,
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[REG_INTERRUPT_MASK] = WL18XX_REG_INTERRUPT_MASK,
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[REG_PC_ON_RECOVERY] = 0, /* TODO: where is the PC? */
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[REG_CHIP_ID_B] = WL18XX_REG_CHIP_ID_B,
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[REG_CMD_MBOX_ADDRESS] = WL18XX_CMD_MBOX_ADDRESS,
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/* data access memory addresses, used with partition translation */
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[REG_SLV_MEM_DATA] = WL18XX_SLV_MEM_DATA,
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[REG_SLV_REG_DATA] = WL18XX_SLV_REG_DATA,
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/* raw data access memory addresses */
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[REG_RAW_FW_STATUS_ADDR] = WL18XX_FW_STATUS_ADDR,
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};
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int __devinit wl18xx_probe(struct platform_device *pdev)
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{
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struct wl1271 *wl;
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@ -76,6 +98,7 @@ int __devinit wl18xx_probe(struct platform_device *pdev)
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wl = hw->priv;
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wl->ops = &wl18xx_ops;
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wl->ptable = wl18xx_ptable;
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wl->rtable = wl18xx_rtable;
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return wlcore_probe(wl, pdev);
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}
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112
drivers/net/wireless/ti/wl18xx/reg.h
Normal file
112
drivers/net/wireless/ti/wl18xx/reg.h
Normal file
@ -0,0 +1,112 @@
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/*
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* This file is part of wlcore
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*
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* Copyright (C) 2011 Texas Instruments Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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*/
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#ifndef __REG_H__
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#define __REG_H__
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#define WL18XX_REGISTERS_BASE 0x00800000
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#define WL18XX_CODE_BASE 0x00000000
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#define WL18XX_DATA_BASE 0x00400000
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#define WL18XX_DOUBLE_BUFFER_BASE 0x00600000
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#define WL18XX_MCU_KEY_SEARCH_BASE 0x00700000
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#define WL18XX_PHY_BASE 0x00900000
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#define WL18XX_TOP_OCP_BASE 0x00A00000
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#define WL18XX_PACKET_RAM_BASE 0x00B00000
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#define WL18XX_HOST_BASE 0x00C00000
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#define WL18XX_REGISTERS_DOWN_SIZE 0x0000B000
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#define WL18XX_REG_BOOT_PART_START 0x00802000
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#define WL18XX_REG_BOOT_PART_SIZE 0x00014578
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#define WL18XX_PHY_INIT_MEM_ADDR 0x80926000
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#define WL18XX_SDIO_WSPI_BASE (WL18XX_REGISTERS_BASE)
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#define WL18XX_REG_CONFIG_BASE (WL18XX_REGISTERS_BASE + 0x02000)
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#define WL18XX_WGCM_REGS_BASE (WL18XX_REGISTERS_BASE + 0x03000)
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#define WL18XX_ENC_BASE (WL18XX_REGISTERS_BASE + 0x04000)
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#define WL18XX_INTERRUPT_BASE (WL18XX_REGISTERS_BASE + 0x05000)
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#define WL18XX_UART_BASE (WL18XX_REGISTERS_BASE + 0x06000)
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#define WL18XX_WELP_BASE (WL18XX_REGISTERS_BASE + 0x07000)
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#define WL18XX_TCP_CKSM_BASE (WL18XX_REGISTERS_BASE + 0x08000)
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#define WL18XX_FIFO_BASE (WL18XX_REGISTERS_BASE + 0x09000)
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#define WL18XX_OCP_BRIDGE_BASE (WL18XX_REGISTERS_BASE + 0x0A000)
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#define WL18XX_PMAC_RX_BASE (WL18XX_REGISTERS_BASE + 0x14800)
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#define WL18XX_PMAC_ACM_BASE (WL18XX_REGISTERS_BASE + 0x14C00)
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#define WL18XX_PMAC_TX_BASE (WL18XX_REGISTERS_BASE + 0x15000)
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#define WL18XX_PMAC_CSR_BASE (WL18XX_REGISTERS_BASE + 0x15400)
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#define WL18XX_REG_ECPU_CONTROL (WL18XX_REGISTERS_BASE + 0x02004)
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#define WL18XX_REG_INTERRUPT_NO_CLEAR (WL18XX_REGISTERS_BASE + 0x050E8)
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#define WL18XX_REG_INTERRUPT_ACK (WL18XX_REGISTERS_BASE + 0x050F0)
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#define WL18XX_REG_INTERRUPT_TRIG (WL18XX_REGISTERS_BASE + 0x5074)
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#define WL18XX_REG_INTERRUPT_TRIG_H (WL18XX_REGISTERS_BASE + 0x5078)
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#define WL18XX_REG_INTERRUPT_MASK (WL18XX_REGISTERS_BASE + 0x0050DC)
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#define WL18XX_REG_CHIP_ID_B (WL18XX_REGISTERS_BASE + 0x01542C)
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#define WL18XX_SLV_MEM_DATA (WL18XX_HOST_BASE + 0x0018)
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#define WL18XX_SLV_REG_DATA (WL18XX_HOST_BASE + 0x0008)
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/* Scratch Pad registers*/
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#define WL18XX_SCR_PAD0 (WL18XX_REGISTERS_BASE + 0x0154EC)
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#define WL18XX_SCR_PAD1 (WL18XX_REGISTERS_BASE + 0x0154F0)
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#define WL18XX_SCR_PAD2 (WL18XX_REGISTERS_BASE + 0x0154F4)
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#define WL18XX_SCR_PAD3 (WL18XX_REGISTERS_BASE + 0x0154F8)
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#define WL18XX_SCR_PAD4 (WL18XX_REGISTERS_BASE + 0x0154FC)
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#define WL18XX_SCR_PAD4_SET (WL18XX_REGISTERS_BASE + 0x015504)
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#define WL18XX_SCR_PAD4_CLR (WL18XX_REGISTERS_BASE + 0x015500)
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#define WL18XX_SCR_PAD5 (WL18XX_REGISTERS_BASE + 0x015508)
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#define WL18XX_SCR_PAD5_SET (WL18XX_REGISTERS_BASE + 0x015510)
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#define WL18XX_SCR_PAD5_CLR (WL18XX_REGISTERS_BASE + 0x01550C)
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#define WL18XX_SCR_PAD6 (WL18XX_REGISTERS_BASE + 0x015514)
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#define WL18XX_SCR_PAD7 (WL18XX_REGISTERS_BASE + 0x015518)
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#define WL18XX_SCR_PAD8 (WL18XX_REGISTERS_BASE + 0x01551C)
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#define WL18XX_SCR_PAD9 (WL18XX_REGISTERS_BASE + 0x015520)
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/* Spare registers*/
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#define WL18XX_SPARE_A1 (WL18XX_REGISTERS_BASE + 0x002194)
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#define WL18XX_SPARE_A2 (WL18XX_REGISTERS_BASE + 0x002198)
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#define WL18XX_SPARE_A3 (WL18XX_REGISTERS_BASE + 0x00219C)
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#define WL18XX_SPARE_A4 (WL18XX_REGISTERS_BASE + 0x0021A0)
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#define WL18XX_SPARE_A5 (WL18XX_REGISTERS_BASE + 0x0021A4)
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#define WL18XX_SPARE_A6 (WL18XX_REGISTERS_BASE + 0x0021A8)
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#define WL18XX_SPARE_A7 (WL18XX_REGISTERS_BASE + 0x0021AC)
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#define WL18XX_SPARE_A8 (WL18XX_REGISTERS_BASE + 0x0021B0)
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#define WL18XX_SPARE_B1 (WL18XX_REGISTERS_BASE + 0x015524)
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#define WL18XX_SPARE_B2 (WL18XX_REGISTERS_BASE + 0x015528)
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#define WL18XX_SPARE_B3 (WL18XX_REGISTERS_BASE + 0x01552C)
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#define WL18XX_SPARE_B4 (WL18XX_REGISTERS_BASE + 0x015530)
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#define WL18XX_SPARE_B5 (WL18XX_REGISTERS_BASE + 0x015534)
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#define WL18XX_SPARE_B6 (WL18XX_REGISTERS_BASE + 0x015538)
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#define WL18XX_SPARE_B7 (WL18XX_REGISTERS_BASE + 0x01553C)
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#define WL18XX_SPARE_B8 (WL18XX_REGISTERS_BASE + 0x015540)
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#define WL18XX_REG_COMMAND_MAILBOX_PTR (WL18XX_SCR_PAD0)
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#define WL18XX_REG_EVENT_MAILBOX_PTR (WL18XX_SCR_PAD1)
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#define WL18XX_CMD_MBOX_ADDRESS 0xB007B4
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#define WL18XX_FW_STATUS_ADDR 0x50F8
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#define CHIP_ID_185x_PG10 (0x06030101)
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#endif /* __REG_H__ */
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