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clk: uniphier: rename MIO clock to SD clock for Pro5, PXs2, LD20 SoCs
I made a mistake as for naming for this block. The MIO block is not implemented for these 3 SoCs in the first place. The current naming will be a trouble if an SoC with both MIO and SD-ctrl blocks appear in the future. This driver has just been merged in the previous merge window. Rename it before the release. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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@ -24,7 +24,7 @@ Example:
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reg = <0x61840000 0x4000>;
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clock {
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compatible = "socionext,uniphier-ld20-clock";
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compatible = "socionext,uniphier-ld11-clock";
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#clock-cells = <1>;
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};
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@ -43,8 +43,8 @@ Provided clocks:
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21: USB3 ch1 PHY1
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Media I/O (MIO) clock
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---------------------
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Media I/O (MIO) clock, SD clock
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-------------------------------
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Required properties:
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- compatible: should be one of the following:
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@ -52,10 +52,10 @@ Required properties:
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"socionext,uniphier-ld4-mio-clock" - for LD4 SoC.
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"socionext,uniphier-pro4-mio-clock" - for Pro4 SoC.
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"socionext,uniphier-sld8-mio-clock" - for sLD8 SoC.
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"socionext,uniphier-pro5-mio-clock" - for Pro5 SoC.
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"socionext,uniphier-pxs2-mio-clock" - for PXs2/LD6b SoC.
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"socionext,uniphier-pro5-sd-clock" - for Pro5 SoC.
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"socionext,uniphier-pxs2-sd-clock" - for PXs2/LD6b SoC.
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"socionext,uniphier-ld11-mio-clock" - for LD11 SoC.
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"socionext,uniphier-ld20-mio-clock" - for LD20 SoC.
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"socionext,uniphier-ld20-sd-clock" - for LD20 SoC.
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- #clock-cells: should be 1.
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Example:
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@ -66,7 +66,7 @@ Example:
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reg = <0x59810000 0x800>;
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clock {
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compatible = "socionext,uniphier-ld20-mio-clock";
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compatible = "socionext,uniphier-ld11-mio-clock";
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#clock-cells = <1>;
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};
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@ -112,7 +112,7 @@ Example:
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reg = <0x59820000 0x200>;
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clock {
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compatible = "socionext,uniphier-ld20-peri-clock";
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compatible = "socionext,uniphier-ld11-peri-clock";
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#clock-cells = <1>;
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};
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@ -142,7 +142,7 @@ static const struct of_device_id uniphier_clk_match[] = {
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.compatible = "socionext,uniphier-ld20-clock",
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.data = uniphier_ld20_sys_clk_data,
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},
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/* Media I/O clock */
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/* Media I/O clock, SD clock */
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{
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.compatible = "socionext,uniphier-sld3-mio-clock",
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.data = uniphier_sld3_mio_clk_data,
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@ -160,20 +160,20 @@ static const struct of_device_id uniphier_clk_match[] = {
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.data = uniphier_sld3_mio_clk_data,
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},
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{
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.compatible = "socionext,uniphier-pro5-mio-clock",
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.data = uniphier_pro5_mio_clk_data,
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.compatible = "socionext,uniphier-pro5-sd-clock",
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.data = uniphier_pro5_sd_clk_data,
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},
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{
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.compatible = "socionext,uniphier-pxs2-mio-clock",
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.data = uniphier_pro5_mio_clk_data,
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.compatible = "socionext,uniphier-pxs2-sd-clock",
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.data = uniphier_pro5_sd_clk_data,
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},
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{
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.compatible = "socionext,uniphier-ld11-mio-clock",
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.data = uniphier_sld3_mio_clk_data,
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},
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{
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.compatible = "socionext,uniphier-ld20-mio-clock",
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.data = uniphier_pro5_mio_clk_data,
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.compatible = "socionext,uniphier-ld20-sd-clock",
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.data = uniphier_pro5_sd_clk_data,
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},
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/* Peripheral clock */
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{
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@ -93,7 +93,7 @@ const struct uniphier_clk_data uniphier_sld3_mio_clk_data[] = {
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{ /* sentinel */ }
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};
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const struct uniphier_clk_data uniphier_pro5_mio_clk_data[] = {
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const struct uniphier_clk_data uniphier_pro5_sd_clk_data[] = {
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UNIPHIER_MIO_CLK_SD_FIXED,
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UNIPHIER_MIO_CLK_SD(0, 0),
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UNIPHIER_MIO_CLK_SD(1, 1),
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@ -115,7 +115,7 @@ extern const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[];
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extern const struct uniphier_clk_data uniphier_ld11_sys_clk_data[];
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extern const struct uniphier_clk_data uniphier_ld20_sys_clk_data[];
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extern const struct uniphier_clk_data uniphier_sld3_mio_clk_data[];
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extern const struct uniphier_clk_data uniphier_pro5_mio_clk_data[];
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extern const struct uniphier_clk_data uniphier_pro5_sd_clk_data[];
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extern const struct uniphier_clk_data uniphier_ld4_peri_clk_data[];
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extern const struct uniphier_clk_data uniphier_pro4_peri_clk_data[];
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