mirror of
https://github.com/edk2-porting/linux-next.git
synced 2025-01-19 19:14:01 +08:00
drm/nouveau/bar: cosmetic changes
This is purely preparation for upcoming commits, there should be no code changes here. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
parent
9ace404b10
commit
5b0c189fcb
@ -5,7 +5,7 @@ struct nvkm_mem;
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struct nvkm_vma;
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struct nvkm_bar {
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struct nvkm_subdev base;
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struct nvkm_subdev subdev;
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int (*alloc)(struct nvkm_bar *, struct nvkm_object *,
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struct nvkm_mem *, struct nvkm_object **);
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@ -117,22 +117,14 @@ int
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nvkm_bar_create_(struct nvkm_object *parent, struct nvkm_object *engine,
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struct nvkm_oclass *oclass, int length, void **pobject)
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{
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struct nvkm_bar *bar;
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int ret;
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ret = nvkm_subdev_create_(parent, engine, oclass, 0, "BARCTL",
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"bar", length, pobject);
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bar = *pobject;
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if (ret)
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return ret;
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return 0;
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return nvkm_subdev_create_(parent, engine, oclass, 0, "BARCTL",
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"bar", length, pobject);
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}
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void
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nvkm_bar_destroy(struct nvkm_bar *bar)
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{
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nvkm_subdev_destroy(&bar->base);
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nvkm_subdev_destroy(&bar->subdev);
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}
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void
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@ -27,26 +27,26 @@
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#include <subdev/fb.h>
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#include <subdev/mmu.h>
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struct gf100_bar_priv_vm {
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struct gf100_bar_vm {
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struct nvkm_gpuobj *mem;
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struct nvkm_gpuobj *pgd;
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struct nvkm_vm *vm;
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};
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struct gf100_bar_priv {
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struct gf100_bar {
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struct nvkm_bar base;
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spinlock_t lock;
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struct gf100_bar_priv_vm bar[2];
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struct gf100_bar_vm bar[2];
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};
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static int
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gf100_bar_kmap(struct nvkm_bar *bar, struct nvkm_mem *mem, u32 flags,
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gf100_bar_kmap(struct nvkm_bar *obj, struct nvkm_mem *mem, u32 flags,
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struct nvkm_vma *vma)
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{
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struct gf100_bar_priv *priv = (void *)bar;
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struct gf100_bar *bar = container_of(obj, typeof(*bar), base);
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int ret;
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ret = nvkm_vm_get(priv->bar[0].vm, mem->size << 12, 12, flags, vma);
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ret = nvkm_vm_get(bar->bar[0].vm, mem->size << 12, 12, flags, vma);
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if (ret)
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return ret;
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@ -55,13 +55,13 @@ gf100_bar_kmap(struct nvkm_bar *bar, struct nvkm_mem *mem, u32 flags,
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}
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static int
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gf100_bar_umap(struct nvkm_bar *bar, struct nvkm_mem *mem, u32 flags,
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gf100_bar_umap(struct nvkm_bar *obj, struct nvkm_mem *mem, u32 flags,
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struct nvkm_vma *vma)
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{
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struct gf100_bar_priv *priv = (void *)bar;
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struct gf100_bar *bar = container_of(obj, typeof(*bar), base);
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int ret;
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ret = nvkm_vm_get(priv->bar[1].vm, mem->size << 12,
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ret = nvkm_vm_get(bar->bar[1].vm, mem->size << 12,
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mem->page_shift, flags, vma);
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if (ret)
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return ret;
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@ -78,20 +78,20 @@ gf100_bar_unmap(struct nvkm_bar *bar, struct nvkm_vma *vma)
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}
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static int
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gf100_bar_ctor_vm(struct gf100_bar_priv *priv, struct gf100_bar_priv_vm *bar_vm,
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gf100_bar_ctor_vm(struct gf100_bar *bar, struct gf100_bar_vm *bar_vm,
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int bar_nr)
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{
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struct nvkm_device *device = nv_device(&priv->base);
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struct nvkm_device *device = nv_device(&bar->base);
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struct nvkm_vm *vm;
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resource_size_t bar_len;
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int ret;
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ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x1000, 0, 0,
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ret = nvkm_gpuobj_new(nv_object(bar), NULL, 0x1000, 0, 0,
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&bar_vm->mem);
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if (ret)
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return ret;
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ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x8000, 0, 0,
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ret = nvkm_gpuobj_new(nv_object(bar), NULL, 0x8000, 0, 0,
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&bar_vm->pgd);
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if (ret)
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return ret;
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@ -108,7 +108,7 @@ gf100_bar_ctor_vm(struct gf100_bar_priv *priv, struct gf100_bar_priv_vm *bar_vm,
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* Bootstrap page table lookup.
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*/
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if (bar_nr == 3) {
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ret = nvkm_gpuobj_new(nv_object(priv), NULL,
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ret = nvkm_gpuobj_new(nv_object(bar), NULL,
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(bar_len >> 12) * 8, 0x1000,
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NVOBJ_FLAG_ZERO_ALLOC,
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&vm->pgt[0].obj[0]);
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@ -135,74 +135,74 @@ gf100_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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struct nvkm_object **pobject)
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{
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struct nvkm_device *device = nv_device(parent);
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struct gf100_bar_priv *priv;
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struct gf100_bar *bar;
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bool has_bar3 = nv_device_resource_len(device, 3) != 0;
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int ret;
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ret = nvkm_bar_create(parent, engine, oclass, &priv);
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*pobject = nv_object(priv);
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ret = nvkm_bar_create(parent, engine, oclass, &bar);
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*pobject = nv_object(bar);
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if (ret)
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return ret;
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/* BAR3 */
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if (has_bar3) {
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ret = gf100_bar_ctor_vm(priv, &priv->bar[0], 3);
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ret = gf100_bar_ctor_vm(bar, &bar->bar[0], 3);
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if (ret)
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return ret;
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}
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/* BAR1 */
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ret = gf100_bar_ctor_vm(priv, &priv->bar[1], 1);
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ret = gf100_bar_ctor_vm(bar, &bar->bar[1], 1);
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if (ret)
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return ret;
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if (has_bar3) {
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priv->base.alloc = nvkm_bar_alloc;
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priv->base.kmap = gf100_bar_kmap;
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bar->base.alloc = nvkm_bar_alloc;
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bar->base.kmap = gf100_bar_kmap;
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}
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priv->base.umap = gf100_bar_umap;
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priv->base.unmap = gf100_bar_unmap;
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priv->base.flush = g84_bar_flush;
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spin_lock_init(&priv->lock);
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bar->base.umap = gf100_bar_umap;
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bar->base.unmap = gf100_bar_unmap;
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bar->base.flush = g84_bar_flush;
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spin_lock_init(&bar->lock);
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return 0;
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}
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void
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gf100_bar_dtor(struct nvkm_object *object)
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{
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struct gf100_bar_priv *priv = (void *)object;
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struct gf100_bar *bar = (void *)object;
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nvkm_vm_ref(NULL, &priv->bar[1].vm, priv->bar[1].pgd);
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nvkm_gpuobj_ref(NULL, &priv->bar[1].pgd);
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nvkm_gpuobj_ref(NULL, &priv->bar[1].mem);
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nvkm_vm_ref(NULL, &bar->bar[1].vm, bar->bar[1].pgd);
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nvkm_gpuobj_ref(NULL, &bar->bar[1].pgd);
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nvkm_gpuobj_ref(NULL, &bar->bar[1].mem);
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if (priv->bar[0].vm) {
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nvkm_gpuobj_ref(NULL, &priv->bar[0].vm->pgt[0].obj[0]);
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nvkm_vm_ref(NULL, &priv->bar[0].vm, priv->bar[0].pgd);
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if (bar->bar[0].vm) {
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nvkm_gpuobj_ref(NULL, &bar->bar[0].vm->pgt[0].obj[0]);
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nvkm_vm_ref(NULL, &bar->bar[0].vm, bar->bar[0].pgd);
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}
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nvkm_gpuobj_ref(NULL, &priv->bar[0].pgd);
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nvkm_gpuobj_ref(NULL, &priv->bar[0].mem);
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nvkm_gpuobj_ref(NULL, &bar->bar[0].pgd);
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nvkm_gpuobj_ref(NULL, &bar->bar[0].mem);
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nvkm_bar_destroy(&priv->base);
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nvkm_bar_destroy(&bar->base);
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}
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int
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gf100_bar_init(struct nvkm_object *object)
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{
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struct gf100_bar_priv *priv = (void *)object;
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struct gf100_bar *bar = (void *)object;
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int ret;
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ret = nvkm_bar_init(&priv->base);
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ret = nvkm_bar_init(&bar->base);
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if (ret)
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return ret;
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nv_mask(priv, 0x000200, 0x00000100, 0x00000000);
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nv_mask(priv, 0x000200, 0x00000100, 0x00000100);
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nv_mask(bar, 0x000200, 0x00000100, 0x00000000);
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nv_mask(bar, 0x000200, 0x00000100, 0x00000100);
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nv_wr32(priv, 0x001704, 0x80000000 | priv->bar[1].mem->addr >> 12);
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if (priv->bar[0].mem)
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nv_wr32(priv, 0x001714,
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0xc0000000 | priv->bar[0].mem->addr >> 12);
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nv_wr32(bar, 0x001704, 0x80000000 | bar->bar[1].mem->addr >> 12);
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if (bar->bar[0].mem)
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nv_wr32(bar, 0x001714,
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0xc0000000 | bar->bar[0].mem->addr >> 12);
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return 0;
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}
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@ -28,7 +28,7 @@
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#include <subdev/mmu.h>
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#include <subdev/timer.h>
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struct nv50_bar_priv {
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struct nv50_bar {
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struct nvkm_bar base;
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spinlock_t lock;
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struct nvkm_gpuobj *mem;
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@ -41,13 +41,13 @@ struct nv50_bar_priv {
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};
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static int
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nv50_bar_kmap(struct nvkm_bar *bar, struct nvkm_mem *mem, u32 flags,
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nv50_bar_kmap(struct nvkm_bar *obj, struct nvkm_mem *mem, u32 flags,
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struct nvkm_vma *vma)
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{
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struct nv50_bar_priv *priv = (void *)bar;
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struct nv50_bar *bar = container_of(obj, typeof(*bar), base);
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int ret;
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ret = nvkm_vm_get(priv->bar3_vm, mem->size << 12, 12, flags, vma);
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ret = nvkm_vm_get(bar->bar3_vm, mem->size << 12, 12, flags, vma);
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if (ret)
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return ret;
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@ -56,13 +56,13 @@ nv50_bar_kmap(struct nvkm_bar *bar, struct nvkm_mem *mem, u32 flags,
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}
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static int
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nv50_bar_umap(struct nvkm_bar *bar, struct nvkm_mem *mem, u32 flags,
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nv50_bar_umap(struct nvkm_bar *obj, struct nvkm_mem *mem, u32 flags,
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struct nvkm_vma *vma)
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{
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struct nv50_bar_priv *priv = (void *)bar;
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struct nv50_bar *bar = container_of(obj, typeof(*bar), base);
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int ret;
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ret = nvkm_vm_get(priv->bar1_vm, mem->size << 12, 12, flags, vma);
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ret = nvkm_vm_get(bar->bar1_vm, mem->size << 12, 12, flags, vma);
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if (ret)
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return ret;
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@ -78,27 +78,27 @@ nv50_bar_unmap(struct nvkm_bar *bar, struct nvkm_vma *vma)
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}
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static void
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nv50_bar_flush(struct nvkm_bar *bar)
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nv50_bar_flush(struct nvkm_bar *obj)
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{
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struct nv50_bar_priv *priv = (void *)bar;
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struct nv50_bar *bar = container_of(obj, typeof(*bar), base);
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unsigned long flags;
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spin_lock_irqsave(&priv->lock, flags);
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nv_wr32(priv, 0x00330c, 0x00000001);
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if (!nv_wait(priv, 0x00330c, 0x00000002, 0x00000000))
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nv_warn(priv, "flush timeout\n");
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spin_unlock_irqrestore(&priv->lock, flags);
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spin_lock_irqsave(&bar->lock, flags);
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nv_wr32(bar, 0x00330c, 0x00000001);
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if (!nv_wait(bar, 0x00330c, 0x00000002, 0x00000000))
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nv_warn(bar, "flush timeout\n");
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spin_unlock_irqrestore(&bar->lock, flags);
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}
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void
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g84_bar_flush(struct nvkm_bar *bar)
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g84_bar_flush(struct nvkm_bar *obj)
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{
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struct nv50_bar_priv *priv = (void *)bar;
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struct nv50_bar *bar = container_of(obj, typeof(*bar), base);
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unsigned long flags;
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spin_lock_irqsave(&priv->lock, flags);
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spin_lock_irqsave(&bar->lock, flags);
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nv_wr32(bar, 0x070000, 0x00000001);
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if (!nv_wait(priv, 0x070000, 0x00000002, 0x00000000))
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nv_warn(priv, "flush timeout\n");
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spin_unlock_irqrestore(&priv->lock, flags);
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if (!nv_wait(bar, 0x070000, 0x00000002, 0x00000000))
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nv_warn(bar, "flush timeout\n");
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spin_unlock_irqrestore(&bar->lock, flags);
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}
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static int
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@ -109,28 +109,28 @@ nv50_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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struct nvkm_device *device = nv_device(parent);
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struct nvkm_object *heap;
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struct nvkm_vm *vm;
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struct nv50_bar_priv *priv;
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struct nv50_bar *bar;
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u64 start, limit;
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int ret;
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ret = nvkm_bar_create(parent, engine, oclass, &priv);
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*pobject = nv_object(priv);
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ret = nvkm_bar_create(parent, engine, oclass, &bar);
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*pobject = nv_object(bar);
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if (ret)
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return ret;
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ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x20000, 0,
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NVOBJ_FLAG_HEAP, &priv->mem);
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heap = nv_object(priv->mem);
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ret = nvkm_gpuobj_new(nv_object(bar), NULL, 0x20000, 0,
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NVOBJ_FLAG_HEAP, &bar->mem);
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heap = nv_object(bar->mem);
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if (ret)
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return ret;
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ret = nvkm_gpuobj_new(nv_object(priv), heap,
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ret = nvkm_gpuobj_new(nv_object(bar), heap,
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(device->chipset == 0x50) ? 0x1400 : 0x0200,
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0, 0, &priv->pad);
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0, 0, &bar->pad);
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if (ret)
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return ret;
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ret = nvkm_gpuobj_new(nv_object(priv), heap, 0x4000, 0, 0, &priv->pgd);
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ret = nvkm_gpuobj_new(nv_object(bar), heap, 0x4000, 0, 0, &bar->pgd);
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if (ret)
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return ret;
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@ -144,29 +144,29 @@ nv50_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]);
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ret = nvkm_gpuobj_new(nv_object(priv), heap,
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ret = nvkm_gpuobj_new(nv_object(bar), heap,
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((limit-- - start) >> 12) * 8, 0x1000,
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NVOBJ_FLAG_ZERO_ALLOC, &vm->pgt[0].obj[0]);
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vm->pgt[0].refcount[0] = 1;
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if (ret)
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return ret;
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ret = nvkm_vm_ref(vm, &priv->bar3_vm, priv->pgd);
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ret = nvkm_vm_ref(vm, &bar->bar3_vm, bar->pgd);
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nvkm_vm_ref(NULL, &vm, NULL);
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if (ret)
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return ret;
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ret = nvkm_gpuobj_new(nv_object(priv), heap, 24, 16, 0, &priv->bar3);
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ret = nvkm_gpuobj_new(nv_object(bar), heap, 24, 16, 0, &bar->bar3);
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if (ret)
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return ret;
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nv_wo32(priv->bar3, 0x00, 0x7fc00000);
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nv_wo32(priv->bar3, 0x04, lower_32_bits(limit));
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nv_wo32(priv->bar3, 0x08, lower_32_bits(start));
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nv_wo32(priv->bar3, 0x0c, upper_32_bits(limit) << 24 |
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nv_wo32(bar->bar3, 0x00, 0x7fc00000);
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nv_wo32(bar->bar3, 0x04, lower_32_bits(limit));
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nv_wo32(bar->bar3, 0x08, lower_32_bits(start));
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nv_wo32(bar->bar3, 0x0c, upper_32_bits(limit) << 24 |
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upper_32_bits(start));
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nv_wo32(priv->bar3, 0x10, 0x00000000);
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nv_wo32(priv->bar3, 0x14, 0x00000000);
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nv_wo32(bar->bar3, 0x10, 0x00000000);
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nv_wo32(bar->bar3, 0x14, 0x00000000);
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/* BAR1 */
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start = 0x0000000000ULL;
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@ -178,84 +178,84 @@ nv50_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]);
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ret = nvkm_vm_ref(vm, &priv->bar1_vm, priv->pgd);
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ret = nvkm_vm_ref(vm, &bar->bar1_vm, bar->pgd);
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nvkm_vm_ref(NULL, &vm, NULL);
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if (ret)
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return ret;
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ret = nvkm_gpuobj_new(nv_object(priv), heap, 24, 16, 0, &priv->bar1);
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ret = nvkm_gpuobj_new(nv_object(bar), heap, 24, 16, 0, &bar->bar1);
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if (ret)
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return ret;
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nv_wo32(priv->bar1, 0x00, 0x7fc00000);
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||||
nv_wo32(priv->bar1, 0x04, lower_32_bits(limit));
|
||||
nv_wo32(priv->bar1, 0x08, lower_32_bits(start));
|
||||
nv_wo32(priv->bar1, 0x0c, upper_32_bits(limit) << 24 |
|
||||
nv_wo32(bar->bar1, 0x00, 0x7fc00000);
|
||||
nv_wo32(bar->bar1, 0x04, lower_32_bits(limit));
|
||||
nv_wo32(bar->bar1, 0x08, lower_32_bits(start));
|
||||
nv_wo32(bar->bar1, 0x0c, upper_32_bits(limit) << 24 |
|
||||
upper_32_bits(start));
|
||||
nv_wo32(priv->bar1, 0x10, 0x00000000);
|
||||
nv_wo32(priv->bar1, 0x14, 0x00000000);
|
||||
nv_wo32(bar->bar1, 0x10, 0x00000000);
|
||||
nv_wo32(bar->bar1, 0x14, 0x00000000);
|
||||
|
||||
priv->base.alloc = nvkm_bar_alloc;
|
||||
priv->base.kmap = nv50_bar_kmap;
|
||||
priv->base.umap = nv50_bar_umap;
|
||||
priv->base.unmap = nv50_bar_unmap;
|
||||
bar->base.alloc = nvkm_bar_alloc;
|
||||
bar->base.kmap = nv50_bar_kmap;
|
||||
bar->base.umap = nv50_bar_umap;
|
||||
bar->base.unmap = nv50_bar_unmap;
|
||||
if (device->chipset == 0x50)
|
||||
priv->base.flush = nv50_bar_flush;
|
||||
bar->base.flush = nv50_bar_flush;
|
||||
else
|
||||
priv->base.flush = g84_bar_flush;
|
||||
spin_lock_init(&priv->lock);
|
||||
bar->base.flush = g84_bar_flush;
|
||||
spin_lock_init(&bar->lock);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void
|
||||
nv50_bar_dtor(struct nvkm_object *object)
|
||||
{
|
||||
struct nv50_bar_priv *priv = (void *)object;
|
||||
nvkm_gpuobj_ref(NULL, &priv->bar1);
|
||||
nvkm_vm_ref(NULL, &priv->bar1_vm, priv->pgd);
|
||||
nvkm_gpuobj_ref(NULL, &priv->bar3);
|
||||
if (priv->bar3_vm) {
|
||||
nvkm_gpuobj_ref(NULL, &priv->bar3_vm->pgt[0].obj[0]);
|
||||
nvkm_vm_ref(NULL, &priv->bar3_vm, priv->pgd);
|
||||
struct nv50_bar *bar = (void *)object;
|
||||
nvkm_gpuobj_ref(NULL, &bar->bar1);
|
||||
nvkm_vm_ref(NULL, &bar->bar1_vm, bar->pgd);
|
||||
nvkm_gpuobj_ref(NULL, &bar->bar3);
|
||||
if (bar->bar3_vm) {
|
||||
nvkm_gpuobj_ref(NULL, &bar->bar3_vm->pgt[0].obj[0]);
|
||||
nvkm_vm_ref(NULL, &bar->bar3_vm, bar->pgd);
|
||||
}
|
||||
nvkm_gpuobj_ref(NULL, &priv->pgd);
|
||||
nvkm_gpuobj_ref(NULL, &priv->pad);
|
||||
nvkm_gpuobj_ref(NULL, &priv->mem);
|
||||
nvkm_bar_destroy(&priv->base);
|
||||
nvkm_gpuobj_ref(NULL, &bar->pgd);
|
||||
nvkm_gpuobj_ref(NULL, &bar->pad);
|
||||
nvkm_gpuobj_ref(NULL, &bar->mem);
|
||||
nvkm_bar_destroy(&bar->base);
|
||||
}
|
||||
|
||||
static int
|
||||
nv50_bar_init(struct nvkm_object *object)
|
||||
{
|
||||
struct nv50_bar_priv *priv = (void *)object;
|
||||
struct nv50_bar *bar = (void *)object;
|
||||
int ret, i;
|
||||
|
||||
ret = nvkm_bar_init(&priv->base);
|
||||
ret = nvkm_bar_init(&bar->base);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
nv_mask(priv, 0x000200, 0x00000100, 0x00000000);
|
||||
nv_mask(priv, 0x000200, 0x00000100, 0x00000100);
|
||||
nv_wr32(priv, 0x100c80, 0x00060001);
|
||||
if (!nv_wait(priv, 0x100c80, 0x00000001, 0x00000000)) {
|
||||
nv_error(priv, "vm flush timeout\n");
|
||||
nv_mask(bar, 0x000200, 0x00000100, 0x00000000);
|
||||
nv_mask(bar, 0x000200, 0x00000100, 0x00000100);
|
||||
nv_wr32(bar, 0x100c80, 0x00060001);
|
||||
if (!nv_wait(bar, 0x100c80, 0x00000001, 0x00000000)) {
|
||||
nv_error(bar, "vm flush timeout\n");
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
nv_wr32(priv, 0x001704, 0x00000000 | priv->mem->addr >> 12);
|
||||
nv_wr32(priv, 0x001704, 0x40000000 | priv->mem->addr >> 12);
|
||||
nv_wr32(priv, 0x001708, 0x80000000 | priv->bar1->node->offset >> 4);
|
||||
nv_wr32(priv, 0x00170c, 0x80000000 | priv->bar3->node->offset >> 4);
|
||||
nv_wr32(bar, 0x001704, 0x00000000 | bar->mem->addr >> 12);
|
||||
nv_wr32(bar, 0x001704, 0x40000000 | bar->mem->addr >> 12);
|
||||
nv_wr32(bar, 0x001708, 0x80000000 | bar->bar1->node->offset >> 4);
|
||||
nv_wr32(bar, 0x00170c, 0x80000000 | bar->bar3->node->offset >> 4);
|
||||
for (i = 0; i < 8; i++)
|
||||
nv_wr32(priv, 0x001900 + (i * 4), 0x00000000);
|
||||
nv_wr32(bar, 0x001900 + (i * 4), 0x00000000);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
nv50_bar_fini(struct nvkm_object *object, bool suspend)
|
||||
{
|
||||
struct nv50_bar_priv *priv = (void *)object;
|
||||
return nvkm_bar_fini(&priv->base, suspend);
|
||||
struct nv50_bar *bar = (void *)object;
|
||||
return nvkm_bar_fini(&bar->base, suspend);
|
||||
}
|
||||
|
||||
struct nvkm_oclass
|
||||
|
||||
@ -5,9 +5,9 @@
|
||||
#define nvkm_bar_create(p,e,o,d) \
|
||||
nvkm_bar_create_((p), (e), (o), sizeof(**d), (void **)d)
|
||||
#define nvkm_bar_init(p) \
|
||||
nvkm_subdev_init(&(p)->base)
|
||||
nvkm_subdev_init(&(p)->subdev)
|
||||
#define nvkm_bar_fini(p,s) \
|
||||
nvkm_subdev_fini(&(p)->base, (s))
|
||||
nvkm_subdev_fini(&(p)->subdev, (s))
|
||||
|
||||
int nvkm_bar_create_(struct nvkm_object *, struct nvkm_object *,
|
||||
struct nvkm_oclass *, int, void **);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user