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drm/i915: Stop getting the fault address from RING_FAULT_REG
This register does not contain it. Instead, we have to look into FAULT_TLB_DATA0 & 1
(where, by the way, we can also get the address space).
v2: Right formatting
v3:
- Use 12 (as per the register format) instead of PAGE_SIZE (Chris)
- s/BITS_44_TO_47/HIGHBITS (Chris)
- Right formatting, this time for real
Fixes: b03ec3d67a
("drm/i915: There is only one fault register from GEN8 onwards")
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/1513982329-32191-1-git-send-email-oscar.mateo@intel.com
Reviewed-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
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@ -2287,12 +2287,23 @@ static void gen8_check_and_clear_faults(struct drm_i915_private *dev_priv)
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u32 fault = I915_READ(GEN8_RING_FAULT_REG);
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if (fault & RING_FAULT_VALID) {
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u32 fault_data0, fault_data1;
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u64 fault_addr;
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fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
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fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
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fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
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((u64)fault_data0 << 12);
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DRM_DEBUG_DRIVER("Unexpected fault\n"
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"\tAddr: 0x%08lx\n"
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"\tAddr: 0x%08x_%08x\n"
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"\tAddress space: %s\n"
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"\tEngine ID: %d\n"
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"\tSource ID: %d\n"
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"\tType: %d\n",
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fault & PAGE_MASK,
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upper_32_bits(fault_addr),
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lower_32_bits(fault_addr),
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fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
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GEN8_RING_FAULT_ENGINE_ID(fault),
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RING_FAULT_SRCID(fault),
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RING_FAULT_FAULT_TYPE(fault));
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@ -2489,6 +2489,8 @@ enum i915_power_well_id {
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#define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10)
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#define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14)
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#define FAULT_VA_HIGH_BITS (0xf << 0)
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#define FAULT_GTT_SEL (1 << 4)
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#define FPGA_DBG _MMIO(0x42300)
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#define FPGA_DBG_RM_NOCLAIM (1<<31)
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