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Code

- DT cleanups

Browse Source 
- fix for early use of kzalloc on mt7621 platform
 - cleanups and fixes
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Merge tag 'mips_6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

Pull MIPS updates from Thomas Bogendoerfer:

 - DT cleanups

 - fix for early use of kzalloc on mt7621 platform

 - cleanups and fixes

* tag 'mips_6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (21 commits)
  MIPS: OCTEON: warn only once if deprecated link status is being used
  MIPS: BCM63xx: Add check for NULL for clk in clk_enable
  platform/mips: Adjust Kconfig to keep consistency
  MIPS: OCTEON: cvmx-bootmem: use strscpy() to instead of strncpy()
  MIPS: mscc: jaguar2: Fix pca9545 i2c-mux node names
  mips/pci: use devm_platform_ioremap_resource()
  mips: ralink: mt7621: do not use kzalloc too early
  mips: ralink: mt7621: soc queries and tests as functions
  mips: ralink: mt7621: define MT7621_SYSC_BASE with __iomem
  MIPS: Restore symbol versions for copy_page_cpu and clear_page_cpu
  mips: dts: remove label = "cpu" from DSA dt-binding
  mips: ralink: mt7621: change DSA port labels to generic naming
  mips: ralink: mt7621: fix phy-mode of external phy on GB-PC2
  MIPS: vpe-cmp: fix possible memory leak while module exiting
  MIPS: vpe-mt: fix possible memory leak while module exiting
  dt-bindings: mips: brcm: add Broadcom SoCs bindings
  dt-bindings: mips: add CPU bindings for MIPS architecture
  mips: dts: brcm: bcm7435: add "interrupt-names" for NAND controller
  mips: dts: bcm63268: add TWD block timer
  MIPS: Use "grep -E" instead of "egrep"
  ...
This commit is contained in:
Linus Torvalds 2022-12-12 10:59:13 -08:00
commit 5977aa66c4
25 changed files with 313 additions and 133 deletions
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8
Documentation/devicetree/bindings/mips/brcm/brcm,bmips.txt
View File

@ -1,8 +0,0 @@
* Broadcom MIPS (BMIPS) CPUs
Required properties:
- compatible: "brcm,bmips3300", "brcm,bmips4350", "brcm,bmips4380",
"brcm,bmips5000"
- mips-hpt-frequency: This is common to all CPUs in the system so it lives
under the "cpus" node.

96
Documentation/devicetree/bindings/mips/brcm/soc.yaml Normal file
View File

@ -0,0 +1,96 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mips/brcm/soc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom cable/DSL/settop platforms
maintainers:
- Florian Fainelli <f.fainelli@gmail.com>
description: |
Boards Broadcom cable/DSL/settop SoC shall have the following properties.
The experimental -viper variants are for running Linux on the 3384's
BMIPS4355 cable modem CPU instead of the BMIPS5000 application processor.
properties:
$nodename:
const: '/'
compatible:
enum:
- brcm,bcm3368
- brcm,bcm3384
- brcm,bcm33843
- brcm,bcm3384-viper
- brcm,bcm33843-viper
- brcm,bcm6328
- brcm,bcm6358
- brcm,bcm6362
- brcm,bcm6368
- brcm,bcm63168
- brcm,bcm63268
- brcm,bcm7125
- brcm,bcm7346
- brcm,bcm7358
- brcm,bcm7360
- brcm,bcm7362
- brcm,bcm7420
- brcm,bcm7425
cpus:
type: object
additionalProperties: false
properties:
'#address-cells':
const: 1
'#size-cells':
const: 0
mips-hpt-frequency:
description: MIPS counter high precision timer frequency.
This is common to all CPUs in the system so it lives
under the "cpus" node.
$ref: /schemas/types.yaml#/definitions/uint32
patternProperties:
"^cpu@[0-9]$":
type: object
$ref: /schemas/mips/cpus.yaml#
unevaluatedProperties: false
required:
- mips-hpt-frequency
additionalProperties: true
examples:
- |
/ {
compatible = "brcm,bcm3368";
#address-cells = <1>;
#size-cells = <1>;
model = "Broadcom 3368";
cpus {
#address-cells = <1>;
#size-cells = <0>;
mips-hpt-frequency = <150000000>;
cpu@0 {
compatible = "brcm,bmips4350";
device_type = "cpu";
reg = <0>;
};
cpu@1 {
compatible = "brcm,bmips4350";
device_type = "cpu";
reg = <1>;
};
};
};
...

115
Documentation/devicetree/bindings/mips/cpus.yaml Normal file
View File

@ -0,0 +1,115 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mips/cpus.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MIPS CPUs bindings
maintainers:
- Thomas Bogendoerfer <tsbogend@alpha.franken.de>
- 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
description: |
The device tree allows to describe the layout of CPUs in a system through
the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
defining properties for every CPU.
properties:
compatible:
enum:
- brcm,bmips3300
- brcm,bmips4350
- brcm,bmips4380
- brcm,bmips5000
- brcm,bmips5200
- ingenic,xburst-mxu1.0
- ingenic,xburst-fpu1.0-mxu1.1
- ingenic,xburst-fpu2.0-mxu2.0
- ingenic,xburst2-fpu2.1-mxu2.1-smt
- loongson,gs264
- mips,m14Kc
- mips,mips4Kc
- mips,mips4KEc
- mips,mips24Kc
- mips,mips24KEc
- mips,mips74Kc
- mips,mips1004Kc
- mti,interaptiv
- mti,mips24KEc
- mti,mips14KEc
- mti,mips14Kc
reg:
maxItems: 1
clocks:
maxItems: 1
device_type: true
allOf:
- if:
properties:
compatible:
contains:
enum:
- ingenic,xburst-mxu1.0
- ingenic,xburst-fpu1.0-mxu1.1
- ingenic,xburst-fpu2.0-mxu2.0
- ingenic,xburst2-fpu2.1-mxu2.1-smt
then:
required:
- device_type
- clocks
required:
- compatible
- reg
additionalProperties: false
examples:
- |
cpus {
#size-cells = <0>;
#address-cells = <1>;
cpu@0 {
compatible = "mips,mips1004Kc";
device_type = "cpu";
reg = <0>;
};
cpu@1 {
compatible = "mips,mips1004Kc";
device_type = "cpu";
reg = <1>;
};
};
- |
// Example 2 (Ingenic CPU)
#include <dt-bindings/clock/ingenic,jz4780-cgu.h>
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "ingenic,xburst-fpu1.0-mxu1.1";
device_type = "cpu";
reg = <0>;
clocks = <&cgu JZ4780_CLK_CPU>;
};
cpu@1 {
compatible = "ingenic,xburst-fpu1.0-mxu1.1";
device_type = "cpu";
reg = <1>;
clocks = <&cgu JZ4780_CLK_CORE1>;
};
};
...

69
Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml
View File

@ -1,69 +0,0 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mips/ingenic/ingenic,cpu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Bindings for Ingenic XBurst family CPUs
maintainers:
- 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
description:
Ingenic XBurst family CPUs shall have the following properties.
properties:
compatible:
oneOf:
- description: Ingenic XBurst®1 CPU Cores
enum:
- ingenic,xburst-mxu1.0
- ingenic,xburst-fpu1.0-mxu1.1
- ingenic,xburst-fpu2.0-mxu2.0
- description: Ingenic XBurst®2 CPU Cores
enum:
- ingenic,xburst2-fpu2.1-mxu2.1-smt
reg:
maxItems: 1
clocks:
maxItems: 1
device_type: true
required:
- device_type
- compatible
- reg
- clocks
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/ingenic,jz4780-cgu.h>
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "ingenic,xburst-fpu1.0-mxu1.1";
reg = <0>;
clocks = <&cgu JZ4780_CLK_CPU>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "ingenic,xburst-fpu1.0-mxu1.1";
reg = <1>;
clocks = <&cgu JZ4780_CLK_CORE1>;
};
};
...

2
arch/mips/Makefile
View File

@ -318,7 +318,7 @@ KBUILD_LDFLAGS += -m $(ld-emul)
ifdef CONFIG_MIPS
CHECKFLAGS += $(shell $(CC) $(KBUILD_CFLAGS) -dM -E -x c /dev/null | \
egrep -vw '__GNUC_(MINOR_|PATCHLEVEL_)?_' | \
grep -E -vw '__GNUC_(MINOR_|PATCHLEVEL_)?_' | \
sed -e "s/^\#define /-D'/" -e "s/ /'='/" -e "s/$$/'/" -e 's/\$$/&&/g')
endif

2
arch/mips/bcm63xx/clk.c
View File

@ -361,6 +361,8 @@ static struct clk clk_periph = {
*/
int clk_enable(struct clk *clk)
{
if (!clk)
return 0;
mutex_lock(&clocks_mutex);
clk_enable_unlocked(clk);
mutex_unlock(&clocks_mutex);

5
arch/mips/boot/dts/brcm/bcm63268.dtsi
View File

@ -110,6 +110,11 @@
reg = <0x10000080 0x30>;
ranges = <0x0 0x10000080 0x30>;
timer@0 {
compatible = "brcm,bcm6345-timer";
reg = <0x0 0x1c>;
};
wdt: watchdog@1c {
compatible = "brcm,bcm7038-wdt";
reg = <0x1c 0xc>;

1
arch/mips/boot/dts/brcm/bcm7435.dtsi
View File

@ -422,6 +422,7 @@
reg = <0x41c800 0x600>, <0x41d000 0x100>;
interrupt-parent = <&hif_l2_intc>;
interrupts = <24>, <4>;
interrupt-names = "nand_ctlrdy", "flash_dma_done";
status = "disabled";
};

2
arch/mips/boot/dts/ingenic/ci20.dts
View File

@ -438,7 +438,7 @@
ingenic,nemc-tAW = <50>;
ingenic,nemc-tSTRV = <100>;
reset-gpios = <&gpf 12 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpf 12 GPIO_ACTIVE_LOW>;
vcc-supply = <&eth0_power>;
interrupt-parent = <&gpe>;

4
arch/mips/boot/dts/mscc/jaguar2_pcb110.dts
View File

@ -208,7 +208,7 @@
};
&i2c0 {
pca9545@70 {
i2c-mux@70 {
compatible = "nxp,pca9545";
reg = <0x70>;
#address-cells = <1>;
@ -236,7 +236,7 @@
reg = <3>;
};
};
pca9545@71 {
i2c-mux@71 {
compatible = "nxp,pca9545";
reg = <0x71>;
#address-cells = <1>;

1
arch/mips/boot/dts/qca/ar9331.dtsi
View File

@ -176,7 +176,6 @@
switch_port0: port@0 {
reg = <0x0>;
label = "cpu";
ethernet = <&eth1>;
phy-mode = "gmii";

2
arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc2.dts
View File

@ -113,13 +113,13 @@
&gmac1 {
status = "okay";
phy-mode = "rgmii-rxid";
phy-handle = <&ethphy5>;
};
&mdio {
ethphy5: ethernet-phy@5 {
reg = <5>;
phy-mode = "rgmii-rxid";
};
};

11
arch/mips/boot/dts/ralink/mt7621.dtsi
View File

@ -357,36 +357,35 @@
port@0 {
status = "disabled";
reg = <0>;
label = "lan0";
label = "swp0";
};
port@1 {
status = "disabled";
reg = <1>;
label = "lan1";
label = "swp1";
};
port@2 {
status = "disabled";
reg = <2>;
label = "lan2";
label = "swp2";
};
port@3 {
status = "disabled";
reg = <3>;
label = "lan3";
label = "swp3";
};
port@4 {
status = "disabled";
reg = <4>;
label = "lan4";
label = "swp4";
};
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac0>;
phy-mode = "trgmii";

3
arch/mips/cavium-octeon/executive/cvmx-bootmem.c
View File

@ -780,9 +780,8 @@ int64_t cvmx_bootmem_phy_named_block_alloc(uint64_t size, uint64_t min_addr,
if (addr_allocated >= 0) {
named_block_desc_ptr->base_addr = addr_allocated;
named_block_desc_ptr->size = size;
strncpy(named_block_desc_ptr->name, name,
strscpy(named_block_desc_ptr->name, name,
cvmx_bootmem_desc->named_block_name_len);
named_block_desc_ptr->name[cvmx_bootmem_desc->named_block_name_len - 1] = 0;
}
if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))

2
arch/mips/cavium-octeon/executive/cvmx-helper-board.c
View File

@ -211,7 +211,7 @@ union cvmx_helper_link_info __cvmx_helper_board_link_get(int ipd_port)
{
union cvmx_helper_link_info result;
WARN(!octeon_is_simulation(),
WARN_ONCE(!octeon_is_simulation(),
"Using deprecated link status - please update your DT");
/* Unless we fix it later, all links are defaulted to down */

2
arch/mips/cavium-octeon/executive/cvmx-helper.c
View File

@ -1096,7 +1096,7 @@ union cvmx_helper_link_info cvmx_helper_link_get(int ipd_port)
if (index == 0)
result = __cvmx_helper_rgmii_link_get(ipd_port);
else {
WARN(1, "Using deprecated link status - please update your DT");
WARN_ONCE(1, "Using deprecated link status - please update your DT");
result.s.full_duplex = 1;
result.s.link_up = 1;
result.s.speed = 1000;

3
arch/mips/include/asm/asm-prototypes.h
View File

@ -6,3 +6,6 @@
#include <linux/uaccess.h>
#include <asm/ftrace.h>
#include <asm/mmu_context.h>
extern void clear_page_cpu(void *page);
extern void copy_page_cpu(void *to, void *from);

4
arch/mips/include/asm/mach-ralink/mt7621.h
View File

@ -7,10 +7,12 @@
#ifndef _MT7621_REGS_H_
#define _MT7621_REGS_H_
#define IOMEM(x) ((void __iomem *)(KSEG1ADDR(x)))
#define MT7621_PALMBUS_BASE 0x1C000000
#define MT7621_PALMBUS_SIZE 0x03FFFFFF
#define MT7621_SYSC_BASE 0x1E000000
#define MT7621_SYSC_BASE IOMEM(0x1E000000)
#define SYSC_REG_CHIP_NAME0 0x00
#define SYSC_REG_CHIP_NAME1 0x04

4
arch/mips/kernel/vpe-cmp.c
View File

@ -75,7 +75,6 @@ ATTRIBUTE_GROUPS(vpe);
static void vpe_device_release(struct device *cd)
{
kfree(cd);
}
static struct class vpe_class = {
@ -157,6 +156,7 @@ out_dev:
device_del(&vpe_device);
out_class:
put_device(&vpe_device);
class_unregister(&vpe_class);
out_chrdev:
@ -169,7 +169,7 @@ void __exit vpe_module_exit(void)
{
struct vpe *v, *n;
device_del(&vpe_device);
device_unregister(&vpe_device);
class_unregister(&vpe_class);
unregister_chrdev(major, VPE_MODULE_NAME);

4
arch/mips/kernel/vpe-mt.c
View File

@ -313,7 +313,6 @@ ATTRIBUTE_GROUPS(vpe);
static void vpe_device_release(struct device *cd)
{
kfree(cd);
}
static struct class vpe_class = {
@ -497,6 +496,7 @@ out_dev:
device_del(&vpe_device);
out_class:
put_device(&vpe_device);
class_unregister(&vpe_class);
out_chrdev:
@ -509,7 +509,7 @@ void __exit vpe_module_exit(void)
{
struct vpe *v, *n;
device_del(&vpe_device);
device_unregister(&vpe_device);
class_unregister(&vpe_class);
unregister_chrdev(major, VPE_MODULE_NAME);

4
arch/mips/pci/pci-rt3883.c
View File

@ -404,7 +404,6 @@ static int rt3883_pci_probe(struct platform_device *pdev)
struct rt3883_pci_controller *rpc;
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
struct resource *res;
struct device_node *child;
u32 val;
int err;
@ -414,8 +413,7 @@ static int rt3883_pci_probe(struct platform_device *pdev)
if (!rpc)
return -ENOMEM;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
rpc->base = devm_ioremap_resource(dev, res);
rpc->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(rpc->base))
return PTR_ERR(rpc->base);

97
arch/mips/ralink/mt7621.c
View File

@ -25,6 +25,7 @@
#define MT7621_MEM_TEST_PATTERN 0xaa5555aa
static u32 detect_magic __initdata;
static struct ralink_soc_info *soc_info_ptr;
int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
{
@ -97,41 +98,83 @@ void __init ralink_of_remap(void)
panic("Failed to remap core resources");
}
static void soc_dev_init(struct ralink_soc_info *soc_info, u32 rev)
static unsigned int __init mt7621_get_soc_name0(void)
{
return __raw_readl(MT7621_SYSC_BASE + SYSC_REG_CHIP_NAME0);
}
static unsigned int __init mt7621_get_soc_name1(void)
{
return __raw_readl(MT7621_SYSC_BASE + SYSC_REG_CHIP_NAME1);
}
static bool __init mt7621_soc_valid(void)
{
if (mt7621_get_soc_name0() == MT7621_CHIP_NAME0 &&
mt7621_get_soc_name1() == MT7621_CHIP_NAME1)
return true;
else
return false;
}
static const char __init *mt7621_get_soc_id(void)
{
if (mt7621_soc_valid())
return "MT7621";
else
return "invalid";
}
static unsigned int __init mt7621_get_soc_rev(void)
{
return __raw_readl(MT7621_SYSC_BASE + SYSC_REG_CHIP_REV);
}
static unsigned int __init mt7621_get_soc_ver(void)
{
return (mt7621_get_soc_rev() >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK;
}
static unsigned int __init mt7621_get_soc_eco(void)
{
return (mt7621_get_soc_rev() & CHIP_REV_ECO_MASK);
}
static const char __init *mt7621_get_soc_revision(void)
{
if (mt7621_get_soc_rev() == 1 && mt7621_get_soc_eco() == 1)
return "E2";
else
return "E1";
}
static int __init mt7621_soc_dev_init(void)
{
struct soc_device *soc_dev;
struct soc_device_attribute *soc_dev_attr;
soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
if (!soc_dev_attr)
return;
return -ENOMEM;
soc_dev_attr->soc_id = "mt7621";
soc_dev_attr->family = "Ralink";
soc_dev_attr->revision = mt7621_get_soc_revision();
if (((rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK) == 1 &&
(rev & CHIP_REV_ECO_MASK) == 1)
soc_dev_attr->revision = "E2";
else
soc_dev_attr->revision = "E1";
soc_dev_attr->data = soc_info;
soc_dev_attr->data = soc_info_ptr;
soc_dev = soc_device_register(soc_dev_attr);
if (IS_ERR(soc_dev)) {
kfree(soc_dev_attr);
return;
return PTR_ERR(soc_dev);
}
return 0;
}
device_initcall(mt7621_soc_dev_init);
void __init prom_soc_init(struct ralink_soc_info *soc_info)
{
void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
unsigned char *name = NULL;
u32 n0;
u32 n1;
u32 rev;
/* Early detection of CMP support */
mips_cm_probe();
mips_cpc_probe();
@ -154,27 +197,23 @@ void __init prom_soc_init(struct ralink_soc_info *soc_info)
__sync();
}
n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) {
name = "MT7621";
if (mt7621_soc_valid())
soc_info->compatible = "mediatek,mt7621-soc";
} else {
panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
}
else
panic("mt7621: unknown SoC, n0:%08x n1:%08x\n",
mt7621_get_soc_name0(),
mt7621_get_soc_name1());
ralink_soc = MT762X_SOC_MT7621AT;
rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
"MediaTek %s ver:%u eco:%u",
name,
(rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
(rev & CHIP_REV_ECO_MASK));
mt7621_get_soc_id(),
mt7621_get_soc_ver(),
mt7621_get_soc_eco());
soc_info->mem_detect = mt7621_memory_detect;
soc_dev_init(soc_info, rev);
soc_info_ptr = soc_info;
if (!register_cps_smp_ops())
return;

2
arch/mips/vdso/Makefile
View File

@ -71,7 +71,7 @@ KCOV_INSTRUMENT := n
# Check that we don't have PIC 'jalr t9' calls left
quiet_cmd_vdso_mips_check = VDSOCHK $@
cmd_vdso_mips_check = if $(OBJDUMP) --disassemble $@ | egrep -h "jalr.*t9" > /dev/null; \
cmd_vdso_mips_check = if $(OBJDUMP) --disassemble $@ | grep -E -h "jalr.*t9" > /dev/null; \
then (echo >&2 "$@: PIC 'jalr t9' calls are not supported"; \
rm -f $@; /bin/false); fi

2
drivers/platform/Kconfig
View File

@ -1,7 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-only
if MIPS
source "drivers/platform/mips/Kconfig"
endif
source "drivers/platform/loongarch/Kconfig"

1
drivers/platform/mips/Kconfig
View File

@ -6,6 +6,7 @@
menuconfig MIPS_PLATFORM_DEVICES
bool "MIPS Platform Specific Device Drivers"
default y
depends on MIPS
help
Say Y here to get to see options for device drivers of various
MIPS platforms, including vendor-specific netbook/laptop/desktop