mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-18 18:23:53 +08:00
This is a patch series that:
- Pulls the Integrator/AP PCI bridge driver into one file - Adds full device tree support for it - Keeps ATAG support around for the time being -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.13 (GNU/Linux) iQIcBAABAgAGBQJRvMzZAAoJEEEQszewGV1zUQUQAJbES7DXw+lPSIYaI6MFEFJa SHAD0T3J91ya5chawMC4U5g60734Q8K1k052KpIPNoBBby7spve2zklON8wCVWnj ta5TAzDQy+T5TRMpIap6bhvMJQQw+qvTCbxIYivb4WtaBgByBXfJCyCiKjJ+yX28 KQlyMIqrH8G1GyItC1e4gnUP9KJb9djT51nRL6asvLcD4/Cf9OJadXUCAUmwHDWK PUvZm5R8zDFnwNTh5tIrTuac4rY/vsJd2PLvbsai9hghOwhUT6I+pHpP2snUq+0e 77+K4LnOIbh9nNMATJHgP6iSLjc8ncfPwCGmf27bA968am9arYJMnX8sKFTNms9s n1qvaOQnYclrujX2Sy25PXBc/3FCoVP0e2nNzG3e7fdn3gVQDrmSw1ag7/vTDbS5 kFrWjJFnr6Sxy3FthzTwWGgb4IHIRTZg+MuHjjyf4iSq14IGZoHal9n/GvGL3MUL G5o1lvxXBC9UKYslUmfvYM1yIMzUqSxYs09d96KRHF+XGNnk0GaMgUqfXqFb33JH HocHqevH+WGgach6Qqgop7ZGrdjOe75wDn03yIgM29SL4WKtFbfY0KPySBFqHPd/ RNCwFQZo1N8rhbfB/sCFDVAAZfbbQxomID8p5KAvD0IaVIiE9eLbSgJdDQR0o148 lFhe+9QCIRQkiLmYc+Sf =bzpe -----END PGP SIGNATURE----- Merge tag 'integrator-pci-for-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into next/soc From Linus Walleij: This is a patch series that: - Pulls the Integrator/AP PCI bridge driver into one file - Adds full device tree support for it - Keeps ATAG support around for the time being * tag 'integrator-pci-for-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator: ARM: integrator: basic PCIv3 device tree support ARM: integrator: move static ioremapping into PCIv3 driver ARM: integrator: move VGA base assignment ARM: integrator: remap PCIv3 base dynamically ARM: integrator: move V3 register definitions into driver ARM: integrator: move PCI base address grab to probe ARM: integrator: grab PCI error IRQ in probe() ARM: integrator: convert PCIv3 bridge to platform device ARM: integrator: merge PCIv3 driver into one file ARM: pci: create pci_common_init_dev() Documentation/devicetree: add a small note on PCI Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
commit
596fd95ea6
9
Documentation/devicetree/bindings/pci/pci.txt
Normal file
9
Documentation/devicetree/bindings/pci/pci.txt
Normal file
@ -0,0 +1,9 @@
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PCI bus bridges have standardized Device Tree bindings:
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PCI Bus Binding to: IEEE Std 1275-1994
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http://www.openfirmware.org/ofwg/bindings/pci/pci2_1.pdf
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And for the interrupt mapping part:
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Open Firmware Recommended Practice: Interrupt Mapping
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http://www.openfirmware.org/1275/practice/imap/imap0_9d.pdf
|
15
Documentation/devicetree/bindings/pci/v3-v360epc-pci.txt
Normal file
15
Documentation/devicetree/bindings/pci/v3-v360epc-pci.txt
Normal file
@ -0,0 +1,15 @@
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V3 Semiconductor V360 EPC PCI bridge
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This bridge is found in the ARM Integrator/AP (Application Platform)
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Integrator-specific notes:
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- syscon: should contain a link to the syscon device node (since
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on the Integrator, some registers in the syscon are required to
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operate the V3).
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V360 EPC specific notes:
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- reg: should contain the base address of the V3 adapter.
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- interrupts: should contain a reference to the V3 error interrupt
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as routed on the system.
|
@ -59,6 +59,7 @@ ste ST-Ericsson
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stericsson ST-Ericsson
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ti Texas Instruments
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toshiba Toshiba Corporation
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v3 V3 Semiconductor
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via VIA Technologies, Inc.
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wlf Wolfson Microelectronics
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wm Wondermedia Technologies, Inc.
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|
@ -39,6 +39,47 @@
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valid-mask = <0x003fffff>;
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};
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pci: pciv3@62000000 {
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compatible = "v3,v360epc-pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0x62000000 0x10000>;
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interrupt-parent = <&pic>;
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interrupts = <17>; /* Bus error IRQ */
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ranges = <0x00000000 0 0x61000000 /* config space */
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0x61000000 0 0x00100000 /* 16 MiB @ 61000000 */
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0x01000000 0 0x60000000 /* I/O space */
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0x60000000 0 0x00100000 /* 16 MiB @ 60000000 */
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0x02000000 0 0x40000000 /* non-prefectable memory */
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0x40000000 0 0x10000000 /* 256 MiB @ 40000000 */
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0x42000000 0 0x50000000 /* prefetchable memory */
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0x50000000 0 0x10000000>; /* 256 MiB @ 50000000 */
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interrupt-map-mask = <0xf800 0 0 0x7>;
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interrupt-map = <
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/* IDSEL 9 */
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0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
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0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
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0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
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0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
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/* IDSEL 10 */
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0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
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0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
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0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
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0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
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/* IDSEL 11 */
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0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */
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0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */
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0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */
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0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */
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/* IDSEL 12 */
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0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */
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0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */
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0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */
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0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */
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>;
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};
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fpga {
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/*
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* The Integator/AP predates the idea to have magic numbers
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|
@ -1,186 +0,0 @@
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/*
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* arch/arm/include/asm/hardware/pci_v3.h
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*
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* Internal header file PCI V3 chip
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*
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* Copyright (C) ARM Limited
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* Copyright (C) 2000-2001 Deep Blue Solutions Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
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*
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* This program is distributed in the hope that it will be useful,
|
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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||||
* GNU General Public License for more details.
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||||
*
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* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef ASM_ARM_HARDWARE_PCI_V3_H
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#define ASM_ARM_HARDWARE_PCI_V3_H
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/* -------------------------------------------------------------------------------
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* V3 Local Bus to PCI Bridge definitions
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* -------------------------------------------------------------------------------
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* Registers (these are taken from page 129 of the EPC User's Manual Rev 1.04
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* All V3 register names are prefaced by V3_ to avoid clashing with any other
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* PCI definitions. Their names match the user's manual.
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*
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* I'm assuming that I20 is disabled.
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*
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*/
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#define V3_PCI_VENDOR 0x00000000
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#define V3_PCI_DEVICE 0x00000002
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#define V3_PCI_CMD 0x00000004
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#define V3_PCI_STAT 0x00000006
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#define V3_PCI_CC_REV 0x00000008
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#define V3_PCI_HDR_CFG 0x0000000C
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#define V3_PCI_IO_BASE 0x00000010
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#define V3_PCI_BASE0 0x00000014
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#define V3_PCI_BASE1 0x00000018
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#define V3_PCI_SUB_VENDOR 0x0000002C
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#define V3_PCI_SUB_ID 0x0000002E
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#define V3_PCI_ROM 0x00000030
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#define V3_PCI_BPARAM 0x0000003C
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#define V3_PCI_MAP0 0x00000040
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#define V3_PCI_MAP1 0x00000044
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#define V3_PCI_INT_STAT 0x00000048
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#define V3_PCI_INT_CFG 0x0000004C
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#define V3_LB_BASE0 0x00000054
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#define V3_LB_BASE1 0x00000058
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#define V3_LB_MAP0 0x0000005E
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#define V3_LB_MAP1 0x00000062
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#define V3_LB_BASE2 0x00000064
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#define V3_LB_MAP2 0x00000066
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#define V3_LB_SIZE 0x00000068
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#define V3_LB_IO_BASE 0x0000006E
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#define V3_FIFO_CFG 0x00000070
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#define V3_FIFO_PRIORITY 0x00000072
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#define V3_FIFO_STAT 0x00000074
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#define V3_LB_ISTAT 0x00000076
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#define V3_LB_IMASK 0x00000077
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#define V3_SYSTEM 0x00000078
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#define V3_LB_CFG 0x0000007A
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#define V3_PCI_CFG 0x0000007C
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#define V3_DMA_PCI_ADR0 0x00000080
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#define V3_DMA_PCI_ADR1 0x00000090
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#define V3_DMA_LOCAL_ADR0 0x00000084
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#define V3_DMA_LOCAL_ADR1 0x00000094
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#define V3_DMA_LENGTH0 0x00000088
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#define V3_DMA_LENGTH1 0x00000098
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#define V3_DMA_CSR0 0x0000008B
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#define V3_DMA_CSR1 0x0000009B
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#define V3_DMA_CTLB_ADR0 0x0000008C
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#define V3_DMA_CTLB_ADR1 0x0000009C
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#define V3_DMA_DELAY 0x000000E0
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#define V3_MAIL_DATA 0x000000C0
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#define V3_PCI_MAIL_IEWR 0x000000D0
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#define V3_PCI_MAIL_IERD 0x000000D2
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#define V3_LB_MAIL_IEWR 0x000000D4
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#define V3_LB_MAIL_IERD 0x000000D6
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#define V3_MAIL_WR_STAT 0x000000D8
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#define V3_MAIL_RD_STAT 0x000000DA
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#define V3_QBA_MAP 0x000000DC
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/* PCI COMMAND REGISTER bits
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*/
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#define V3_COMMAND_M_FBB_EN (1 << 9)
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#define V3_COMMAND_M_SERR_EN (1 << 8)
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#define V3_COMMAND_M_PAR_EN (1 << 6)
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#define V3_COMMAND_M_MASTER_EN (1 << 2)
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#define V3_COMMAND_M_MEM_EN (1 << 1)
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#define V3_COMMAND_M_IO_EN (1 << 0)
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/* SYSTEM REGISTER bits
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*/
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#define V3_SYSTEM_M_RST_OUT (1 << 15)
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#define V3_SYSTEM_M_LOCK (1 << 14)
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/* PCI_CFG bits
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*/
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#define V3_PCI_CFG_M_I2O_EN (1 << 15)
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#define V3_PCI_CFG_M_IO_REG_DIS (1 << 14)
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#define V3_PCI_CFG_M_IO_DIS (1 << 13)
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#define V3_PCI_CFG_M_EN3V (1 << 12)
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#define V3_PCI_CFG_M_RETRY_EN (1 << 10)
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#define V3_PCI_CFG_M_AD_LOW1 (1 << 9)
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#define V3_PCI_CFG_M_AD_LOW0 (1 << 8)
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/* PCI_BASE register bits (PCI -> Local Bus)
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*/
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#define V3_PCI_BASE_M_ADR_BASE 0xFFF00000
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#define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00
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#define V3_PCI_BASE_M_PREFETCH (1 << 3)
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#define V3_PCI_BASE_M_TYPE (3 << 1)
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#define V3_PCI_BASE_M_IO (1 << 0)
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/* PCI MAP register bits (PCI -> Local bus)
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*/
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#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000
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#define V3_PCI_MAP_M_RD_POST_INH (1 << 15)
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#define V3_PCI_MAP_M_ROM_SIZE (3 << 10)
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#define V3_PCI_MAP_M_SWAP (3 << 8)
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#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0
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#define V3_PCI_MAP_M_REG_EN (1 << 1)
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#define V3_PCI_MAP_M_ENABLE (1 << 0)
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/*
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* LB_BASE0,1 register bits (Local bus -> PCI)
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*/
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#define V3_LB_BASE_ADR_BASE 0xfff00000
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#define V3_LB_BASE_SWAP (3 << 8)
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#define V3_LB_BASE_ADR_SIZE (15 << 4)
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#define V3_LB_BASE_PREFETCH (1 << 3)
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#define V3_LB_BASE_ENABLE (1 << 0)
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#define V3_LB_BASE_ADR_SIZE_1MB (0 << 4)
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#define V3_LB_BASE_ADR_SIZE_2MB (1 << 4)
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#define V3_LB_BASE_ADR_SIZE_4MB (2 << 4)
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#define V3_LB_BASE_ADR_SIZE_8MB (3 << 4)
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#define V3_LB_BASE_ADR_SIZE_16MB (4 << 4)
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#define V3_LB_BASE_ADR_SIZE_32MB (5 << 4)
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#define V3_LB_BASE_ADR_SIZE_64MB (6 << 4)
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#define V3_LB_BASE_ADR_SIZE_128MB (7 << 4)
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#define V3_LB_BASE_ADR_SIZE_256MB (8 << 4)
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#define V3_LB_BASE_ADR_SIZE_512MB (9 << 4)
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#define V3_LB_BASE_ADR_SIZE_1GB (10 << 4)
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#define V3_LB_BASE_ADR_SIZE_2GB (11 << 4)
|
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|
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#define v3_addr_to_lb_base(a) ((a) & V3_LB_BASE_ADR_BASE)
|
||||
|
||||
/*
|
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* LB_MAP0,1 register bits (Local bus -> PCI)
|
||||
*/
|
||||
#define V3_LB_MAP_MAP_ADR 0xfff0
|
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#define V3_LB_MAP_TYPE (7 << 1)
|
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#define V3_LB_MAP_AD_LOW_EN (1 << 0)
|
||||
|
||||
#define V3_LB_MAP_TYPE_IACK (0 << 1)
|
||||
#define V3_LB_MAP_TYPE_IO (1 << 1)
|
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#define V3_LB_MAP_TYPE_MEM (3 << 1)
|
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#define V3_LB_MAP_TYPE_CONFIG (5 << 1)
|
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#define V3_LB_MAP_TYPE_MEM_MULTIPLE (6 << 1)
|
||||
|
||||
#define v3_addr_to_lb_map(a) (((a) >> 16) & V3_LB_MAP_MAP_ADR)
|
||||
|
||||
/*
|
||||
* LB_BASE2 register bits (Local bus -> PCI IO)
|
||||
*/
|
||||
#define V3_LB_BASE2_ADR_BASE 0xff00
|
||||
#define V3_LB_BASE2_SWAP (3 << 6)
|
||||
#define V3_LB_BASE2_ENABLE (1 << 0)
|
||||
|
||||
#define v3_addr_to_lb_base2(a) (((a) >> 16) & V3_LB_BASE2_ADR_BASE)
|
||||
|
||||
/*
|
||||
* LB_MAP2 register bits (Local bus -> PCI IO)
|
||||
*/
|
||||
#define V3_LB_MAP2_MAP_ADR 0xff00
|
||||
|
||||
#define v3_addr_to_lb_map2(a) (((a) >> 16) & V3_LB_MAP2_MAP_ADR)
|
||||
|
||||
#endif
|
@ -16,6 +16,7 @@
|
||||
struct pci_sys_data;
|
||||
struct pci_ops;
|
||||
struct pci_bus;
|
||||
struct device;
|
||||
|
||||
struct hw_pci {
|
||||
#ifdef CONFIG_PCI_DOMAINS
|
||||
@ -68,7 +69,16 @@ struct pci_sys_data {
|
||||
/*
|
||||
* Call this with your hw_pci struct to initialise the PCI system.
|
||||
*/
|
||||
void pci_common_init(struct hw_pci *);
|
||||
void pci_common_init_dev(struct device *, struct hw_pci *);
|
||||
|
||||
/*
|
||||
* Compatibility wrapper for older platforms that do not care about
|
||||
* passing the parent device.
|
||||
*/
|
||||
static inline void pci_common_init(struct hw_pci *hw)
|
||||
{
|
||||
pci_common_init_dev(NULL, hw);
|
||||
}
|
||||
|
||||
/*
|
||||
* Setup early fixed I/O mapping.
|
||||
@ -96,9 +106,4 @@ extern struct pci_ops via82c505_ops;
|
||||
extern int via82c505_setup(int nr, struct pci_sys_data *);
|
||||
extern void via82c505_init(void *sysdata);
|
||||
|
||||
extern struct pci_ops pci_v3_ops;
|
||||
extern int pci_v3_setup(int nr, struct pci_sys_data *);
|
||||
extern void pci_v3_preinit(void);
|
||||
extern void pci_v3_postinit(void);
|
||||
|
||||
#endif /* __ASM_MACH_PCI_H */
|
||||
|
@ -445,7 +445,8 @@ static int pcibios_init_resources(int busnr, struct pci_sys_data *sys)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void pcibios_init_hw(struct hw_pci *hw, struct list_head *head)
|
||||
static void pcibios_init_hw(struct device *parent, struct hw_pci *hw,
|
||||
struct list_head *head)
|
||||
{
|
||||
struct pci_sys_data *sys = NULL;
|
||||
int ret;
|
||||
@ -480,7 +481,7 @@ static void pcibios_init_hw(struct hw_pci *hw, struct list_head *head)
|
||||
if (hw->scan)
|
||||
sys->bus = hw->scan(nr, sys);
|
||||
else
|
||||
sys->bus = pci_scan_root_bus(NULL, sys->busnr,
|
||||
sys->bus = pci_scan_root_bus(parent, sys->busnr,
|
||||
hw->ops, sys, &sys->resources);
|
||||
|
||||
if (!sys->bus)
|
||||
@ -497,7 +498,7 @@ static void pcibios_init_hw(struct hw_pci *hw, struct list_head *head)
|
||||
}
|
||||
}
|
||||
|
||||
void pci_common_init(struct hw_pci *hw)
|
||||
void pci_common_init_dev(struct device *parent, struct hw_pci *hw)
|
||||
{
|
||||
struct pci_sys_data *sys;
|
||||
LIST_HEAD(head);
|
||||
@ -505,7 +506,7 @@ void pci_common_init(struct hw_pci *hw)
|
||||
pci_add_flags(PCI_REASSIGN_ALL_RSRC);
|
||||
if (hw->preinit)
|
||||
hw->preinit();
|
||||
pcibios_init_hw(hw, &head);
|
||||
pcibios_init_hw(parent, hw, &head);
|
||||
if (hw->postinit)
|
||||
hw->postinit();
|
||||
|
||||
|
@ -8,5 +8,5 @@ obj-y := core.o lm.o leds.o
|
||||
obj-$(CONFIG_ARCH_INTEGRATOR_AP) += integrator_ap.o
|
||||
obj-$(CONFIG_ARCH_INTEGRATOR_CP) += integrator_cp.o
|
||||
|
||||
obj-$(CONFIG_PCI) += pci_v3.o pci.o
|
||||
obj-$(CONFIG_PCI) += pci_v3.o
|
||||
obj-$(CONFIG_INTEGRATOR_IMPD1) += impd1.o
|
||||
|
@ -304,29 +304,6 @@
|
||||
|
||||
/* KMI definitions are now in include/asm-arm/hardware/amba_kmi.h -- rmk */
|
||||
|
||||
/* ------------------------------------------------------------------------
|
||||
* Where in the memory map does PCI live?
|
||||
* ------------------------------------------------------------------------
|
||||
* This represents a fairly liberal usage of address space. Even though
|
||||
* the V3 only has two windows (therefore we need to map stuff on the fly),
|
||||
* we maintain the same addresses, even if they're not mapped.
|
||||
*
|
||||
*/
|
||||
#define PHYS_PCI_MEM_BASE 0x40000000 /* 512M to xxx */
|
||||
/* unused 256M from A0000000-AFFFFFFF might be used for I2O ???
|
||||
*/
|
||||
#define PHYS_PCI_IO_BASE 0x60000000 /* 16M to xxx */
|
||||
/* unused (128-16)M from B1000000-B7FFFFFF
|
||||
*/
|
||||
#define PHYS_PCI_CONFIG_BASE 0x61000000 /* 16M to xxx */
|
||||
/* unused ((128-16)M - 64K) from XXX
|
||||
*/
|
||||
#define PHYS_PCI_V3_BASE 0x62000000
|
||||
|
||||
#define PCI_MEMORY_VADDR IOMEM(0xe8000000)
|
||||
#define PCI_CONFIG_VADDR IOMEM(0xec000000)
|
||||
#define PCI_V3_VADDR IOMEM(0xed000000)
|
||||
|
||||
/* ------------------------------------------------------------------------
|
||||
* Integrator Interrupt Controllers
|
||||
* ------------------------------------------------------------------------
|
||||
|
@ -41,7 +41,6 @@
|
||||
#include <linux/stat.h>
|
||||
#include <linux/sys_soc.h>
|
||||
#include <linux/termios.h>
|
||||
#include <video/vga.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/platform.h>
|
||||
@ -57,10 +56,10 @@
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/irq.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/pci.h>
|
||||
#include <asm/mach/time.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "pci_v3.h"
|
||||
|
||||
/* Base address to the AP system controller */
|
||||
void __iomem *ap_syscon_base;
|
||||
@ -78,10 +77,6 @@ void __iomem *ap_syscon_base;
|
||||
|
||||
/*
|
||||
* Logical Physical
|
||||
* e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M)
|
||||
* ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M)
|
||||
* ed000000 62000000 PCI V3 regs PHYS_PCI_V3_BASE (max 64k)
|
||||
* fee00000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M)
|
||||
* ef000000 Cache flush
|
||||
* f1000000 10000000 Core module registers
|
||||
* f1100000 11000000 System controller registers
|
||||
@ -130,29 +125,13 @@ static struct map_desc ap_io_desc[] __initdata __maybe_unused = {
|
||||
.pfn = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE
|
||||
}, {
|
||||
.virtual = (unsigned long)PCI_MEMORY_VADDR,
|
||||
.pfn = __phys_to_pfn(PHYS_PCI_MEM_BASE),
|
||||
.length = SZ_16M,
|
||||
.type = MT_DEVICE
|
||||
}, {
|
||||
.virtual = (unsigned long)PCI_CONFIG_VADDR,
|
||||
.pfn = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
|
||||
.length = SZ_16M,
|
||||
.type = MT_DEVICE
|
||||
}, {
|
||||
.virtual = (unsigned long)PCI_V3_VADDR,
|
||||
.pfn = __phys_to_pfn(PHYS_PCI_V3_BASE),
|
||||
.length = SZ_64K,
|
||||
.type = MT_DEVICE
|
||||
}
|
||||
};
|
||||
|
||||
static void __init ap_map_io(void)
|
||||
{
|
||||
iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
|
||||
vga_base = (unsigned long)PCI_MEMORY_VADDR;
|
||||
pci_map_io_early(__phys_to_pfn(PHYS_PCI_IO_BASE));
|
||||
pci_v3_early_init();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
@ -615,6 +594,11 @@ static void __init ap_map_io_atag(void)
|
||||
* for eventual deletion.
|
||||
*/
|
||||
|
||||
static struct platform_device pci_v3_device = {
|
||||
.name = "pci-v3",
|
||||
.id = 0,
|
||||
};
|
||||
|
||||
static struct resource cfi_flash_resource = {
|
||||
.start = INTEGRATOR_FLASH_BASE,
|
||||
.end = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
|
||||
@ -672,6 +656,7 @@ static void __init ap_init(void)
|
||||
unsigned long sc_dec;
|
||||
int i;
|
||||
|
||||
platform_device_register(&pci_v3_device);
|
||||
platform_device_register(&cfi_flash_device);
|
||||
|
||||
ap_syscon_base = __io_address(INTEGRATOR_SC_BASE);
|
||||
|
@ -1,113 +0,0 @@
|
||||
/*
|
||||
* linux/arch/arm/mach-integrator/pci-integrator.c
|
||||
*
|
||||
* Copyright (C) 1999 ARM Limited
|
||||
* Copyright (C) 2000 Deep Blue Solutions Ltd
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*
|
||||
*
|
||||
* PCI functions for Integrator
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/init.h>
|
||||
|
||||
#include <asm/mach/pci.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
#include <mach/irqs.h>
|
||||
|
||||
/*
|
||||
* A small note about bridges and interrupts. The DECchip 21050 (and
|
||||
* later) adheres to the PCI-PCI bridge specification. This says that
|
||||
* the interrupts on the other side of a bridge are swizzled in the
|
||||
* following manner:
|
||||
*
|
||||
* Dev Interrupt Interrupt
|
||||
* Pin on Pin on
|
||||
* Device Connector
|
||||
*
|
||||
* 4 A A
|
||||
* B B
|
||||
* C C
|
||||
* D D
|
||||
*
|
||||
* 5 A B
|
||||
* B C
|
||||
* C D
|
||||
* D A
|
||||
*
|
||||
* 6 A C
|
||||
* B D
|
||||
* C A
|
||||
* D B
|
||||
*
|
||||
* 7 A D
|
||||
* B A
|
||||
* C B
|
||||
* D C
|
||||
*
|
||||
* Where A = pin 1, B = pin 2 and so on and pin=0 = default = A.
|
||||
* Thus, each swizzle is ((pin-1) + (device#-4)) % 4
|
||||
*/
|
||||
|
||||
/*
|
||||
* This routine handles multiple bridges.
|
||||
*/
|
||||
static u8 __init integrator_swizzle(struct pci_dev *dev, u8 *pinp)
|
||||
{
|
||||
if (*pinp == 0)
|
||||
*pinp = 1;
|
||||
|
||||
return pci_common_swizzle(dev, pinp);
|
||||
}
|
||||
|
||||
static int irq_tab[4] __initdata = {
|
||||
IRQ_AP_PCIINT0, IRQ_AP_PCIINT1, IRQ_AP_PCIINT2, IRQ_AP_PCIINT3
|
||||
};
|
||||
|
||||
/*
|
||||
* map the specified device/slot/pin to an IRQ. This works out such
|
||||
* that slot 9 pin 1 is INT0, pin 2 is INT1, and slot 10 pin 1 is INT1.
|
||||
*/
|
||||
static int __init integrator_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
|
||||
{
|
||||
int intnr = ((slot - 9) + (pin - 1)) & 3;
|
||||
|
||||
return irq_tab[intnr];
|
||||
}
|
||||
|
||||
extern void pci_v3_init(void *);
|
||||
|
||||
static struct hw_pci integrator_pci __initdata = {
|
||||
.swizzle = integrator_swizzle,
|
||||
.map_irq = integrator_map_irq,
|
||||
.setup = pci_v3_setup,
|
||||
.nr_controllers = 1,
|
||||
.ops = &pci_v3_ops,
|
||||
.preinit = pci_v3_preinit,
|
||||
.postinit = pci_v3_postinit,
|
||||
};
|
||||
|
||||
static int __init integrator_pci_init(void)
|
||||
{
|
||||
if (machine_is_integrator())
|
||||
pci_common_init(&integrator_pci);
|
||||
return 0;
|
||||
}
|
||||
|
||||
subsys_initcall(integrator_pci_init);
|
@ -27,16 +27,198 @@
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_pci.h>
|
||||
#include <video/vga.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/platform.h>
|
||||
#include <mach/irqs.h>
|
||||
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/signal.h>
|
||||
#include <asm/mach/pci.h>
|
||||
#include <asm/irq_regs.h>
|
||||
|
||||
#include <asm/hardware/pci_v3.h>
|
||||
#include "pci_v3.h"
|
||||
|
||||
/*
|
||||
* Where in the memory map does PCI live?
|
||||
*
|
||||
* This represents a fairly liberal usage of address space. Even though
|
||||
* the V3 only has two windows (therefore we need to map stuff on the fly),
|
||||
* we maintain the same addresses, even if they're not mapped.
|
||||
*/
|
||||
#define PHYS_PCI_MEM_BASE 0x40000000 /* 512M */
|
||||
#define PHYS_PCI_IO_BASE 0x60000000 /* 16M */
|
||||
#define PHYS_PCI_CONFIG_BASE 0x61000000 /* 16M */
|
||||
#define PHYS_PCI_V3_BASE 0x62000000 /* 64K */
|
||||
|
||||
#define PCI_MEMORY_VADDR IOMEM(0xe8000000)
|
||||
#define PCI_CONFIG_VADDR IOMEM(0xec000000)
|
||||
|
||||
/*
|
||||
* V3 Local Bus to PCI Bridge definitions
|
||||
*
|
||||
* Registers (these are taken from page 129 of the EPC User's Manual Rev 1.04
|
||||
* All V3 register names are prefaced by V3_ to avoid clashing with any other
|
||||
* PCI definitions. Their names match the user's manual.
|
||||
*
|
||||
* I'm assuming that I20 is disabled.
|
||||
*
|
||||
*/
|
||||
#define V3_PCI_VENDOR 0x00000000
|
||||
#define V3_PCI_DEVICE 0x00000002
|
||||
#define V3_PCI_CMD 0x00000004
|
||||
#define V3_PCI_STAT 0x00000006
|
||||
#define V3_PCI_CC_REV 0x00000008
|
||||
#define V3_PCI_HDR_CFG 0x0000000C
|
||||
#define V3_PCI_IO_BASE 0x00000010
|
||||
#define V3_PCI_BASE0 0x00000014
|
||||
#define V3_PCI_BASE1 0x00000018
|
||||
#define V3_PCI_SUB_VENDOR 0x0000002C
|
||||
#define V3_PCI_SUB_ID 0x0000002E
|
||||
#define V3_PCI_ROM 0x00000030
|
||||
#define V3_PCI_BPARAM 0x0000003C
|
||||
#define V3_PCI_MAP0 0x00000040
|
||||
#define V3_PCI_MAP1 0x00000044
|
||||
#define V3_PCI_INT_STAT 0x00000048
|
||||
#define V3_PCI_INT_CFG 0x0000004C
|
||||
#define V3_LB_BASE0 0x00000054
|
||||
#define V3_LB_BASE1 0x00000058
|
||||
#define V3_LB_MAP0 0x0000005E
|
||||
#define V3_LB_MAP1 0x00000062
|
||||
#define V3_LB_BASE2 0x00000064
|
||||
#define V3_LB_MAP2 0x00000066
|
||||
#define V3_LB_SIZE 0x00000068
|
||||
#define V3_LB_IO_BASE 0x0000006E
|
||||
#define V3_FIFO_CFG 0x00000070
|
||||
#define V3_FIFO_PRIORITY 0x00000072
|
||||
#define V3_FIFO_STAT 0x00000074
|
||||
#define V3_LB_ISTAT 0x00000076
|
||||
#define V3_LB_IMASK 0x00000077
|
||||
#define V3_SYSTEM 0x00000078
|
||||
#define V3_LB_CFG 0x0000007A
|
||||
#define V3_PCI_CFG 0x0000007C
|
||||
#define V3_DMA_PCI_ADR0 0x00000080
|
||||
#define V3_DMA_PCI_ADR1 0x00000090
|
||||
#define V3_DMA_LOCAL_ADR0 0x00000084
|
||||
#define V3_DMA_LOCAL_ADR1 0x00000094
|
||||
#define V3_DMA_LENGTH0 0x00000088
|
||||
#define V3_DMA_LENGTH1 0x00000098
|
||||
#define V3_DMA_CSR0 0x0000008B
|
||||
#define V3_DMA_CSR1 0x0000009B
|
||||
#define V3_DMA_CTLB_ADR0 0x0000008C
|
||||
#define V3_DMA_CTLB_ADR1 0x0000009C
|
||||
#define V3_DMA_DELAY 0x000000E0
|
||||
#define V3_MAIL_DATA 0x000000C0
|
||||
#define V3_PCI_MAIL_IEWR 0x000000D0
|
||||
#define V3_PCI_MAIL_IERD 0x000000D2
|
||||
#define V3_LB_MAIL_IEWR 0x000000D4
|
||||
#define V3_LB_MAIL_IERD 0x000000D6
|
||||
#define V3_MAIL_WR_STAT 0x000000D8
|
||||
#define V3_MAIL_RD_STAT 0x000000DA
|
||||
#define V3_QBA_MAP 0x000000DC
|
||||
|
||||
/* PCI COMMAND REGISTER bits
|
||||
*/
|
||||
#define V3_COMMAND_M_FBB_EN (1 << 9)
|
||||
#define V3_COMMAND_M_SERR_EN (1 << 8)
|
||||
#define V3_COMMAND_M_PAR_EN (1 << 6)
|
||||
#define V3_COMMAND_M_MASTER_EN (1 << 2)
|
||||
#define V3_COMMAND_M_MEM_EN (1 << 1)
|
||||
#define V3_COMMAND_M_IO_EN (1 << 0)
|
||||
|
||||
/* SYSTEM REGISTER bits
|
||||
*/
|
||||
#define V3_SYSTEM_M_RST_OUT (1 << 15)
|
||||
#define V3_SYSTEM_M_LOCK (1 << 14)
|
||||
|
||||
/* PCI_CFG bits
|
||||
*/
|
||||
#define V3_PCI_CFG_M_I2O_EN (1 << 15)
|
||||
#define V3_PCI_CFG_M_IO_REG_DIS (1 << 14)
|
||||
#define V3_PCI_CFG_M_IO_DIS (1 << 13)
|
||||
#define V3_PCI_CFG_M_EN3V (1 << 12)
|
||||
#define V3_PCI_CFG_M_RETRY_EN (1 << 10)
|
||||
#define V3_PCI_CFG_M_AD_LOW1 (1 << 9)
|
||||
#define V3_PCI_CFG_M_AD_LOW0 (1 << 8)
|
||||
|
||||
/* PCI_BASE register bits (PCI -> Local Bus)
|
||||
*/
|
||||
#define V3_PCI_BASE_M_ADR_BASE 0xFFF00000
|
||||
#define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00
|
||||
#define V3_PCI_BASE_M_PREFETCH (1 << 3)
|
||||
#define V3_PCI_BASE_M_TYPE (3 << 1)
|
||||
#define V3_PCI_BASE_M_IO (1 << 0)
|
||||
|
||||
/* PCI MAP register bits (PCI -> Local bus)
|
||||
*/
|
||||
#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000
|
||||
#define V3_PCI_MAP_M_RD_POST_INH (1 << 15)
|
||||
#define V3_PCI_MAP_M_ROM_SIZE (3 << 10)
|
||||
#define V3_PCI_MAP_M_SWAP (3 << 8)
|
||||
#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0
|
||||
#define V3_PCI_MAP_M_REG_EN (1 << 1)
|
||||
#define V3_PCI_MAP_M_ENABLE (1 << 0)
|
||||
|
||||
/*
|
||||
* LB_BASE0,1 register bits (Local bus -> PCI)
|
||||
*/
|
||||
#define V3_LB_BASE_ADR_BASE 0xfff00000
|
||||
#define V3_LB_BASE_SWAP (3 << 8)
|
||||
#define V3_LB_BASE_ADR_SIZE (15 << 4)
|
||||
#define V3_LB_BASE_PREFETCH (1 << 3)
|
||||
#define V3_LB_BASE_ENABLE (1 << 0)
|
||||
|
||||
#define V3_LB_BASE_ADR_SIZE_1MB (0 << 4)
|
||||
#define V3_LB_BASE_ADR_SIZE_2MB (1 << 4)
|
||||
#define V3_LB_BASE_ADR_SIZE_4MB (2 << 4)
|
||||
#define V3_LB_BASE_ADR_SIZE_8MB (3 << 4)
|
||||
#define V3_LB_BASE_ADR_SIZE_16MB (4 << 4)
|
||||
#define V3_LB_BASE_ADR_SIZE_32MB (5 << 4)
|
||||
#define V3_LB_BASE_ADR_SIZE_64MB (6 << 4)
|
||||
#define V3_LB_BASE_ADR_SIZE_128MB (7 << 4)
|
||||
#define V3_LB_BASE_ADR_SIZE_256MB (8 << 4)
|
||||
#define V3_LB_BASE_ADR_SIZE_512MB (9 << 4)
|
||||
#define V3_LB_BASE_ADR_SIZE_1GB (10 << 4)
|
||||
#define V3_LB_BASE_ADR_SIZE_2GB (11 << 4)
|
||||
|
||||
#define v3_addr_to_lb_base(a) ((a) & V3_LB_BASE_ADR_BASE)
|
||||
|
||||
/*
|
||||
* LB_MAP0,1 register bits (Local bus -> PCI)
|
||||
*/
|
||||
#define V3_LB_MAP_MAP_ADR 0xfff0
|
||||
#define V3_LB_MAP_TYPE (7 << 1)
|
||||
#define V3_LB_MAP_AD_LOW_EN (1 << 0)
|
||||
|
||||
#define V3_LB_MAP_TYPE_IACK (0 << 1)
|
||||
#define V3_LB_MAP_TYPE_IO (1 << 1)
|
||||
#define V3_LB_MAP_TYPE_MEM (3 << 1)
|
||||
#define V3_LB_MAP_TYPE_CONFIG (5 << 1)
|
||||
#define V3_LB_MAP_TYPE_MEM_MULTIPLE (6 << 1)
|
||||
|
||||
#define v3_addr_to_lb_map(a) (((a) >> 16) & V3_LB_MAP_MAP_ADR)
|
||||
|
||||
/*
|
||||
* LB_BASE2 register bits (Local bus -> PCI IO)
|
||||
*/
|
||||
#define V3_LB_BASE2_ADR_BASE 0xff00
|
||||
#define V3_LB_BASE2_SWAP (3 << 6)
|
||||
#define V3_LB_BASE2_ENABLE (1 << 0)
|
||||
|
||||
#define v3_addr_to_lb_base2(a) (((a) >> 16) & V3_LB_BASE2_ADR_BASE)
|
||||
|
||||
/*
|
||||
* LB_MAP2 register bits (Local bus -> PCI IO)
|
||||
*/
|
||||
#define V3_LB_MAP2_MAP_ADR 0xff00
|
||||
|
||||
#define v3_addr_to_lb_map2(a) (((a) >> 16) & V3_LB_MAP2_MAP_ADR)
|
||||
|
||||
/*
|
||||
* The V3 PCI interface chip in Integrator provides several windows from
|
||||
@ -101,15 +283,22 @@
|
||||
* the mappings into PCI memory.
|
||||
*/
|
||||
|
||||
/* Filled in by probe */
|
||||
static void __iomem *pci_v3_base;
|
||||
static struct resource conf_mem; /* FIXME: remap this instead of static map */
|
||||
static struct resource io_mem;
|
||||
static struct resource non_mem;
|
||||
static struct resource pre_mem;
|
||||
|
||||
// V3 access routines
|
||||
#define v3_writeb(o,v) __raw_writeb(v, PCI_V3_VADDR + (unsigned int)(o))
|
||||
#define v3_readb(o) (__raw_readb(PCI_V3_VADDR + (unsigned int)(o)))
|
||||
#define v3_writeb(o,v) __raw_writeb(v, pci_v3_base + (unsigned int)(o))
|
||||
#define v3_readb(o) (__raw_readb(pci_v3_base + (unsigned int)(o)))
|
||||
|
||||
#define v3_writew(o,v) __raw_writew(v, PCI_V3_VADDR + (unsigned int)(o))
|
||||
#define v3_readw(o) (__raw_readw(PCI_V3_VADDR + (unsigned int)(o)))
|
||||
#define v3_writew(o,v) __raw_writew(v, pci_v3_base + (unsigned int)(o))
|
||||
#define v3_readw(o) (__raw_readw(pci_v3_base + (unsigned int)(o)))
|
||||
|
||||
#define v3_writel(o,v) __raw_writel(v, PCI_V3_VADDR + (unsigned int)(o))
|
||||
#define v3_readl(o) (__raw_readl(PCI_V3_VADDR + (unsigned int)(o)))
|
||||
#define v3_writel(o,v) __raw_writel(v, pci_v3_base + (unsigned int)(o))
|
||||
#define v3_readl(o) (__raw_readl(pci_v3_base + (unsigned int)(o)))
|
||||
|
||||
/*============================================================================
|
||||
*
|
||||
@ -243,13 +432,13 @@ static void __iomem *v3_open_config_window(struct pci_bus *bus,
|
||||
* prefetchable), this frees up base1 for re-use by
|
||||
* configuration memory
|
||||
*/
|
||||
v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
|
||||
v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(non_mem.start) |
|
||||
V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE);
|
||||
|
||||
/*
|
||||
* Set up base1/map1 to point into configuration space.
|
||||
*/
|
||||
v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_CONFIG_BASE) |
|
||||
v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(conf_mem.start) |
|
||||
V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE);
|
||||
v3_writew(V3_LB_MAP1, mapaddress);
|
||||
|
||||
@ -261,7 +450,7 @@ static void v3_close_config_window(void)
|
||||
/*
|
||||
* Reassign base1 for use by prefetchable PCI memory
|
||||
*/
|
||||
v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) |
|
||||
v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(pre_mem.start) |
|
||||
V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
|
||||
V3_LB_BASE_ENABLE);
|
||||
v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) |
|
||||
@ -270,7 +459,7 @@ static void v3_close_config_window(void)
|
||||
/*
|
||||
* And shrink base0 back to a 256M window (NOTE: MAP0 already correct)
|
||||
*/
|
||||
v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
|
||||
v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(non_mem.start) |
|
||||
V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
|
||||
}
|
||||
|
||||
@ -337,25 +526,11 @@ static int v3_write_config(struct pci_bus *bus, unsigned int devfn, int where,
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
struct pci_ops pci_v3_ops = {
|
||||
static struct pci_ops pci_v3_ops = {
|
||||
.read = v3_read_config,
|
||||
.write = v3_write_config,
|
||||
};
|
||||
|
||||
static struct resource non_mem = {
|
||||
.name = "PCI non-prefetchable",
|
||||
.start = PHYS_PCI_MEM_BASE + PCI_BUS_NONMEM_START,
|
||||
.end = PHYS_PCI_MEM_BASE + PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
};
|
||||
|
||||
static struct resource pre_mem = {
|
||||
.name = "PCI prefetchable",
|
||||
.start = PHYS_PCI_MEM_BASE + PCI_BUS_PREMEM_START,
|
||||
.end = PHYS_PCI_MEM_BASE + PCI_BUS_PREMEM_START + PCI_BUS_PREMEM_SIZE - 1,
|
||||
.flags = IORESOURCE_MEM | IORESOURCE_PREFETCH,
|
||||
};
|
||||
|
||||
static int __init pci_v3_setup_resources(struct pci_sys_data *sys)
|
||||
{
|
||||
if (request_resource(&iomem_resource, &non_mem)) {
|
||||
@ -471,7 +646,7 @@ static irqreturn_t v3_irq(int dummy, void *devid)
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
|
||||
static int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
@ -479,7 +654,7 @@ int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
|
||||
return -EINVAL;
|
||||
|
||||
if (nr == 0) {
|
||||
sys->mem_offset = PHYS_PCI_MEM_BASE;
|
||||
sys->mem_offset = non_mem.start;
|
||||
ret = pci_v3_setup_resources(sys);
|
||||
}
|
||||
|
||||
@ -490,18 +665,10 @@ int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
|
||||
* V3_LB_BASE? - local bus address
|
||||
* V3_LB_MAP? - pci bus address
|
||||
*/
|
||||
void __init pci_v3_preinit(void)
|
||||
static void __init pci_v3_preinit(void)
|
||||
{
|
||||
unsigned long flags;
|
||||
unsigned int temp;
|
||||
int ret;
|
||||
|
||||
/* Remap the Integrator system controller */
|
||||
ap_syscon_base = ioremap(INTEGRATOR_SC_BASE, 0x100);
|
||||
if (!ap_syscon_base) {
|
||||
pr_err("unable to remap the AP syscon for PCIv3\n");
|
||||
return;
|
||||
}
|
||||
|
||||
pcibios_min_mem = 0x00100000;
|
||||
|
||||
@ -525,7 +692,7 @@ void __init pci_v3_preinit(void)
|
||||
* Setup window 0 - PCI non-prefetchable memory
|
||||
* Local: 0x40000000 Bus: 0x00000000 Size: 256MB
|
||||
*/
|
||||
v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
|
||||
v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(non_mem.start) |
|
||||
V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
|
||||
v3_writew(V3_LB_MAP0, v3_addr_to_lb_map(PCI_BUS_NONMEM_START) |
|
||||
V3_LB_MAP_TYPE_MEM);
|
||||
@ -534,7 +701,7 @@ void __init pci_v3_preinit(void)
|
||||
* Setup window 1 - PCI prefetchable memory
|
||||
* Local: 0x50000000 Bus: 0x10000000 Size: 256MB
|
||||
*/
|
||||
v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) |
|
||||
v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(pre_mem.start) |
|
||||
V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
|
||||
V3_LB_BASE_ENABLE);
|
||||
v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) |
|
||||
@ -543,7 +710,7 @@ void __init pci_v3_preinit(void)
|
||||
/*
|
||||
* Setup window 2 - PCI IO
|
||||
*/
|
||||
v3_writel(V3_LB_BASE2, v3_addr_to_lb_base2(PHYS_PCI_IO_BASE) |
|
||||
v3_writel(V3_LB_BASE2, v3_addr_to_lb_base2(io_mem.start) |
|
||||
V3_LB_BASE_ENABLE);
|
||||
v3_writew(V3_LB_MAP2, v3_addr_to_lb_map2(0));
|
||||
|
||||
@ -578,18 +745,10 @@ void __init pci_v3_preinit(void)
|
||||
v3_writeb(V3_LB_IMASK, 0x28);
|
||||
__raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET);
|
||||
|
||||
/*
|
||||
* Grab the PCI error interrupt.
|
||||
*/
|
||||
ret = request_irq(IRQ_AP_V3INT, v3_irq, 0, "V3", NULL);
|
||||
if (ret)
|
||||
printk(KERN_ERR "PCI: unable to grab PCI error "
|
||||
"interrupt: %d\n", ret);
|
||||
|
||||
raw_spin_unlock_irqrestore(&v3_lock, flags);
|
||||
}
|
||||
|
||||
void __init pci_v3_postinit(void)
|
||||
static void __init pci_v3_postinit(void)
|
||||
{
|
||||
unsigned int pci_cmd;
|
||||
|
||||
@ -608,5 +767,278 @@ void __init pci_v3_postinit(void)
|
||||
"interrupt: %d\n", ret);
|
||||
#endif
|
||||
|
||||
register_isa_ports(PHYS_PCI_MEM_BASE, PHYS_PCI_IO_BASE, 0);
|
||||
register_isa_ports(non_mem.start, io_mem.start, 0);
|
||||
}
|
||||
|
||||
/*
|
||||
* A small note about bridges and interrupts. The DECchip 21050 (and
|
||||
* later) adheres to the PCI-PCI bridge specification. This says that
|
||||
* the interrupts on the other side of a bridge are swizzled in the
|
||||
* following manner:
|
||||
*
|
||||
* Dev Interrupt Interrupt
|
||||
* Pin on Pin on
|
||||
* Device Connector
|
||||
*
|
||||
* 4 A A
|
||||
* B B
|
||||
* C C
|
||||
* D D
|
||||
*
|
||||
* 5 A B
|
||||
* B C
|
||||
* C D
|
||||
* D A
|
||||
*
|
||||
* 6 A C
|
||||
* B D
|
||||
* C A
|
||||
* D B
|
||||
*
|
||||
* 7 A D
|
||||
* B A
|
||||
* C B
|
||||
* D C
|
||||
*
|
||||
* Where A = pin 1, B = pin 2 and so on and pin=0 = default = A.
|
||||
* Thus, each swizzle is ((pin-1) + (device#-4)) % 4
|
||||
*/
|
||||
|
||||
/*
|
||||
* This routine handles multiple bridges.
|
||||
*/
|
||||
static u8 __init pci_v3_swizzle(struct pci_dev *dev, u8 *pinp)
|
||||
{
|
||||
if (*pinp == 0)
|
||||
*pinp = 1;
|
||||
|
||||
return pci_common_swizzle(dev, pinp);
|
||||
}
|
||||
|
||||
static int irq_tab[4] __initdata = {
|
||||
IRQ_AP_PCIINT0, IRQ_AP_PCIINT1, IRQ_AP_PCIINT2, IRQ_AP_PCIINT3
|
||||
};
|
||||
|
||||
/*
|
||||
* map the specified device/slot/pin to an IRQ. This works out such
|
||||
* that slot 9 pin 1 is INT0, pin 2 is INT1, and slot 10 pin 1 is INT1.
|
||||
*/
|
||||
static int __init pci_v3_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
|
||||
{
|
||||
int intnr = ((slot - 9) + (pin - 1)) & 3;
|
||||
|
||||
return irq_tab[intnr];
|
||||
}
|
||||
|
||||
static struct hw_pci pci_v3 __initdata = {
|
||||
.swizzle = pci_v3_swizzle,
|
||||
.setup = pci_v3_setup,
|
||||
.nr_controllers = 1,
|
||||
.ops = &pci_v3_ops,
|
||||
.preinit = pci_v3_preinit,
|
||||
.postinit = pci_v3_postinit,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
|
||||
static int __init pci_v3_map_irq_dt(const struct pci_dev *dev, u8 slot, u8 pin)
|
||||
{
|
||||
struct of_irq oirq;
|
||||
int ret;
|
||||
|
||||
ret = of_irq_map_pci(dev, &oirq);
|
||||
if (ret) {
|
||||
dev_err(&dev->dev, "of_irq_map_pci() %d\n", ret);
|
||||
/* Proper return code 0 == NO_IRQ */
|
||||
return 0;
|
||||
}
|
||||
|
||||
return irq_create_of_mapping(oirq.controller, oirq.specifier,
|
||||
oirq.size);
|
||||
}
|
||||
|
||||
static int __init pci_v3_dtprobe(struct platform_device *pdev,
|
||||
struct device_node *np)
|
||||
{
|
||||
struct of_pci_range_parser parser;
|
||||
struct of_pci_range range;
|
||||
struct resource *res;
|
||||
int irq, ret;
|
||||
|
||||
if (of_pci_range_parser_init(&parser, np))
|
||||
return -EINVAL;
|
||||
|
||||
/* Get base for bridge registers */
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res) {
|
||||
dev_err(&pdev->dev, "unable to obtain PCIv3 base\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
pci_v3_base = devm_ioremap(&pdev->dev, res->start,
|
||||
resource_size(res));
|
||||
if (!pci_v3_base) {
|
||||
dev_err(&pdev->dev, "unable to remap PCIv3 base\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* Get and request error IRQ resource */
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq <= 0) {
|
||||
dev_err(&pdev->dev, "unable to obtain PCIv3 error IRQ\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
ret = devm_request_irq(&pdev->dev, irq, v3_irq, 0,
|
||||
"PCIv3 error", NULL);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "unable to request PCIv3 error IRQ %d (%d)\n", irq, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
for_each_of_pci_range(&parser, &range) {
|
||||
if (!range.flags) {
|
||||
of_pci_range_to_resource(&range, np, &conf_mem);
|
||||
conf_mem.name = "PCIv3 config";
|
||||
}
|
||||
if (range.flags & IORESOURCE_IO) {
|
||||
of_pci_range_to_resource(&range, np, &io_mem);
|
||||
io_mem.name = "PCIv3 I/O";
|
||||
}
|
||||
if ((range.flags & IORESOURCE_MEM) &&
|
||||
!(range.flags & IORESOURCE_PREFETCH)) {
|
||||
of_pci_range_to_resource(&range, np, &non_mem);
|
||||
non_mem.name = "PCIv3 non-prefetched mem";
|
||||
}
|
||||
if ((range.flags & IORESOURCE_MEM) &&
|
||||
(range.flags & IORESOURCE_PREFETCH)) {
|
||||
of_pci_range_to_resource(&range, np, &pre_mem);
|
||||
pre_mem.name = "PCIv3 prefetched mem";
|
||||
}
|
||||
}
|
||||
|
||||
if (!conf_mem.start || !io_mem.start ||
|
||||
!non_mem.start || !pre_mem.start) {
|
||||
dev_err(&pdev->dev, "missing ranges in device node\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
pci_v3.map_irq = pci_v3_map_irq_dt;
|
||||
pci_common_init_dev(&pdev->dev, &pci_v3);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
static inline int pci_v3_dtprobe(struct platform_device *pdev,
|
||||
struct device_node *np)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
static int __init pci_v3_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
int ret;
|
||||
|
||||
/* Remap the Integrator system controller */
|
||||
ap_syscon_base = ioremap(INTEGRATOR_SC_BASE, 0x100);
|
||||
if (!ap_syscon_base) {
|
||||
dev_err(&pdev->dev, "unable to remap the AP syscon for PCIv3\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* Device tree probe path */
|
||||
if (np)
|
||||
return pci_v3_dtprobe(pdev, np);
|
||||
|
||||
pci_v3_base = devm_ioremap(&pdev->dev, PHYS_PCI_V3_BASE, SZ_64K);
|
||||
if (!pci_v3_base) {
|
||||
dev_err(&pdev->dev, "unable to remap PCIv3 base\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
ret = devm_request_irq(&pdev->dev, IRQ_AP_V3INT, v3_irq, 0, "V3", NULL);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "unable to grab PCI error interrupt: %d\n",
|
||||
ret);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
conf_mem.name = "PCIv3 config";
|
||||
conf_mem.start = PHYS_PCI_CONFIG_BASE;
|
||||
conf_mem.end = PHYS_PCI_CONFIG_BASE + SZ_16M - 1;
|
||||
conf_mem.flags = IORESOURCE_MEM;
|
||||
|
||||
io_mem.name = "PCIv3 I/O";
|
||||
io_mem.start = PHYS_PCI_IO_BASE;
|
||||
io_mem.end = PHYS_PCI_IO_BASE + SZ_16M - 1;
|
||||
io_mem.flags = IORESOURCE_MEM;
|
||||
|
||||
non_mem.name = "PCIv3 non-prefetched mem";
|
||||
non_mem.start = PHYS_PCI_MEM_BASE + PCI_BUS_NONMEM_START;
|
||||
non_mem.end = PHYS_PCI_MEM_BASE + PCI_BUS_NONMEM_START +
|
||||
PCI_BUS_NONMEM_SIZE - 1;
|
||||
non_mem.flags = IORESOURCE_MEM;
|
||||
|
||||
pre_mem.name = "PCIv3 prefetched mem";
|
||||
pre_mem.start = PHYS_PCI_MEM_BASE + PCI_BUS_PREMEM_START;
|
||||
pre_mem.end = PHYS_PCI_MEM_BASE + PCI_BUS_PREMEM_START +
|
||||
PCI_BUS_PREMEM_SIZE - 1;
|
||||
pre_mem.flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
|
||||
|
||||
pci_v3.map_irq = pci_v3_map_irq;
|
||||
|
||||
pci_common_init_dev(&pdev->dev, &pci_v3);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id pci_ids[] = {
|
||||
{ .compatible = "v3,v360epc-pci", },
|
||||
{},
|
||||
};
|
||||
|
||||
static struct platform_driver pci_v3_driver = {
|
||||
.driver = {
|
||||
.name = "pci-v3",
|
||||
.of_match_table = pci_ids,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init pci_v3_init(void)
|
||||
{
|
||||
return platform_driver_probe(&pci_v3_driver, pci_v3_probe);
|
||||
}
|
||||
|
||||
subsys_initcall(pci_v3_init);
|
||||
|
||||
/*
|
||||
* Static mappings for the PCIv3 bridge
|
||||
*
|
||||
* e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M)
|
||||
* ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M)
|
||||
* fee00000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M)
|
||||
*/
|
||||
static struct map_desc pci_v3_io_desc[] __initdata __maybe_unused = {
|
||||
{
|
||||
.virtual = (unsigned long)PCI_MEMORY_VADDR,
|
||||
.pfn = __phys_to_pfn(PHYS_PCI_MEM_BASE),
|
||||
.length = SZ_16M,
|
||||
.type = MT_DEVICE
|
||||
}, {
|
||||
.virtual = (unsigned long)PCI_CONFIG_VADDR,
|
||||
.pfn = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
|
||||
.length = SZ_16M,
|
||||
.type = MT_DEVICE
|
||||
}
|
||||
};
|
||||
|
||||
int __init pci_v3_early_init(void)
|
||||
{
|
||||
iotable_init(pci_v3_io_desc, ARRAY_SIZE(pci_v3_io_desc));
|
||||
vga_base = (unsigned long)PCI_MEMORY_VADDR;
|
||||
pci_map_io_early(__phys_to_pfn(PHYS_PCI_IO_BASE));
|
||||
return 0;
|
||||
}
|
||||
|
2
arch/arm/mach-integrator/pci_v3.h
Normal file
2
arch/arm/mach-integrator/pci_v3.h
Normal file
@ -0,0 +1,2 @@
|
||||
/* Simple oneliner include to the PCIv3 early init */
|
||||
extern int pci_v3_early_init(void);
|
Loading…
Reference in New Issue
Block a user