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drm/msm/disp/dpu1: add support for display for SC7280 target
Add required display hw catalog changes for SC7280 target. Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org> Link: https://lore.kernel.org/r/1617685792-14376-2-git-send-email-mkrishn@codeaurora.org Signed-off-by: Rob Clark <robdclark@chromium.org>
This commit is contained in:
Krishna Manikandan
Rob Clark
parent
63f17ef834
commit
591e34a091
@ -43,6 +43,9 @@
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#define PINGPONG_SDM845_SPLIT_MASK \
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(PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2))
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#define CTL_SC7280_MASK \
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(BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE))
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#define MERGE_3D_SM8150_MASK (0)
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#define DSPP_SC7180_MASK BIT(DPU_DSPP_PCC)
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@ -51,6 +54,8 @@
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#define INTF_SC7180_MASK BIT(DPU_INTF_INPUT_CTRL) | BIT(DPU_INTF_TE)
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#define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN)
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#define DEFAULT_PIXEL_RAM_SIZE (50 * 1024)
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#define DEFAULT_DPU_LINE_WIDTH 2048
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#define DEFAULT_DPU_OUTPUT_LINE_WIDTH 2560
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@ -199,6 +204,18 @@ static const struct dpu_caps sm8250_dpu_caps = {
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.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
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};
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static const struct dpu_caps sc7280_dpu_caps = {
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.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
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.max_mixer_blendstages = 0x7,
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.qseed_type = DPU_SSPP_SCALER_QSEED4,
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.smart_dma_rev = DPU_SSPP_SMART_DMA_V2,
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.ubwc_version = DPU_HW_UBWC_VER_30,
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.has_dim_layer = true,
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.has_idle_pc = true,
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.max_linewidth = 2400,
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.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
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};
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static const struct dpu_mdp_cfg sdm845_mdp[] = {
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{
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.name = "top_0", .id = MDP_TOP,
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@ -268,6 +285,22 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = {
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},
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};
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static const struct dpu_mdp_cfg sc7280_mdp[] = {
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{
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.name = "top_0", .id = MDP_TOP,
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.base = 0x0, .len = 0x2014,
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.highest_bank_bit = 0x1,
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.clk_ctrls[DPU_CLK_CTRL_VIG0] = {
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.reg_off = 0x2AC, .bit_off = 0},
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.clk_ctrls[DPU_CLK_CTRL_DMA0] = {
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.reg_off = 0x2AC, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
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.reg_off = 0x2B4, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
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.reg_off = 0x2C4, .bit_off = 8},
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},
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};
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/*************************************************************
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* CTL sub blocks config
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*************************************************************/
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@ -350,6 +383,29 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = {
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},
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};
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static const struct dpu_ctl_cfg sc7280_ctl[] = {
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{
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.name = "ctl_0", .id = CTL_0,
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.base = 0x15000, .len = 0x1E8,
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.features = CTL_SC7280_MASK
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},
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{
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.name = "ctl_1", .id = CTL_1,
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.base = 0x16000, .len = 0x1E8,
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.features = CTL_SC7280_MASK
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},
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{
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.name = "ctl_2", .id = CTL_2,
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.base = 0x17000, .len = 0x1E8,
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.features = CTL_SC7280_MASK
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},
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{
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.name = "ctl_3", .id = CTL_3,
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.base = 0x18000, .len = 0x1E8,
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.features = CTL_SC7280_MASK
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},
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};
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/*************************************************************
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* SSPP sub blocks config
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*************************************************************/
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@ -475,6 +531,17 @@ static const struct dpu_sspp_cfg sm8250_sspp[] = {
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sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
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};
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static const struct dpu_sspp_cfg sc7280_sspp[] = {
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SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK,
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sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
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SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
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sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
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SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_CURSOR_SDM845_MASK,
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sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
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SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
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sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
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};
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/*************************************************************
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* MIXER sub blocks config
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*************************************************************/
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@ -550,6 +617,15 @@ static const struct dpu_lm_cfg sm8150_lm[] = {
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&sdm845_lm_sblk, PINGPONG_5, LM_4, 0),
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};
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static const struct dpu_lm_cfg sc7280_lm[] = {
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LM_BLK("lm_0", LM_0, 0x44000, MIXER_SC7180_MASK,
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&sc7180_lm_sblk, PINGPONG_0, 0, 0),
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LM_BLK("lm_2", LM_2, 0x46000, MIXER_SC7180_MASK,
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&sc7180_lm_sblk, PINGPONG_2, LM_3, 0),
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LM_BLK("lm_3", LM_3, 0x47000, MIXER_SC7180_MASK,
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&sc7180_lm_sblk, PINGPONG_3, LM_2, 0),
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};
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/*************************************************************
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* DSPP sub blocks config
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*************************************************************/
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@ -602,42 +678,47 @@ static const struct dpu_pingpong_sub_blks sdm845_pp_sblk = {
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.len = 0x20, .version = 0x10000},
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};
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#define PP_BLK_TE(_name, _id, _base, _merge_3d) \
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static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = {
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.dither = {.id = DPU_PINGPONG_DITHER, .base = 0xe0,
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.len = 0x20, .version = 0x20000},
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};
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#define PP_BLK_TE(_name, _id, _base, _merge_3d, _sblk) \
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{\
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.name = _name, .id = _id, \
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.base = _base, .len = 0xd4, \
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.features = PINGPONG_SDM845_SPLIT_MASK, \
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.merge_3d = _merge_3d, \
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.sblk = &sdm845_pp_sblk_te \
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.sblk = &_sblk \
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}
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#define PP_BLK(_name, _id, _base, _merge_3d) \
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#define PP_BLK(_name, _id, _base, _merge_3d, _sblk) \
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{\
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.name = _name, .id = _id, \
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.base = _base, .len = 0xd4, \
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.features = PINGPONG_SDM845_MASK, \
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.merge_3d = _merge_3d, \
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.sblk = &sdm845_pp_sblk \
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.sblk = &_sblk \
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}
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static const struct dpu_pingpong_cfg sdm845_pp[] = {
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PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0),
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PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0),
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PP_BLK("pingpong_2", PINGPONG_2, 0x71000, 0),
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PP_BLK("pingpong_3", PINGPONG_3, 0x71800, 0),
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PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te),
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PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te),
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PP_BLK("pingpong_2", PINGPONG_2, 0x71000, 0, sdm845_pp_sblk),
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PP_BLK("pingpong_3", PINGPONG_3, 0x71800, 0, sdm845_pp_sblk),
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};
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static struct dpu_pingpong_cfg sc7180_pp[] = {
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PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0),
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PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0),
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PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te),
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PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te),
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};
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static const struct dpu_pingpong_cfg sm8150_pp[] = {
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PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0),
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PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0),
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PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1),
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PP_BLK("pingpong_3", PINGPONG_3, 0x71800, MERGE_3D_1),
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PP_BLK("pingpong_4", PINGPONG_4, 0x72000, MERGE_3D_2),
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PP_BLK("pingpong_5", PINGPONG_5, 0x72800, MERGE_3D_2),
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PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk_te),
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PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk_te),
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PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, sdm845_pp_sblk),
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PP_BLK("pingpong_3", PINGPONG_3, 0x71800, MERGE_3D_1, sdm845_pp_sblk),
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PP_BLK("pingpong_4", PINGPONG_4, 0x72000, MERGE_3D_2, sdm845_pp_sblk),
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PP_BLK("pingpong_5", PINGPONG_5, 0x72800, MERGE_3D_2, sdm845_pp_sblk),
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};
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/*************************************************************
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@ -657,6 +738,12 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = {
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MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200),
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};
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static const struct dpu_pingpong_cfg sc7280_pp[] = {
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PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk),
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PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk),
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PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk),
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PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk),
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};
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/*************************************************************
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* INTF sub blocks config
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*************************************************************/
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@ -689,6 +776,12 @@ static const struct dpu_intf_cfg sm8150_intf[] = {
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INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SC7180_MASK),
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};
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static const struct dpu_intf_cfg sc7280_intf[] = {
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INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, 0, 24, INTF_SC7280_MASK),
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INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK),
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INTF_BLK("intf_5", INTF_5, 0x39000, INTF_EDP, 0, 24, INTF_SC7280_MASK),
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};
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/*************************************************************
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* VBIF sub blocks config
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*************************************************************/
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@ -904,6 +997,33 @@ static const struct dpu_perf_cfg sm8250_perf_data = {
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.bw_inefficiency_factor = 120,
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};
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static const struct dpu_perf_cfg sc7280_perf_data = {
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.max_bw_low = 4700000,
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.max_bw_high = 8800000,
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.min_core_ib = 2500000,
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.min_llcc_ib = 0,
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.min_dram_ib = 1600000,
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.min_prefill_lines = 24,
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.danger_lut_tbl = {0xffff, 0xffff, 0x0},
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.qos_lut_tbl = {
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{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
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.entries = sc7180_qos_macrotile
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},
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{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
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.entries = sc7180_qos_macrotile
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},
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{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
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.entries = sc7180_qos_nrt
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},
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},
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.cdp_cfg = {
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{.rd_enable = 1, .wr_enable = 1},
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{.rd_enable = 1, .wr_enable = 0}
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},
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.clk_inefficiency_factor = 105,
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.bw_inefficiency_factor = 120,
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};
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/*************************************************************
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* Hardware catalog init
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*************************************************************/
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@ -1034,6 +1154,29 @@ static void sm8250_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
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};
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}
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static void sc7280_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
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{
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*dpu_cfg = (struct dpu_mdss_cfg){
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.caps = &sc7280_dpu_caps,
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.mdp_count = ARRAY_SIZE(sc7280_mdp),
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.mdp = sc7280_mdp,
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.ctl_count = ARRAY_SIZE(sc7280_ctl),
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.ctl = sc7280_ctl,
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.sspp_count = ARRAY_SIZE(sc7280_sspp),
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.sspp = sc7280_sspp,
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.mixer_count = ARRAY_SIZE(sc7280_lm),
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.mixer = sc7280_lm,
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.pingpong_count = ARRAY_SIZE(sc7280_pp),
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.pingpong = sc7280_pp,
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.intf_count = ARRAY_SIZE(sc7280_intf),
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.intf = sc7280_intf,
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.vbif_count = ARRAY_SIZE(sdm845_vbif),
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.vbif = sdm845_vbif,
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.perf = sc7280_perf_data,
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.mdss_irqs = 0x1c07,
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};
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}
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static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = {
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{ .hw_rev = DPU_HW_VER_400, .cfg_init = sdm845_cfg_init},
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{ .hw_rev = DPU_HW_VER_401, .cfg_init = sdm845_cfg_init},
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@ -1041,6 +1184,7 @@ static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = {
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{ .hw_rev = DPU_HW_VER_501, .cfg_init = sm8150_cfg_init},
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{ .hw_rev = DPU_HW_VER_600, .cfg_init = sm8250_cfg_init},
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{ .hw_rev = DPU_HW_VER_620, .cfg_init = sc7180_cfg_init},
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{ .hw_rev = DPU_HW_VER_720, .cfg_init = sc7280_cfg_init},
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};
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void dpu_hw_catalog_deinit(struct dpu_mdss_cfg *dpu_cfg)
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@ -41,7 +41,7 @@
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#define DPU_HW_VER_501 DPU_HW_VER(5, 0, 1) /* sm8150 v2.0 */
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#define DPU_HW_VER_600 DPU_HW_VER(6, 0, 0) /* sm8250 */
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#define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */
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#define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */
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#define IS_MSM8996_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_170)
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#define IS_MSM8998_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_300)
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@ -49,7 +49,7 @@
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#define IS_SDM670_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_410)
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#define IS_SDM855_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_500)
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#define IS_SC7180_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_620)
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#define IS_SC7280_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_720)
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#define DPU_HW_BLK_NAME_LEN 16
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@ -185,6 +185,7 @@ enum {
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enum {
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DPU_CTL_SPLIT_DISPLAY = 0x1,
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DPU_CTL_ACTIVE_CFG,
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DPU_CTL_FETCH_ACTIVE,
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DPU_CTL_MAX
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};
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@ -193,11 +194,14 @@ enum {
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* @DPU_INTF_INPUT_CTRL Supports the setting of pp block from which
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* pixel data arrives to this INTF
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* @DPU_INTF_TE INTF block has TE configuration support
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* @DPU_DATA_HCTL_EN Allows data to be transferred at different rate
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than video timing
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* @DPU_INTF_MAX
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*/
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enum {
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DPU_INTF_INPUT_CTRL = 0x1,
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DPU_INTF_TE,
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DPU_DATA_HCTL_EN,
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DPU_INTF_MAX
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};
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@ -1225,6 +1225,7 @@ static const struct dev_pm_ops dpu_pm_ops = {
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static const struct of_device_id dpu_dt_match[] = {
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{ .compatible = "qcom,sdm845-dpu", },
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{ .compatible = "qcom,sc7180-dpu", },
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{ .compatible = "qcom,sc7280-dpu", },
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{ .compatible = "qcom,sm8150-dpu", },
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{ .compatible = "qcom,sm8250-dpu", },
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{}
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@ -170,6 +170,9 @@ static int dpu_mdss_enable(struct msm_mdss *mdss)
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case DPU_HW_VER_620:
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writel_relaxed(0x1e, dpu_mdss->mmio + UBWC_STATIC);
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break;
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case DPU_HW_VER_720:
|
||||
writel_relaxed(0x101e, dpu_mdss->mmio + UBWC_STATIC);
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
|
||||
@ -1341,6 +1341,7 @@ static const struct of_device_id dt_match[] = {
|
||||
{ .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 },
|
||||
{ .compatible = "qcom,sdm845-mdss", .data = (void *)KMS_DPU },
|
||||
{ .compatible = "qcom,sc7180-mdss", .data = (void *)KMS_DPU },
|
||||
{ .compatible = "qcom,sc7280-mdss", .data = (void *)KMS_DPU },
|
||||
{ .compatible = "qcom,sm8150-mdss", .data = (void *)KMS_DPU },
|
||||
{ .compatible = "qcom,sm8250-mdss", .data = (void *)KMS_DPU },
|
||||
{}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user