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clk: samsung: exynos5420: fix register offset for sclk_bpll
This patch fixes the wrong register offset for sclk_bpll clock. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
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@ -111,7 +111,6 @@
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#define TOP_SPARE2 0x10b08
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#define BPLL_LOCK 0x20010
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#define BPLL_CON0 0x20110
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#define SRC_CDREX 0x20200
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#define KPLL_LOCK 0x28000
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#define KPLL_CON0 0x28100
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#define SRC_KFC 0x28200
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@ -204,7 +203,6 @@ static unsigned long exynos5420_clk_regs[] __initdata = {
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GATE_TOP_SCLK_FSYS,
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GATE_TOP_SCLK_PERIC,
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TOP_SPARE2,
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SRC_CDREX,
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SRC_KFC,
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DIV_KFC0,
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};
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@ -380,7 +378,7 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
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MUX(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1),
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MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
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MUX(0, "sclk_bpll", mout_bpll_p, SRC_CDREX, 0, 1),
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MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1),
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MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),
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MUX_A(0, "mout_aclk400_mscl", mout_group1_p,
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