renegade-project/linux-next
2
0
Fork 0
mirror of https://github.com/edk2-porting/linux-next.git synced 2024-12-24 13:13:57 +08:00
Code

clk: sunxi: clk-sunxi: Demote a bunch of non-conformant kernel-doc headers

Browse Source 
Fixes the following W=1 kernel build warning(s):

 drivers/clk/sunxi/clk-sunxi.c:34: warning: Function parameter or member 'req' not described in 'sun4i_get_pll1_factors'
 drivers/clk/sunxi/clk-sunxi.c:81: warning: Function parameter or member 'req' not described in 'sun6i_a31_get_pll1_factors'
 drivers/clk/sunxi/clk-sunxi.c:158: warning: Function parameter or member 'req' not described in 'sun8i_a23_get_pll1_factors'
 drivers/clk/sunxi/clk-sunxi.c:202: warning: Function parameter or member 'req' not described in 'sun4i_get_pll5_factors'
 drivers/clk/sunxi/clk-sunxi.c:229: warning: Function parameter or member 'req' not described in 'sun6i_a31_get_pll6_factors'
 drivers/clk/sunxi/clk-sunxi.c:250: warning: Function parameter or member 'req' not described in 'sun5i_a13_get_ahb_factors'
 drivers/clk/sunxi/clk-sunxi.c:289: warning: Function parameter or member 'req' not described in 'sun6i_get_ahb1_factors'
 drivers/clk/sunxi/clk-sunxi.c:328: warning: Function parameter or member 'req' not described in 'sun6i_ahb1_recalc'
 drivers/clk/sunxi/clk-sunxi.c:346: warning: Function parameter or member 'req' not described in 'sun4i_get_apb1_factors'
 drivers/clk/sunxi/clk-sunxi.c:385: warning: Function parameter or member 'req' not described in 'sun7i_a20_get_out_factors'
 drivers/clk/sunxi/clk-sunxi.c:415: warning: cannot understand function prototype: 'const struct clk_factors_config sun4i_pll1_config = '
 drivers/clk/sunxi/clk-sunxi.c:724: warning: cannot understand function prototype: 'struct div_data '
 drivers/clk/sunxi/clk-sunxi.c:945: warning: Function parameter or member 'node' not described in 'sunxi_divs_clk_setup'
 drivers/clk/sunxi/clk-sunxi.c:945: warning: Function parameter or member 'data' not described in 'sunxi_divs_clk_setup'

Cc: "Emilio López" <emilio@elopez.com.ar>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Maxime Ripard <mripard@kernel.org>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Jernej Skrabec <jernej.skrabec@siol.net>
Cc: linux-clk@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20210120093040.1719407-15-lee.jones@linaro.org
This commit is contained in:
Lee Jones 2021-01-20 09:30:34 +00:00 committed by Maxime Ripard
parent 756650820a
commit 58fdf74d43
No known key found for this signature in database
GPG Key ID: E3EF0D6F671851C5
1 changed files with 16 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
drivers/clk/sunxi/clk-sunxi.c
View File

@ -23,7 +23,7 @@ static DEFINE_SPINLOCK(clk_lock);
/* Maximum number of parents our clocks have */ /* Maximum number of parents our clocks have */
#define SUNXI_MAX_PARENTS 5 #define SUNXI_MAX_PARENTS 5
/** /*
* sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
* PLL1 rate is calculated as follows * PLL1 rate is calculated as follows
* rate = (parent_rate * n * (k + 1) >> p) / (m + 1); * rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
@ -71,7 +71,7 @@ static void sun4i_get_pll1_factors(struct factors_request *req)
req->n = div / 4; req->n = div / 4;
} }
/** /*
* sun6i_a31_get_pll1_factors() - calculates n, k and m factors for PLL1 * sun6i_a31_get_pll1_factors() - calculates n, k and m factors for PLL1
* PLL1 rate is calculated as follows * PLL1 rate is calculated as follows
* rate = parent_rate * (n + 1) * (k + 1) / (m + 1); * rate = parent_rate * (n + 1) * (k + 1) / (m + 1);
@ -147,7 +147,7 @@ static void sun6i_a31_get_pll1_factors(struct factors_request *req)
} }
} }
/** /*
* sun8i_a23_get_pll1_factors() - calculates n, k, m, p factors for PLL1 * sun8i_a23_get_pll1_factors() - calculates n, k, m, p factors for PLL1
* PLL1 rate is calculated as follows * PLL1 rate is calculated as follows
* rate = (parent_rate * (n + 1) * (k + 1) >> p) / (m + 1); * rate = (parent_rate * (n + 1) * (k + 1) >> p) / (m + 1);
@ -191,7 +191,7 @@ static void sun8i_a23_get_pll1_factors(struct factors_request *req)
req->n = div / 4 - 1; req->n = div / 4 - 1;
} }
/** /*
* sun4i_get_pll5_factors() - calculates n, k factors for PLL5 * sun4i_get_pll5_factors() - calculates n, k factors for PLL5
* PLL5 rate is calculated as follows * PLL5 rate is calculated as follows
* rate = parent_rate * n * (k + 1) * rate = parent_rate * n * (k + 1)
@ -218,7 +218,7 @@ static void sun4i_get_pll5_factors(struct factors_request *req)
req->n = DIV_ROUND_UP(div, (req->k + 1)); req->n = DIV_ROUND_UP(div, (req->k + 1));
} }
/** /*
* sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6x2 * sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6x2
* PLL6x2 rate is calculated as follows * PLL6x2 rate is calculated as follows
* rate = parent_rate * (n + 1) * (k + 1) * rate = parent_rate * (n + 1) * (k + 1)
@ -240,7 +240,7 @@ static void sun6i_a31_get_pll6_factors(struct factors_request *req)
req->n = DIV_ROUND_UP(div, (req->k + 1)) - 1; req->n = DIV_ROUND_UP(div, (req->k + 1)) - 1;
} }
/** /*
* sun5i_a13_get_ahb_factors() - calculates m, p factors for AHB * sun5i_a13_get_ahb_factors() - calculates m, p factors for AHB
* AHB rate is calculated as follows * AHB rate is calculated as follows
* rate = parent_rate >> p * rate = parent_rate >> p
@ -276,7 +276,7 @@ static void sun5i_a13_get_ahb_factors(struct factors_request *req)
#define SUN6I_AHB1_PARENT_PLL6 3 #define SUN6I_AHB1_PARENT_PLL6 3
/** /*
* sun6i_a31_get_ahb_factors() - calculates m, p factors for AHB * sun6i_a31_get_ahb_factors() - calculates m, p factors for AHB
* AHB rate is calculated as follows * AHB rate is calculated as follows
* rate = parent_rate >> p * rate = parent_rate >> p
@ -320,7 +320,7 @@ static void sun6i_get_ahb1_factors(struct factors_request *req)
req->m = calcm - 1; req->m = calcm - 1;
} }
/** /*
* sun6i_ahb1_recalc() - calculates AHB clock rate from m, p factors and * sun6i_ahb1_recalc() - calculates AHB clock rate from m, p factors and
* parent index * parent index
*/ */
@ -336,7 +336,7 @@ static void sun6i_ahb1_recalc(struct factors_request *req)
req->rate >>= req->p; req->rate >>= req->p;
} }
/** /*
* sun4i_get_apb1_factors() - calculates m, p factors for APB1 * sun4i_get_apb1_factors() - calculates m, p factors for APB1
* APB1 rate is calculated as follows * APB1 rate is calculated as follows
* rate = (parent_rate >> p) / (m + 1); * rate = (parent_rate >> p) / (m + 1);
@ -375,7 +375,7 @@ static void sun4i_get_apb1_factors(struct factors_request *req)
/** /*
* sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B * sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B
* CLK_OUT rate is calculated as follows * CLK_OUT rate is calculated as follows
* rate = (parent_rate >> p) / (m + 1); * rate = (parent_rate >> p) / (m + 1);
@ -408,7 +408,7 @@ static void sun7i_a20_get_out_factors(struct factors_request *req)
req->p = calcp; req->p = calcp;
} }
/** /*
* sunxi_factors_clk_setup() - Setup function for factor clocks * sunxi_factors_clk_setup() - Setup function for factor clocks
*/ */
@ -625,7 +625,7 @@ CLK_OF_DECLARE(sun7i_out, "allwinner,sun7i-a20-out-clk",
sun7i_out_clk_setup); sun7i_out_clk_setup);
/** /*
* sunxi_mux_clk_setup() - Setup function for muxes * sunxi_mux_clk_setup() - Setup function for muxes
*/ */
@ -717,7 +717,7 @@ CLK_OF_DECLARE(sun8i_ahb2, "allwinner,sun8i-h3-ahb2-clk",
sun8i_ahb2_clk_setup); sun8i_ahb2_clk_setup);
/** /*
* sunxi_divider_clk_setup() - Setup function for simple divider clocks * sunxi_divider_clk_setup() - Setup function for simple divider clocks
*/ */
@ -853,7 +853,7 @@ CLK_OF_DECLARE(sun8i_axi, "allwinner,sun8i-a23-axi-clk",
/** /*
* sunxi_gates_clk_setup() - Setup function for leaf gates on clocks * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
*/ */
@ -863,7 +863,7 @@ struct gates_data {
DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE); DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
}; };
/** /*
* sunxi_divs_clk_setup() helper data * sunxi_divs_clk_setup() helper data
*/ */
@ -929,7 +929,7 @@ static const struct divs_data sun6i_a31_pll6_divs_data __initconst = {
} }
}; };
/** /*
* sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
* *
* These clocks look something like this * These clocks look something like this