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Merge branch 'master' of /pub/scm/linux/kernel/git/torvalds/linux-2.6
This commit is contained in:
commit
58b8a5b45a
.mailmap
Documentation
MAINTAINERSarch
arm
include/asm
kernel
mach-ep93xx
mach-omap2
mach-realview
mach-shmobile
Kconfigboard-ag5evm.cboard-g3evm.cboard-mackerel.cclock-sh7372.cclock-sh73a0.cintc-sh7372.cintc-sh73a0.c
mach-tegra
mach-versatile
mach-vexpress
avr32/include/asm
m68k
parisc/kernel
sh
x86
drivers
ata
atm
base/power
bluetooth
char
clocksource
gpio
gpu/drm
nouveau
radeon
hwmon
input
1
.mailmap
1
.mailmap
@ -23,6 +23,7 @@ Andy Adamson <andros@citi.umich.edu>
|
||||
Arnaud Patard <arnaud.patard@rtp-net.org>
|
||||
Arnd Bergmann <arnd@arndb.de>
|
||||
Axel Dyks <xl@xlsigned.net>
|
||||
Axel Lin <axel.lin@gmail.com>
|
||||
Ben Gardner <bgardner@wabtec.com>
|
||||
Ben M Cahill <ben.m.cahill@intel.com>
|
||||
Björn Steinbrink <B.Steinbrink@gmx.de>
|
||||
|
25
Documentation/ABI/testing/sysfs-platform-at91
Normal file
25
Documentation/ABI/testing/sysfs-platform-at91
Normal file
@ -0,0 +1,25 @@
|
||||
What: /sys/devices/platform/at91_can/net/<iface>/mb0_id
|
||||
Date: January 2011
|
||||
KernelVersion: 2.6.38
|
||||
Contact: Marc Kleine-Budde <kernel@pengutronix.de>
|
||||
Description:
|
||||
Value representing the can_id of mailbox 0.
|
||||
|
||||
Default: 0x7ff (standard frame)
|
||||
|
||||
Due to a chip bug (errata 50.2.6.3 & 50.3.5.3 in
|
||||
"AT91SAM9263 Preliminary 6249H-ATARM-27-Jul-09") the
|
||||
contents of mailbox 0 may be send under certain
|
||||
conditions (even if disabled or in rx mode).
|
||||
|
||||
The workaround in the errata suggests not to use the
|
||||
mailbox and load it with an unused identifier.
|
||||
|
||||
In order to use an extended can_id add the
|
||||
CAN_EFF_FLAG (0x80000000U) to the can_id. Example:
|
||||
|
||||
- standard id 0x7ff:
|
||||
echo 0x7ff > /sys/class/net/can0/mb0_id
|
||||
|
||||
- extended id 0x1fffffff:
|
||||
echo 0x9fffffff > /sys/class/net/can0/mb0_id
|
@ -460,6 +460,8 @@ Note, a technical ChangeLog aimed at kernel hackers is in fs/ntfs/ChangeLog.
|
||||
2.1.30:
|
||||
- Fix writev() (it kept writing the first segment over and over again
|
||||
instead of moving onto subsequent segments).
|
||||
- Fix crash in ntfs_mft_record_alloc() when mapping the new extent mft
|
||||
record failed.
|
||||
2.1.29:
|
||||
- Fix a deadlock when mounting read-write.
|
||||
2.1.28:
|
||||
|
@ -43,11 +43,11 @@ parameter is applicable:
|
||||
AVR32 AVR32 architecture is enabled.
|
||||
AX25 Appropriate AX.25 support is enabled.
|
||||
BLACKFIN Blackfin architecture is enabled.
|
||||
DRM Direct Rendering Management support is enabled.
|
||||
DYNAMIC_DEBUG Build in debug messages and enable them at runtime
|
||||
EDD BIOS Enhanced Disk Drive Services (EDD) is enabled
|
||||
EFI EFI Partitioning (GPT) is enabled
|
||||
EIDE EIDE/ATAPI support is enabled.
|
||||
DRM Direct Rendering Management support is enabled.
|
||||
DYNAMIC_DEBUG Build in debug messages and enable them at runtime
|
||||
FB The frame buffer device is enabled.
|
||||
GCOV GCOV profiling is enabled.
|
||||
HW Appropriate hardware is enabled.
|
||||
|
@ -49,7 +49,8 @@ Table of Contents
|
||||
3.3 Configuring Bonding Manually with Ifenslave
|
||||
3.3.1 Configuring Multiple Bonds Manually
|
||||
3.4 Configuring Bonding Manually via Sysfs
|
||||
3.5 Overriding Configuration for Special Cases
|
||||
3.5 Configuration with Interfaces Support
|
||||
3.6 Overriding Configuration for Special Cases
|
||||
|
||||
4. Querying Bonding Configuration
|
||||
4.1 Bonding Configuration
|
||||
@ -161,8 +162,8 @@ onwards) do not have /usr/include/linux symbolically linked to the
|
||||
default kernel source include directory.
|
||||
|
||||
SECOND IMPORTANT NOTE:
|
||||
If you plan to configure bonding using sysfs, you do not need
|
||||
to use ifenslave.
|
||||
If you plan to configure bonding using sysfs or using the
|
||||
/etc/network/interfaces file, you do not need to use ifenslave.
|
||||
|
||||
2. Bonding Driver Options
|
||||
=========================
|
||||
@ -779,22 +780,26 @@ resend_igmp
|
||||
|
||||
You can configure bonding using either your distro's network
|
||||
initialization scripts, or manually using either ifenslave or the
|
||||
sysfs interface. Distros generally use one of two packages for the
|
||||
network initialization scripts: initscripts or sysconfig. Recent
|
||||
versions of these packages have support for bonding, while older
|
||||
sysfs interface. Distros generally use one of three packages for the
|
||||
network initialization scripts: initscripts, sysconfig or interfaces.
|
||||
Recent versions of these packages have support for bonding, while older
|
||||
versions do not.
|
||||
|
||||
We will first describe the options for configuring bonding for
|
||||
distros using versions of initscripts and sysconfig with full or
|
||||
partial support for bonding, then provide information on enabling
|
||||
distros using versions of initscripts, sysconfig and interfaces with full
|
||||
or partial support for bonding, then provide information on enabling
|
||||
bonding without support from the network initialization scripts (i.e.,
|
||||
older versions of initscripts or sysconfig).
|
||||
|
||||
If you're unsure whether your distro uses sysconfig or
|
||||
initscripts, or don't know if it's new enough, have no fear.
|
||||
If you're unsure whether your distro uses sysconfig,
|
||||
initscripts or interfaces, or don't know if it's new enough, have no fear.
|
||||
Determining this is fairly straightforward.
|
||||
|
||||
First, issue the command:
|
||||
First, look for a file called interfaces in /etc/network directory.
|
||||
If this file is present in your system, then your system use interfaces. See
|
||||
Configuration with Interfaces Support.
|
||||
|
||||
Else, issue the command:
|
||||
|
||||
$ rpm -qf /sbin/ifup
|
||||
|
||||
@ -1327,8 +1332,62 @@ echo 2000 > /sys/class/net/bond1/bonding/arp_interval
|
||||
echo +eth2 > /sys/class/net/bond1/bonding/slaves
|
||||
echo +eth3 > /sys/class/net/bond1/bonding/slaves
|
||||
|
||||
3.5 Overriding Configuration for Special Cases
|
||||
3.5 Configuration with Interfaces Support
|
||||
-----------------------------------------
|
||||
|
||||
This section applies to distros which use /etc/network/interfaces file
|
||||
to describe network interface configuration, most notably Debian and it's
|
||||
derivatives.
|
||||
|
||||
The ifup and ifdown commands on Debian don't support bonding out of
|
||||
the box. The ifenslave-2.6 package should be installed to provide bonding
|
||||
support. Once installed, this package will provide bond-* options to be used
|
||||
into /etc/network/interfaces.
|
||||
|
||||
Note that ifenslave-2.6 package will load the bonding module and use
|
||||
the ifenslave command when appropriate.
|
||||
|
||||
Example Configurations
|
||||
----------------------
|
||||
|
||||
In /etc/network/interfaces, the following stanza will configure bond0, in
|
||||
active-backup mode, with eth0 and eth1 as slaves.
|
||||
|
||||
auto bond0
|
||||
iface bond0 inet dhcp
|
||||
bond-slaves eth0 eth1
|
||||
bond-mode active-backup
|
||||
bond-miimon 100
|
||||
bond-primary eth0 eth1
|
||||
|
||||
If the above configuration doesn't work, you might have a system using
|
||||
upstart for system startup. This is most notably true for recent
|
||||
Ubuntu versions. The following stanza in /etc/network/interfaces will
|
||||
produce the same result on those systems.
|
||||
|
||||
auto bond0
|
||||
iface bond0 inet dhcp
|
||||
bond-slaves none
|
||||
bond-mode active-backup
|
||||
bond-miimon 100
|
||||
|
||||
auto eth0
|
||||
iface eth0 inet manual
|
||||
bond-master bond0
|
||||
bond-primary eth0 eth1
|
||||
|
||||
auto eth1
|
||||
iface eth1 inet manual
|
||||
bond-master bond0
|
||||
bond-primary eth0 eth1
|
||||
|
||||
For a full list of bond-* supported options in /etc/network/interfaces and some
|
||||
more advanced examples tailored to you particular distros, see the files in
|
||||
/usr/share/doc/ifenslave-2.6.
|
||||
|
||||
3.6 Overriding Configuration for Special Cases
|
||||
----------------------------------------------
|
||||
|
||||
When using the bonding driver, the physical port which transmits a frame is
|
||||
typically selected by the bonding driver, and is not relevant to the user or
|
||||
system administrator. The output port is simply selected using the policies of
|
||||
|
@ -3327,7 +3327,6 @@ F: drivers/net/wimax/i2400m/
|
||||
F: include/linux/wimax/i2400m.h
|
||||
|
||||
INTEL WIRELESS WIFI LINK (iwlwifi)
|
||||
M: Reinette Chatre <reinette.chatre@intel.com>
|
||||
M: Wey-Yi Guy <wey-yi.w.guy@intel.com>
|
||||
M: Intel Linux Wireless <ilw@linux.intel.com>
|
||||
L: linux-wireless@vger.kernel.org
|
||||
|
@ -50,6 +50,12 @@
|
||||
#define SCPCELLID2 0xFF8
|
||||
#define SCPCELLID3 0xFFC
|
||||
|
||||
#define SCCTRL_TIMEREN0SEL_REFCLK (0 << 15)
|
||||
#define SCCTRL_TIMEREN0SEL_TIMCLK (1 << 15)
|
||||
|
||||
#define SCCTRL_TIMEREN1SEL_REFCLK (0 << 17)
|
||||
#define SCCTRL_TIMEREN1SEL_TIMCLK (1 << 17)
|
||||
|
||||
static inline void sysctl_soft_reset(void __iomem *base)
|
||||
{
|
||||
/* writing any value to SCSYSSTAT reg will reset system */
|
||||
|
@ -188,7 +188,7 @@
|
||||
* translation for translating DMA addresses. Use the driver
|
||||
* DMA support - see dma-mapping.h.
|
||||
*/
|
||||
static inline unsigned long virt_to_phys(void *x)
|
||||
static inline unsigned long virt_to_phys(const volatile void *x)
|
||||
{
|
||||
return __virt_to_phys((unsigned long)(x));
|
||||
}
|
||||
|
@ -36,6 +36,7 @@ static void twd_set_mode(enum clock_event_mode mode,
|
||||
/* timer load already set up */
|
||||
ctrl = TWD_TIMER_CONTROL_ENABLE | TWD_TIMER_CONTROL_IT_ENABLE
|
||||
| TWD_TIMER_CONTROL_PERIODIC;
|
||||
__raw_writel(twd_timer_rate / HZ, twd_base + TWD_TIMER_LOAD);
|
||||
break;
|
||||
case CLOCK_EVT_MODE_ONESHOT:
|
||||
/* period set, and timer enabled in 'next_event' hook */
|
||||
@ -81,7 +82,7 @@ int twd_timer_ack(void)
|
||||
|
||||
static void __cpuinit twd_calibrate_rate(void)
|
||||
{
|
||||
unsigned long load, count;
|
||||
unsigned long count;
|
||||
u64 waitjiffies;
|
||||
|
||||
/*
|
||||
@ -116,10 +117,6 @@ static void __cpuinit twd_calibrate_rate(void)
|
||||
printk("%lu.%02luMHz.\n", twd_timer_rate / 1000000,
|
||||
(twd_timer_rate / 1000000) % 100);
|
||||
}
|
||||
|
||||
load = twd_timer_rate / HZ;
|
||||
|
||||
__raw_writel(load, twd_base + TWD_TIMER_LOAD);
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -427,6 +427,13 @@ void __init ep93xx_gpio_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* Set Ports C, D, E, G, and H for GPIO use */
|
||||
ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS |
|
||||
EP93XX_SYSCON_DEVCFG_GONK |
|
||||
EP93XX_SYSCON_DEVCFG_EONIDE |
|
||||
EP93XX_SYSCON_DEVCFG_GONIDE |
|
||||
EP93XX_SYSCON_DEVCFG_HONIDE);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++)
|
||||
gpiochip_add(&ep93xx_gpio_banks[i].chip);
|
||||
}
|
||||
|
@ -134,7 +134,7 @@ static void omap2_enter_full_retention(void)
|
||||
|
||||
/* Block console output in case it is on one of the OMAP UARTs */
|
||||
if (!is_suspending())
|
||||
if (try_acquire_console_sem())
|
||||
if (!console_trylock())
|
||||
goto no_sleep;
|
||||
|
||||
omap_uart_prepare_idle(0);
|
||||
@ -151,7 +151,7 @@ static void omap2_enter_full_retention(void)
|
||||
omap_uart_resume_idle(0);
|
||||
|
||||
if (!is_suspending())
|
||||
release_console_sem();
|
||||
console_unlock();
|
||||
|
||||
no_sleep:
|
||||
if (omap2_pm_debug) {
|
||||
|
@ -398,7 +398,7 @@ void omap_sram_idle(void)
|
||||
if (!is_suspending())
|
||||
if (per_next_state < PWRDM_POWER_ON ||
|
||||
core_next_state < PWRDM_POWER_ON)
|
||||
if (try_acquire_console_sem())
|
||||
if (!console_trylock())
|
||||
goto console_still_active;
|
||||
|
||||
/* PER */
|
||||
@ -481,7 +481,7 @@ void omap_sram_idle(void)
|
||||
}
|
||||
|
||||
if (!is_suspending())
|
||||
release_console_sem();
|
||||
console_unlock();
|
||||
|
||||
console_still_active:
|
||||
/* Disable IO-PAD and IO-CHAIN wakeup */
|
||||
|
@ -812,7 +812,7 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
|
||||
|
||||
oh->dev_attr = uart;
|
||||
|
||||
acquire_console_sem(); /* in case the earlycon is on the UART */
|
||||
console_lock(); /* in case the earlycon is on the UART */
|
||||
|
||||
/*
|
||||
* Because of early UART probing, UART did not get idled
|
||||
@ -838,7 +838,7 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
|
||||
omap_uart_block_sleep(uart);
|
||||
uart->timeout = DEFAULT_TIMEOUT;
|
||||
|
||||
release_console_sem();
|
||||
console_unlock();
|
||||
|
||||
if ((cpu_is_omap34xx() && uart->padconf) ||
|
||||
(uart->wk_en && uart->wk_mask)) {
|
||||
|
@ -2,52 +2,56 @@ menu "RealView platform type"
|
||||
depends on ARCH_REALVIEW
|
||||
|
||||
config MACH_REALVIEW_EB
|
||||
bool "Support RealView/EB platform"
|
||||
bool "Support RealView(R) Emulation Baseboard"
|
||||
select ARM_GIC
|
||||
help
|
||||
Include support for the ARM(R) RealView Emulation Baseboard platform.
|
||||
Include support for the ARM(R) RealView(R) Emulation Baseboard
|
||||
platform.
|
||||
|
||||
config REALVIEW_EB_A9MP
|
||||
bool "Support Multicore Cortex-A9"
|
||||
bool "Support Multicore Cortex-A9 Tile"
|
||||
depends on MACH_REALVIEW_EB
|
||||
select CPU_V7
|
||||
help
|
||||
Enable support for the Cortex-A9MPCore tile on the Realview platform.
|
||||
Enable support for the Cortex-A9MPCore tile fitted to the
|
||||
Realview(R) Emulation Baseboard platform.
|
||||
|
||||
config REALVIEW_EB_ARM11MP
|
||||
bool "Support ARM11MPCore tile"
|
||||
bool "Support ARM11MPCore Tile"
|
||||
depends on MACH_REALVIEW_EB
|
||||
select CPU_V6
|
||||
select ARCH_HAS_BARRIERS if SMP
|
||||
help
|
||||
Enable support for the ARM11MPCore tile on the Realview platform.
|
||||
Enable support for the ARM11MPCore tile fitted to the Realview(R)
|
||||
Emulation Baseboard platform.
|
||||
|
||||
config REALVIEW_EB_ARM11MP_REVB
|
||||
bool "Support ARM11MPCore RevB tile"
|
||||
bool "Support ARM11MPCore RevB Tile"
|
||||
depends on REALVIEW_EB_ARM11MP
|
||||
help
|
||||
Enable support for the ARM11MPCore RevB tile on the Realview
|
||||
platform. Since there are device address differences, a
|
||||
kernel built with this option enabled is not compatible with
|
||||
other revisions of the ARM11MPCore tile.
|
||||
Enable support for the ARM11MPCore Revision B tile on the
|
||||
Realview(R) Emulation Baseboard platform. Since there are device
|
||||
address differences, a kernel built with this option enabled is
|
||||
not compatible with other revisions of the ARM11MPCore tile.
|
||||
|
||||
config MACH_REALVIEW_PB11MP
|
||||
bool "Support RealView/PB11MPCore platform"
|
||||
bool "Support RealView(R) Platform Baseboard for ARM11MPCore"
|
||||
select CPU_V6
|
||||
select ARM_GIC
|
||||
select HAVE_PATA_PLATFORM
|
||||
select ARCH_HAS_BARRIERS if SMP
|
||||
help
|
||||
Include support for the ARM(R) RealView MPCore Platform Baseboard.
|
||||
PB11MPCore is a platform with an on-board ARM11MPCore and has
|
||||
Include support for the ARM(R) RealView(R) Platform Baseboard for
|
||||
the ARM11MPCore. This platform has an on-board ARM11MPCore and has
|
||||
support for PCI-E and Compact Flash.
|
||||
|
||||
config MACH_REALVIEW_PB1176
|
||||
bool "Support RealView/PB1176 platform"
|
||||
bool "Support RealView(R) Platform Baseboard for ARM1176JZF-S"
|
||||
select CPU_V6
|
||||
select ARM_GIC
|
||||
help
|
||||
Include support for the ARM(R) RealView ARM1176 Platform Baseboard.
|
||||
Include support for the ARM(R) RealView(R) Platform Baseboard for
|
||||
ARM1176JZF-S.
|
||||
|
||||
config REALVIEW_PB1176_SECURE_FLASH
|
||||
bool "Allow access to the secure flash memory block"
|
||||
@ -59,23 +63,24 @@ config REALVIEW_PB1176_SECURE_FLASH
|
||||
block (64MB @ 0x3c000000) is required.
|
||||
|
||||
config MACH_REALVIEW_PBA8
|
||||
bool "Support RealView/PB-A8 platform"
|
||||
bool "Support RealView(R) Platform Baseboard for Cortex(tm)-A8 platform"
|
||||
select CPU_V7
|
||||
select ARM_GIC
|
||||
select HAVE_PATA_PLATFORM
|
||||
help
|
||||
Include support for the ARM(R) RealView Cortex-A8 Platform Baseboard.
|
||||
PB-A8 is a platform with an on-board Cortex-A8 and has support for
|
||||
PCI-E and Compact Flash.
|
||||
Include support for the ARM(R) RealView Platform Baseboard for
|
||||
Cortex(tm)-A8. This platform has an on-board Cortex-A8 and has
|
||||
support for PCI-E and Compact Flash.
|
||||
|
||||
config MACH_REALVIEW_PBX
|
||||
bool "Support RealView/PBX platform"
|
||||
bool "Support RealView(R) Platform Baseboard Explore"
|
||||
select ARM_GIC
|
||||
select HAVE_PATA_PLATFORM
|
||||
select ARCH_SPARSEMEM_ENABLE if CPU_V7 && !REALVIEW_HIGH_PHYS_OFFSET
|
||||
select ZONE_DMA if SPARSEMEM
|
||||
help
|
||||
Include support for the ARM(R) RealView PBX platform.
|
||||
Include support for the ARM(R) RealView(R) Platform Baseboard
|
||||
Explore.
|
||||
|
||||
config REALVIEW_HIGH_PHYS_OFFSET
|
||||
bool "High physical base address for the RealView platform"
|
||||
|
@ -41,7 +41,7 @@ volatile int __cpuinitdata pen_release = -1;
|
||||
* observers, irrespective of whether they're taking part in coherency
|
||||
* or not. This is necessary for the hotplug code to work reliably.
|
||||
*/
|
||||
static void write_pen_release(int val)
|
||||
static void __cpuinit write_pen_release(int val)
|
||||
{
|
||||
pen_release = val;
|
||||
smp_wmb();
|
||||
|
@ -60,6 +60,8 @@ endchoice
|
||||
|
||||
config MACH_AG5EVM
|
||||
bool "AG5EVM board"
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select SH_LCD_MIPI_DSI
|
||||
depends on ARCH_SH73A0
|
||||
|
||||
config MACH_MACKEREL
|
||||
|
@ -34,9 +34,10 @@
|
||||
#include <linux/input/sh_keysc.h>
|
||||
#include <linux/mmc/host.h>
|
||||
#include <linux/mmc/sh_mmcif.h>
|
||||
|
||||
#include <linux/sh_clk.h>
|
||||
#include <video/sh_mobile_lcdc.h>
|
||||
#include <video/sh_mipi_dsi.h>
|
||||
#include <sound/sh_fsi.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/sh73a0.h>
|
||||
#include <mach/common.h>
|
||||
@ -183,11 +184,165 @@ static struct platform_device mmc_device = {
|
||||
.resource = sh_mmcif_resources,
|
||||
};
|
||||
|
||||
/* IrDA */
|
||||
static struct resource irda_resources[] = {
|
||||
[0] = {
|
||||
.start = 0xE6D00000,
|
||||
.end = 0xE6D01FD4 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = gic_spi(95),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device irda_device = {
|
||||
.name = "sh_irda",
|
||||
.id = 0,
|
||||
.resource = irda_resources,
|
||||
.num_resources = ARRAY_SIZE(irda_resources),
|
||||
};
|
||||
|
||||
static unsigned char lcd_backlight_seq[3][2] = {
|
||||
{ 0x04, 0x07 },
|
||||
{ 0x23, 0x80 },
|
||||
{ 0x03, 0x01 },
|
||||
};
|
||||
|
||||
static void lcd_backlight_on(void)
|
||||
{
|
||||
struct i2c_adapter *a;
|
||||
struct i2c_msg msg;
|
||||
int k;
|
||||
|
||||
a = i2c_get_adapter(1);
|
||||
for (k = 0; a && k < 3; k++) {
|
||||
msg.addr = 0x6d;
|
||||
msg.buf = &lcd_backlight_seq[k][0];
|
||||
msg.len = 2;
|
||||
msg.flags = 0;
|
||||
if (i2c_transfer(a, &msg, 1) != 1)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static void lcd_backlight_reset(void)
|
||||
{
|
||||
gpio_set_value(GPIO_PORT235, 0);
|
||||
mdelay(24);
|
||||
gpio_set_value(GPIO_PORT235, 1);
|
||||
}
|
||||
|
||||
static void lcd_on(void *board_data, struct fb_info *info)
|
||||
{
|
||||
lcd_backlight_on();
|
||||
}
|
||||
|
||||
static void lcd_off(void *board_data)
|
||||
{
|
||||
lcd_backlight_reset();
|
||||
}
|
||||
|
||||
/* LCDC0 */
|
||||
static const struct fb_videomode lcdc0_modes[] = {
|
||||
{
|
||||
.name = "R63302(QHD)",
|
||||
.xres = 544,
|
||||
.yres = 961,
|
||||
.left_margin = 72,
|
||||
.right_margin = 600,
|
||||
.hsync_len = 16,
|
||||
.upper_margin = 8,
|
||||
.lower_margin = 8,
|
||||
.vsync_len = 2,
|
||||
.sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct sh_mobile_lcdc_info lcdc0_info = {
|
||||
.clock_source = LCDC_CLK_PERIPHERAL,
|
||||
.ch[0] = {
|
||||
.chan = LCDC_CHAN_MAINLCD,
|
||||
.interface_type = RGB24,
|
||||
.clock_divider = 1,
|
||||
.flags = LCDC_FLAGS_DWPOL,
|
||||
.lcd_size_cfg.width = 44,
|
||||
.lcd_size_cfg.height = 79,
|
||||
.bpp = 16,
|
||||
.lcd_cfg = lcdc0_modes,
|
||||
.num_cfg = ARRAY_SIZE(lcdc0_modes),
|
||||
.board_cfg = {
|
||||
.display_on = lcd_on,
|
||||
.display_off = lcd_off,
|
||||
},
|
||||
}
|
||||
};
|
||||
|
||||
static struct resource lcdc0_resources[] = {
|
||||
[0] = {
|
||||
.name = "LCDC0",
|
||||
.start = 0xfe940000, /* P4-only space */
|
||||
.end = 0xfe943fff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = intcs_evt2irq(0x580),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device lcdc0_device = {
|
||||
.name = "sh_mobile_lcdc_fb",
|
||||
.num_resources = ARRAY_SIZE(lcdc0_resources),
|
||||
.resource = lcdc0_resources,
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &lcdc0_info,
|
||||
.coherent_dma_mask = ~0,
|
||||
},
|
||||
};
|
||||
|
||||
/* MIPI-DSI */
|
||||
static struct resource mipidsi0_resources[] = {
|
||||
[0] = {
|
||||
.start = 0xfeab0000,
|
||||
.end = 0xfeab3fff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = 0xfeab4000,
|
||||
.end = 0xfeab7fff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
static struct sh_mipi_dsi_info mipidsi0_info = {
|
||||
.data_format = MIPI_RGB888,
|
||||
.lcd_chan = &lcdc0_info.ch[0],
|
||||
.vsynw_offset = 20,
|
||||
.clksrc = 1,
|
||||
.flags = SH_MIPI_DSI_HSABM,
|
||||
};
|
||||
|
||||
static struct platform_device mipidsi0_device = {
|
||||
.name = "sh-mipi-dsi",
|
||||
.num_resources = ARRAY_SIZE(mipidsi0_resources),
|
||||
.resource = mipidsi0_resources,
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &mipidsi0_info,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device *ag5evm_devices[] __initdata = {
|
||||
ð_device,
|
||||
&keysc_device,
|
||||
&fsi_device,
|
||||
&mmc_device,
|
||||
&irda_device,
|
||||
&lcdc0_device,
|
||||
&mipidsi0_device,
|
||||
};
|
||||
|
||||
static struct map_desc ag5evm_io_desc[] __initdata = {
|
||||
@ -224,6 +379,8 @@ void __init ag5evm_init_irq(void)
|
||||
__raw_writew(__raw_readw(PINTCR0A) | (2<<10), PINTCR0A);
|
||||
}
|
||||
|
||||
#define DSI0PHYCR 0xe615006c
|
||||
|
||||
static void __init ag5evm_init(void)
|
||||
{
|
||||
sh73a0_pinmux_init();
|
||||
@ -287,6 +444,25 @@ static void __init ag5evm_init(void)
|
||||
gpio_request(GPIO_FN_FSIAISLD, NULL);
|
||||
gpio_request(GPIO_FN_FSIAOSLD, NULL);
|
||||
|
||||
/* IrDA */
|
||||
gpio_request(GPIO_FN_PORT241_IRDA_OUT, NULL);
|
||||
gpio_request(GPIO_FN_PORT242_IRDA_IN, NULL);
|
||||
gpio_request(GPIO_FN_PORT243_IRDA_FIRSEL, NULL);
|
||||
|
||||
/* LCD panel */
|
||||
gpio_request(GPIO_PORT217, NULL); /* RESET */
|
||||
gpio_direction_output(GPIO_PORT217, 0);
|
||||
mdelay(1);
|
||||
gpio_set_value(GPIO_PORT217, 1);
|
||||
|
||||
/* LCD backlight controller */
|
||||
gpio_request(GPIO_PORT235, NULL); /* RESET */
|
||||
gpio_direction_output(GPIO_PORT235, 0);
|
||||
lcd_backlight_reset();
|
||||
|
||||
/* MIPI-DSI clock setup */
|
||||
__raw_writel(0x2a809010, DSI0PHYCR);
|
||||
|
||||
#ifdef CONFIG_CACHE_L2X0
|
||||
/* Shared attribute override enable, 64K*8way */
|
||||
l2x0_init(__io(0xf0100000), 0x00460000, 0xc2000fff);
|
||||
|
@ -347,7 +347,6 @@ static void __init g3evm_init(void)
|
||||
gpio_request(GPIO_FN_IRDA_OUT, NULL);
|
||||
gpio_request(GPIO_FN_IRDA_IN, NULL);
|
||||
gpio_request(GPIO_FN_IRDA_FIRSEL, NULL);
|
||||
set_irq_type(evt2irq(0x480), IRQ_TYPE_LEVEL_LOW);
|
||||
|
||||
sh7367_add_standard_devices();
|
||||
|
||||
|
@ -169,9 +169,8 @@
|
||||
* SW1 | SW33
|
||||
* | bit1 | bit2 | bit3 | bit4
|
||||
* -------------+------+------+------+-------
|
||||
* MMC0 OFF | OFF | ON | ON | X
|
||||
* MMC1 ON | OFF | ON | X | ON
|
||||
* SDHI1 OFF | ON | X | OFF | ON
|
||||
* MMC0 OFF | OFF | X | ON | X (Use MMCIF)
|
||||
* SDHI1 OFF | ON | X | OFF | X (Use MFD_SH_MOBILE_SDHI)
|
||||
*
|
||||
*/
|
||||
|
||||
|
@ -234,7 +234,9 @@ static int pllc2_set_rate(struct clk *clk, unsigned long rate)
|
||||
|
||||
value = __raw_readl(PLLC2CR) & ~(0x3f << 24);
|
||||
|
||||
__raw_writel((value & ~0x80000000) | ((idx + 19) << 24), PLLC2CR);
|
||||
__raw_writel(value | ((idx + 19) << 24), PLLC2CR);
|
||||
|
||||
clk->rate = clk->freq_table[idx].frequency;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -118,8 +118,16 @@ static unsigned long pll_recalc(struct clk *clk)
|
||||
{
|
||||
unsigned long mult = 1;
|
||||
|
||||
if (__raw_readl(PLLECR) & (1 << clk->enable_bit))
|
||||
if (__raw_readl(PLLECR) & (1 << clk->enable_bit)) {
|
||||
mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1);
|
||||
/* handle CFG bit for PLL1 and PLL2 */
|
||||
switch (clk->enable_bit) {
|
||||
case 1:
|
||||
case 2:
|
||||
if (__raw_readl(clk->enable_reg) & (1 << 20))
|
||||
mult *= 2;
|
||||
}
|
||||
}
|
||||
|
||||
return clk->parent->rate * mult;
|
||||
}
|
||||
@ -212,7 +220,7 @@ enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
|
||||
static struct clk div4_clks[DIV4_NR] = {
|
||||
[DIV4_I] = DIV4(FRQCRA, 20, 0xfff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_ZG] = DIV4(FRQCRA, 16, 0xbff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_M3] = DIV4(FRQCRA, 8, 0xfff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_M3] = DIV4(FRQCRA, 12, 0xfff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_B] = DIV4(FRQCRA, 8, 0xfff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_M1] = DIV4(FRQCRA, 4, 0xfff, 0),
|
||||
[DIV4_M2] = DIV4(FRQCRA, 0, 0xfff, 0),
|
||||
@ -255,10 +263,10 @@ static struct clk div6_clks[DIV6_NR] = {
|
||||
};
|
||||
|
||||
enum { MSTP001,
|
||||
MSTP125, MSTP116,
|
||||
MSTP125, MSTP118, MSTP116, MSTP100,
|
||||
MSTP219,
|
||||
MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
|
||||
MSTP331, MSTP329, MSTP323, MSTP312,
|
||||
MSTP331, MSTP329, MSTP325, MSTP323, MSTP312,
|
||||
MSTP411, MSTP410, MSTP403,
|
||||
MSTP_NR };
|
||||
|
||||
@ -268,7 +276,9 @@ enum { MSTP001,
|
||||
static struct clk mstp_clks[MSTP_NR] = {
|
||||
[MSTP001] = MSTP(&div4_clks[DIV4_HP], SMSTPCR0, 1, 0), /* IIC2 */
|
||||
[MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
|
||||
[MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX0 */
|
||||
[MSTP116] = MSTP(&div4_clks[DIV4_HP], SMSTPCR1, 16, 0), /* IIC0 */
|
||||
[MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
|
||||
[MSTP219] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 19, 0), /* SCIFA7 */
|
||||
[MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
|
||||
[MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
|
||||
@ -279,6 +289,7 @@ static struct clk mstp_clks[MSTP_NR] = {
|
||||
[MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
|
||||
[MSTP331] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 31, 0), /* SCIFA6 */
|
||||
[MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
|
||||
[MSTP325] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 25, 0), /* IrDA */
|
||||
[MSTP323] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 23, 0), /* IIC1 */
|
||||
[MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMCIF0 */
|
||||
[MSTP411] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 11, 0), /* IIC3 */
|
||||
@ -288,16 +299,25 @@ static struct clk mstp_clks[MSTP_NR] = {
|
||||
|
||||
#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
|
||||
#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
|
||||
#define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk }
|
||||
|
||||
static struct clk_lookup lookups[] = {
|
||||
/* main clocks */
|
||||
CLKDEV_CON_ID("r_clk", &r_clk),
|
||||
|
||||
/* DIV6 clocks */
|
||||
CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]),
|
||||
CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]),
|
||||
CLKDEV_ICK_ID("dsi0p_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]),
|
||||
CLKDEV_ICK_ID("dsi1p_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]),
|
||||
|
||||
/* MSTP32 clocks */
|
||||
CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* I2C2 */
|
||||
CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */
|
||||
CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]), /* TMU00 */
|
||||
CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]), /* TMU01 */
|
||||
CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* I2C0 */
|
||||
CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX */
|
||||
CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP219]), /* SCIFA7 */
|
||||
CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
|
||||
CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), /* SCIFB */
|
||||
@ -308,6 +328,7 @@ static struct clk_lookup lookups[] = {
|
||||
CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
|
||||
CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */
|
||||
CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
|
||||
CLKDEV_DEV_ID("sh_irda.0", &mstp_clks[MSTP325]), /* IrDA */
|
||||
CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */
|
||||
CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */
|
||||
CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* I2C3 */
|
||||
|
@ -365,6 +365,7 @@ static struct intc_desc intca_desc __initdata = {
|
||||
|
||||
enum {
|
||||
UNUSED_INTCS = 0,
|
||||
ENABLED_INTCS,
|
||||
|
||||
INTCS,
|
||||
|
||||
@ -413,7 +414,7 @@ enum {
|
||||
CMT4,
|
||||
DSITX1_DSITX1_0,
|
||||
DSITX1_DSITX1_1,
|
||||
/* MFIS2 */
|
||||
MFIS2_INTCS, /* Priority always enabled using ENABLED_INTCS */
|
||||
CPORTS2R,
|
||||
/* CEC */
|
||||
JPU6E,
|
||||
@ -477,7 +478,7 @@ static struct intc_vect intcs_vectors[] = {
|
||||
INTCS_VECT(CMT4, 0x1980),
|
||||
INTCS_VECT(DSITX1_DSITX1_0, 0x19a0),
|
||||
INTCS_VECT(DSITX1_DSITX1_1, 0x19c0),
|
||||
/* MFIS2 */
|
||||
INTCS_VECT(MFIS2_INTCS, 0x1a00),
|
||||
INTCS_VECT(CPORTS2R, 0x1a20),
|
||||
/* CEC */
|
||||
INTCS_VECT(JPU6E, 0x1a80),
|
||||
@ -543,7 +544,7 @@ static struct intc_mask_reg intcs_mask_registers[] = {
|
||||
{ 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
|
||||
CMT4, DSITX1_DSITX1_0, DSITX1_DSITX1_1, 0 } },
|
||||
{ 0xffd5019c, 0xffd501dc, 8, /* IMR7SA3 / IMCR7SA3 */
|
||||
{ 0, CPORTS2R, 0, 0,
|
||||
{ MFIS2_INTCS, CPORTS2R, 0, 0,
|
||||
JPU6E, 0, 0, 0 } },
|
||||
{ 0xffd20104, 0, 16, /* INTAMASK */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
@ -571,7 +572,8 @@ static struct intc_prio_reg intcs_prio_registers[] = {
|
||||
{ 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, 0 } },
|
||||
{ 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, DSITX1_DSITX1_0,
|
||||
DSITX1_DSITX1_1, 0 } },
|
||||
{ 0xffd50038, 0, 16, 4, /* IPROS3 */ { 0, CPORTS2R, 0, 0 } },
|
||||
{ 0xffd50038, 0, 16, 4, /* IPROS3 */ { ENABLED_INTCS, CPORTS2R,
|
||||
0, 0 } },
|
||||
{ 0xffd5003c, 0, 16, 4, /* IPRPS3 */ { JPU6E, 0, 0, 0 } },
|
||||
};
|
||||
|
||||
@ -590,6 +592,7 @@ static struct resource intcs_resources[] __initdata = {
|
||||
|
||||
static struct intc_desc intcs_desc __initdata = {
|
||||
.name = "sh7372-intcs",
|
||||
.force_enable = ENABLED_INTCS,
|
||||
.resource = intcs_resources,
|
||||
.num_resources = ARRAY_SIZE(intcs_resources),
|
||||
.hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
|
||||
|
@ -252,10 +252,11 @@ static irqreturn_t sh73a0_intcs_demux(int irq, void *dev_id)
|
||||
|
||||
void __init sh73a0_init_irq(void)
|
||||
{
|
||||
void __iomem *gic_base = __io(0xf0001000);
|
||||
void __iomem *gic_dist_base = __io(0xf0001000);
|
||||
void __iomem *gic_cpu_base = __io(0xf0000100);
|
||||
void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
|
||||
|
||||
gic_init(0, 29, gic_base, gic_base);
|
||||
gic_init(0, 29, gic_dist_base, gic_cpu_base);
|
||||
|
||||
register_intc_controller(&intcs_desc);
|
||||
|
||||
|
@ -207,9 +207,9 @@ static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
|
||||
spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
|
||||
|
||||
if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
|
||||
__set_irq_handler_unlocked(irq, handle_level_irq);
|
||||
__set_irq_handler_unlocked(d->irq, handle_level_irq);
|
||||
else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
|
||||
__set_irq_handler_unlocked(irq, handle_edge_irq);
|
||||
__set_irq_handler_unlocked(d->irq, handle_edge_irq);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -20,6 +20,8 @@
|
||||
#ifndef __MACH_CLK_H
|
||||
#define __MACH_CLK_H
|
||||
|
||||
struct clk;
|
||||
|
||||
void tegra_periph_reset_deassert(struct clk *c);
|
||||
void tegra_periph_reset_assert(struct clk *c);
|
||||
|
||||
|
@ -20,6 +20,8 @@
|
||||
#ifndef __MACH_CLKDEV_H
|
||||
#define __MACH_CLKDEV_H
|
||||
|
||||
struct clk;
|
||||
|
||||
static inline int __clk_get(struct clk *clk)
|
||||
{
|
||||
return 1;
|
||||
|
61
arch/arm/mach-tegra/include/mach/kbc.h
Normal file
61
arch/arm/mach-tegra/include/mach/kbc.h
Normal file
@ -0,0 +1,61 @@
|
||||
/*
|
||||
* Platform definitions for tegra-kbc keyboard input driver
|
||||
*
|
||||
* Copyright (c) 2010-2011, NVIDIA Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#ifndef ASMARM_ARCH_TEGRA_KBC_H
|
||||
#define ASMARM_ARCH_TEGRA_KBC_H
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/input/matrix_keypad.h>
|
||||
|
||||
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
|
||||
#define KBC_MAX_GPIO 24
|
||||
#define KBC_MAX_KPENT 8
|
||||
#else
|
||||
#define KBC_MAX_GPIO 20
|
||||
#define KBC_MAX_KPENT 7
|
||||
#endif
|
||||
|
||||
#define KBC_MAX_ROW 16
|
||||
#define KBC_MAX_COL 8
|
||||
#define KBC_MAX_KEY (KBC_MAX_ROW * KBC_MAX_COL)
|
||||
|
||||
struct tegra_kbc_pin_cfg {
|
||||
bool is_row;
|
||||
unsigned char num;
|
||||
};
|
||||
|
||||
struct tegra_kbc_wake_key {
|
||||
u8 row:4;
|
||||
u8 col:4;
|
||||
};
|
||||
|
||||
struct tegra_kbc_platform_data {
|
||||
unsigned int debounce_cnt;
|
||||
unsigned int repeat_cnt;
|
||||
|
||||
unsigned int wake_cnt; /* 0:wake on any key >1:wake on wake_cfg */
|
||||
const struct tegra_kbc_wake_key *wake_cfg;
|
||||
|
||||
struct tegra_kbc_pin_cfg pin_cfg[KBC_MAX_GPIO];
|
||||
const struct matrix_keymap_data *keymap_data;
|
||||
|
||||
bool wakeup;
|
||||
};
|
||||
#endif
|
@ -46,24 +46,24 @@
|
||||
#define ICTLR_COP_IER_CLR 0x38
|
||||
#define ICTLR_COP_IEP_CLASS 0x3c
|
||||
|
||||
static void (*gic_mask_irq)(struct irq_data *d);
|
||||
static void (*gic_unmask_irq)(struct irq_data *d);
|
||||
static void (*tegra_gic_mask_irq)(struct irq_data *d);
|
||||
static void (*tegra_gic_unmask_irq)(struct irq_data *d);
|
||||
|
||||
#define irq_to_ictlr(irq) (((irq)-32) >> 5)
|
||||
#define irq_to_ictlr(irq) (((irq) - 32) >> 5)
|
||||
static void __iomem *tegra_ictlr_base = IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE);
|
||||
#define ictlr_to_virt(ictlr) (tegra_ictlr_base + (ictlr)*0x100)
|
||||
#define ictlr_to_virt(ictlr) (tegra_ictlr_base + (ictlr) * 0x100)
|
||||
|
||||
static void tegra_mask(struct irq_data *d)
|
||||
{
|
||||
void __iomem *addr = ictlr_to_virt(irq_to_ictlr(d->irq));
|
||||
gic_mask_irq(d);
|
||||
writel(1<<(d->irq&31), addr+ICTLR_CPU_IER_CLR);
|
||||
tegra_gic_mask_irq(d);
|
||||
writel(1 << (d->irq & 31), addr+ICTLR_CPU_IER_CLR);
|
||||
}
|
||||
|
||||
static void tegra_unmask(struct irq_data *d)
|
||||
{
|
||||
void __iomem *addr = ictlr_to_virt(irq_to_ictlr(d->irq));
|
||||
gic_unmask_irq(d);
|
||||
tegra_gic_unmask_irq(d);
|
||||
writel(1<<(d->irq&31), addr+ICTLR_CPU_IER_SET);
|
||||
}
|
||||
|
||||
@ -98,8 +98,8 @@ void __init tegra_init_irq(void)
|
||||
IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
|
||||
|
||||
gic = get_irq_chip(29);
|
||||
gic_unmask_irq = gic->irq_unmask;
|
||||
gic_mask_irq = gic->irq_mask;
|
||||
tegra_gic_unmask_irq = gic->irq_unmask;
|
||||
tegra_gic_mask_irq = gic->irq_mask;
|
||||
tegra_irq.irq_ack = gic->irq_ack;
|
||||
#ifdef CONFIG_SMP
|
||||
tegra_irq.irq_set_affinity = gic->irq_set_affinity;
|
||||
|
@ -2,17 +2,19 @@ menu "Versatile platform type"
|
||||
depends on ARCH_VERSATILE
|
||||
|
||||
config ARCH_VERSATILE_PB
|
||||
bool "Support Versatile/PB platform"
|
||||
bool "Support Versatile Platform Baseboard for ARM926EJ-S"
|
||||
select CPU_ARM926T
|
||||
select MIGHT_HAVE_PCI
|
||||
default y
|
||||
help
|
||||
Include support for the ARM(R) Versatile/PB platform.
|
||||
Include support for the ARM(R) Versatile Platform Baseboard
|
||||
for the ARM926EJ-S.
|
||||
|
||||
config MACH_VERSATILE_AB
|
||||
bool "Support Versatile/AB platform"
|
||||
bool "Support Versatile Application Baseboard for ARM926EJ-S"
|
||||
select CPU_ARM926T
|
||||
help
|
||||
Include support for the ARM(R) Versatile/AP platform.
|
||||
Include support for the ARM(R) Versatile Application Baseboard
|
||||
for the ARM926EJ-S.
|
||||
|
||||
endmenu
|
||||
|
@ -39,7 +39,7 @@ volatile int __cpuinitdata pen_release = -1;
|
||||
* observers, irrespective of whether they're taking part in coherency
|
||||
* or not. This is necessary for the hotplug code to work reliably.
|
||||
*/
|
||||
static void write_pen_release(int val)
|
||||
static void __cpuinit write_pen_release(int val)
|
||||
{
|
||||
pen_release = val;
|
||||
smp_wmb();
|
||||
|
@ -19,6 +19,7 @@
|
||||
#include <asm/mach/time.h>
|
||||
#include <asm/hardware/arm_timer.h>
|
||||
#include <asm/hardware/timer-sp.h>
|
||||
#include <asm/hardware/sp810.h>
|
||||
|
||||
#include <mach/motherboard.h>
|
||||
|
||||
@ -50,8 +51,16 @@ void __init v2m_map_io(struct map_desc *tile, size_t num)
|
||||
|
||||
static void __init v2m_timer_init(void)
|
||||
{
|
||||
u32 scctrl;
|
||||
|
||||
versatile_sched_clock_init(MMIO_P2V(V2M_SYS_24MHZ), 24000000);
|
||||
|
||||
/* Select 1MHz TIMCLK as the reference clock for SP804 timers */
|
||||
scctrl = readl(MMIO_P2V(V2M_SYSCTL + SCCTRL));
|
||||
scctrl |= SCCTRL_TIMEREN0SEL_TIMCLK;
|
||||
scctrl |= SCCTRL_TIMEREN1SEL_TIMCLK;
|
||||
writel(scctrl, MMIO_P2V(V2M_SYSCTL + SCCTRL));
|
||||
|
||||
writel(0, MMIO_P2V(V2M_TIMER0) + TIMER_CTRL);
|
||||
writel(0, MMIO_P2V(V2M_TIMER1) + TIMER_CTRL);
|
||||
|
||||
|
@ -8,6 +8,7 @@
|
||||
#ifndef __ASM_AVR32_PGALLOC_H
|
||||
#define __ASM_AVR32_PGALLOC_H
|
||||
|
||||
#include <linux/mm.h>
|
||||
#include <linux/quicklist.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/pgtable.h>
|
||||
|
@ -610,17 +610,17 @@ static void amiga_mem_console_write(struct console *co, const char *s,
|
||||
|
||||
static int __init amiga_savekmsg_setup(char *arg)
|
||||
{
|
||||
static struct resource debug_res = { .name = "Debug" };
|
||||
|
||||
if (!MACH_IS_AMIGA || strcmp(arg, "mem"))
|
||||
goto done;
|
||||
return 0;
|
||||
|
||||
if (!AMIGAHW_PRESENT(CHIP_RAM)) {
|
||||
printk("Warning: no chipram present for debugging\n");
|
||||
goto done;
|
||||
if (amiga_chip_size < SAVEKMSG_MAXMEM) {
|
||||
pr_err("Not enough chipram for debugging\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
savekmsg = amiga_chip_alloc_res(SAVEKMSG_MAXMEM, &debug_res);
|
||||
/* Just steal the block, the chipram allocator isn't functional yet */
|
||||
amiga_chip_size -= SAVEKMSG_MAXMEM;
|
||||
savekmsg = (void *)ZTWO_VADDR(CHIP_PHYSADDR + amiga_chip_size);
|
||||
savekmsg->magic1 = SAVEKMSG_MAGIC1;
|
||||
savekmsg->magic2 = SAVEKMSG_MAGIC2;
|
||||
savekmsg->magicptr = ZTWO_PADDR(savekmsg);
|
||||
@ -628,8 +628,6 @@ static int __init amiga_savekmsg_setup(char *arg)
|
||||
|
||||
amiga_console_driver.write = amiga_mem_console_write;
|
||||
register_console(&amiga_console_driver);
|
||||
|
||||
done:
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -388,9 +388,9 @@ void __init atari_init_IRQ(void)
|
||||
}
|
||||
|
||||
if (ATARIHW_PRESENT(SCC) && !atari_SCC_reset_done) {
|
||||
scc.cha_a_ctrl = 9;
|
||||
atari_scc.cha_a_ctrl = 9;
|
||||
MFPDELAY();
|
||||
scc.cha_a_ctrl = (char) 0xc0; /* hardware reset */
|
||||
atari_scc.cha_a_ctrl = (char) 0xc0; /* hardware reset */
|
||||
}
|
||||
|
||||
if (ATARIHW_PRESENT(SCU)) {
|
||||
|
@ -315,7 +315,7 @@ void __init config_atari(void)
|
||||
ATARIHW_SET(SCC_DMA);
|
||||
printk("SCC_DMA ");
|
||||
}
|
||||
if (scc_test(&scc.cha_a_ctrl)) {
|
||||
if (scc_test(&atari_scc.cha_a_ctrl)) {
|
||||
ATARIHW_SET(SCC);
|
||||
printk("SCC ");
|
||||
}
|
||||
|
@ -53,9 +53,9 @@ static inline void ata_scc_out(char c)
|
||||
{
|
||||
do {
|
||||
MFPDELAY();
|
||||
} while (!(scc.cha_b_ctrl & 0x04)); /* wait for tx buf empty */
|
||||
} while (!(atari_scc.cha_b_ctrl & 0x04)); /* wait for tx buf empty */
|
||||
MFPDELAY();
|
||||
scc.cha_b_data = c;
|
||||
atari_scc.cha_b_data = c;
|
||||
}
|
||||
|
||||
static void atari_scc_console_write(struct console *co, const char *str,
|
||||
@ -140,9 +140,9 @@ int atari_scc_console_wait_key(struct console *co)
|
||||
{
|
||||
do {
|
||||
MFPDELAY();
|
||||
} while (!(scc.cha_b_ctrl & 0x01)); /* wait for rx buf filled */
|
||||
} while (!(atari_scc.cha_b_ctrl & 0x01)); /* wait for rx buf filled */
|
||||
MFPDELAY();
|
||||
return scc.cha_b_data;
|
||||
return atari_scc.cha_b_data;
|
||||
}
|
||||
|
||||
int atari_midi_console_wait_key(struct console *co)
|
||||
@ -185,9 +185,9 @@ static void __init atari_init_mfp_port(int cflag)
|
||||
|
||||
#define SCC_WRITE(reg, val) \
|
||||
do { \
|
||||
scc.cha_b_ctrl = (reg); \
|
||||
atari_scc.cha_b_ctrl = (reg); \
|
||||
MFPDELAY(); \
|
||||
scc.cha_b_ctrl = (val); \
|
||||
atari_scc.cha_b_ctrl = (val); \
|
||||
MFPDELAY(); \
|
||||
} while (0)
|
||||
|
||||
@ -240,7 +240,7 @@ static void __init atari_init_scc_port(int cflag)
|
||||
reg3 = (cflag & CSIZE) == CS8 ? 0xc0 : 0x40;
|
||||
reg5 = (cflag & CSIZE) == CS8 ? 0x60 : 0x20 | 0x82 /* assert DTR/RTS */;
|
||||
|
||||
(void)scc.cha_b_ctrl; /* reset reg pointer */
|
||||
(void)atari_scc.cha_b_ctrl; /* reset reg pointer */
|
||||
SCC_WRITE(9, 0xc0); /* reset */
|
||||
LONG_DELAY(); /* extra delay after WR9 access */
|
||||
SCC_WRITE(4, (cflag & PARENB) ? ((cflag & PARODD) ? 0x01 : 0x03)
|
||||
|
@ -449,7 +449,7 @@ struct SCC
|
||||
u_char char_dummy3;
|
||||
u_char cha_b_data;
|
||||
};
|
||||
# define scc ((*(volatile struct SCC*)SCC_BAS))
|
||||
# define atari_scc ((*(volatile struct SCC*)SCC_BAS))
|
||||
|
||||
/* The ESCC (Z85230) in an Atari ST. The channels are reversed! */
|
||||
# define st_escc ((*(volatile struct SCC*)0xfffffa31))
|
||||
|
@ -81,18 +81,6 @@ static inline char *strncpy(char *dest, const char *src, size_t n)
|
||||
strcpy(__d + strlen(__d), (s)); \
|
||||
})
|
||||
|
||||
#define __HAVE_ARCH_STRCHR
|
||||
static inline char *strchr(const char *s, int c)
|
||||
{
|
||||
char sc, ch = c;
|
||||
|
||||
for (; (sc = *s++) != ch; ) {
|
||||
if (!sc)
|
||||
return NULL;
|
||||
}
|
||||
return (char *)s - 1;
|
||||
}
|
||||
|
||||
#ifndef CONFIG_COLDFIRE
|
||||
#define __HAVE_ARCH_STRCMP
|
||||
static inline int strcmp(const char *cs, const char *ct)
|
||||
|
@ -169,11 +169,11 @@ static int __init pdc_console_tty_driver_init(void)
|
||||
|
||||
struct console *tmp;
|
||||
|
||||
acquire_console_sem();
|
||||
console_lock();
|
||||
for_each_console(tmp)
|
||||
if (tmp == &pdc_cons)
|
||||
break;
|
||||
release_console_sem();
|
||||
console_unlock();
|
||||
|
||||
if (!tmp) {
|
||||
printk(KERN_INFO "PDC console driver not registered anymore, not creating %s\n", pdc_cons.name);
|
||||
|
@ -15,6 +15,7 @@ config SUPERH
|
||||
select HAVE_KERNEL_GZIP
|
||||
select HAVE_KERNEL_BZIP2
|
||||
select HAVE_KERNEL_LZMA
|
||||
select HAVE_KERNEL_XZ
|
||||
select HAVE_KERNEL_LZO
|
||||
select HAVE_SYSCALL_TRACEPOINTS
|
||||
select HAVE_REGS_AND_STACK_ACCESS_API
|
||||
|
@ -200,7 +200,7 @@ endif
|
||||
libs-$(CONFIG_SUPERH32) := arch/sh/lib/ $(libs-y)
|
||||
libs-$(CONFIG_SUPERH64) := arch/sh/lib64/ $(libs-y)
|
||||
|
||||
BOOT_TARGETS = uImage uImage.bz2 uImage.gz uImage.lzma uImage.lzo \
|
||||
BOOT_TARGETS = uImage uImage.bz2 uImage.gz uImage.lzma uImage.xz uImage.lzo \
|
||||
uImage.srec uImage.bin zImage vmlinux.bin vmlinux.srec \
|
||||
romImage
|
||||
PHONY += $(BOOT_TARGETS)
|
||||
@ -230,5 +230,6 @@ define archhelp
|
||||
@echo '* uImage.gz - Kernel-only image for U-Boot (gzip)'
|
||||
@echo ' uImage.bz2 - Kernel-only image for U-Boot (bzip2)'
|
||||
@echo ' uImage.lzma - Kernel-only image for U-Boot (lzma)'
|
||||
@echo ' uImage.xz - Kernel-only image for U-Boot (xz)'
|
||||
@echo ' uImage.lzo - Kernel-only image for U-Boot (lzo)'
|
||||
endef
|
||||
|
@ -1294,6 +1294,7 @@ static int __init arch_setup(void)
|
||||
i2c_register_board_info(1, i2c1_devices,
|
||||
ARRAY_SIZE(i2c1_devices));
|
||||
|
||||
#if defined(CONFIG_VIDEO_SH_VOU) || defined(CONFIG_VIDEO_SH_VOU_MODULE)
|
||||
/* VOU */
|
||||
gpio_request(GPIO_FN_DV_D15, NULL);
|
||||
gpio_request(GPIO_FN_DV_D14, NULL);
|
||||
@ -1325,6 +1326,7 @@ static int __init arch_setup(void)
|
||||
|
||||
/* Remove reset */
|
||||
gpio_set_value(GPIO_PTG4, 1);
|
||||
#endif
|
||||
|
||||
return platform_add_devices(ecovec_devices,
|
||||
ARRAY_SIZE(ecovec_devices));
|
||||
|
@ -24,12 +24,13 @@ suffix-y := bin
|
||||
suffix-$(CONFIG_KERNEL_GZIP) := gz
|
||||
suffix-$(CONFIG_KERNEL_BZIP2) := bz2
|
||||
suffix-$(CONFIG_KERNEL_LZMA) := lzma
|
||||
suffix-$(CONFIG_KERNEL_XZ) := xz
|
||||
suffix-$(CONFIG_KERNEL_LZO) := lzo
|
||||
|
||||
targets := zImage vmlinux.srec romImage uImage uImage.srec uImage.gz \
|
||||
uImage.bz2 uImage.lzma uImage.lzo uImage.bin
|
||||
uImage.bz2 uImage.lzma uImage.xz uImage.lzo uImage.bin
|
||||
extra-y += vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma \
|
||||
vmlinux.bin.lzo
|
||||
vmlinux.bin.xz vmlinux.bin.lzo
|
||||
subdir- := compressed romimage
|
||||
|
||||
$(obj)/zImage: $(obj)/compressed/vmlinux FORCE
|
||||
@ -76,6 +77,9 @@ $(obj)/vmlinux.bin.bz2: $(obj)/vmlinux.bin FORCE
|
||||
$(obj)/vmlinux.bin.lzma: $(obj)/vmlinux.bin FORCE
|
||||
$(call if_changed,lzma)
|
||||
|
||||
$(obj)/vmlinux.bin.xz: $(obj)/vmlinux.bin FORCE
|
||||
$(call if_changed,xzkern)
|
||||
|
||||
$(obj)/vmlinux.bin.lzo: $(obj)/vmlinux.bin FORCE
|
||||
$(call if_changed,lzo)
|
||||
|
||||
@ -88,6 +92,9 @@ $(obj)/uImage.gz: $(obj)/vmlinux.bin.gz
|
||||
$(obj)/uImage.lzma: $(obj)/vmlinux.bin.lzma
|
||||
$(call if_changed,uimage,lzma)
|
||||
|
||||
$(obj)/uImage.xz: $(obj)/vmlinux.bin.xz
|
||||
$(call if_changed,uimage,xz)
|
||||
|
||||
$(obj)/uImage.lzo: $(obj)/vmlinux.bin.lzo
|
||||
$(call if_changed,uimage,lzo)
|
||||
|
||||
|
@ -6,7 +6,7 @@
|
||||
|
||||
targets := vmlinux vmlinux.bin vmlinux.bin.gz \
|
||||
vmlinux.bin.bz2 vmlinux.bin.lzma \
|
||||
vmlinux.bin.lzo \
|
||||
vmlinux.bin.xz vmlinux.bin.lzo \
|
||||
head_$(BITS).o misc.o piggy.o
|
||||
|
||||
OBJECTS = $(obj)/head_$(BITS).o $(obj)/misc.o $(obj)/cache.o
|
||||
@ -50,6 +50,8 @@ $(obj)/vmlinux.bin.bz2: $(vmlinux.bin.all-y) FORCE
|
||||
$(call if_changed,bzip2)
|
||||
$(obj)/vmlinux.bin.lzma: $(vmlinux.bin.all-y) FORCE
|
||||
$(call if_changed,lzma)
|
||||
$(obj)/vmlinux.bin.xz: $(vmlinux.bin.all-y) FORCE
|
||||
$(call if_changed,xzkern)
|
||||
$(obj)/vmlinux.bin.lzo: $(vmlinux.bin.all-y) FORCE
|
||||
$(call if_changed,lzo)
|
||||
|
||||
|
@ -61,6 +61,10 @@ static unsigned long free_mem_end_ptr;
|
||||
#include "../../../../lib/decompress_unlzma.c"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_KERNEL_XZ
|
||||
#include "../../../../lib/decompress_unxz.c"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_KERNEL_LZO
|
||||
#include "../../../../lib/decompress_unlzo.c"
|
||||
#endif
|
||||
|
@ -134,6 +134,7 @@ typedef pte_t *pte_addr_t;
|
||||
extern void pgtable_cache_init(void);
|
||||
|
||||
struct vm_area_struct;
|
||||
struct mm_struct;
|
||||
|
||||
extern void __update_cache(struct vm_area_struct *vma,
|
||||
unsigned long address, pte_t pte);
|
||||
|
@ -230,10 +230,10 @@ static struct platform_device *sh7750_devices[] __initdata = {
|
||||
static int __init sh7750_devices_setup(void)
|
||||
{
|
||||
if (mach_is_rts7751r2d()) {
|
||||
platform_register_device(&scif_device);
|
||||
platform_device_register(&scif_device);
|
||||
} else {
|
||||
platform_register_device(&sci_device);
|
||||
platform_register_device(&scif_device);
|
||||
platform_device_register(&sci_device);
|
||||
platform_device_register(&scif_device);
|
||||
}
|
||||
|
||||
return platform_add_devices(sh7750_devices,
|
||||
|
@ -17,6 +17,7 @@
|
||||
static DEFINE_PER_CPU(struct cpu, cpu_devices);
|
||||
|
||||
cpumask_t cpu_core_map[NR_CPUS];
|
||||
EXPORT_SYMBOL(cpu_core_map);
|
||||
|
||||
static cpumask_t cpu_coregroup_map(unsigned int cpu)
|
||||
{
|
||||
|
@ -558,13 +558,12 @@ static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
|
||||
static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
|
||||
pmd_t *pmdp, pmd_t pmd)
|
||||
{
|
||||
#if PAGETABLE_LEVELS >= 3
|
||||
if (sizeof(pmdval_t) > sizeof(long))
|
||||
/* 5 arg words */
|
||||
pv_mmu_ops.set_pmd_at(mm, addr, pmdp, pmd);
|
||||
else
|
||||
PVOP_VCALL4(pv_mmu_ops.set_pmd_at, mm, addr, pmdp, pmd.pmd);
|
||||
#endif
|
||||
PVOP_VCALL4(pv_mmu_ops.set_pmd_at, mm, addr, pmdp,
|
||||
native_pmd_val(pmd));
|
||||
}
|
||||
#endif
|
||||
|
||||
|
@ -273,34 +273,34 @@ do { \
|
||||
typeof(var) pxo_new__ = (nval); \
|
||||
switch (sizeof(var)) { \
|
||||
case 1: \
|
||||
asm("\n1:mov "__percpu_arg(1)",%%al" \
|
||||
"\n\tcmpxchgb %2, "__percpu_arg(1) \
|
||||
asm("\n\tmov "__percpu_arg(1)",%%al" \
|
||||
"\n1:\tcmpxchgb %2, "__percpu_arg(1) \
|
||||
"\n\tjnz 1b" \
|
||||
: "=a" (pxo_ret__), "+m" (var) \
|
||||
: "=&a" (pxo_ret__), "+m" (var) \
|
||||
: "q" (pxo_new__) \
|
||||
: "memory"); \
|
||||
break; \
|
||||
case 2: \
|
||||
asm("\n1:mov "__percpu_arg(1)",%%ax" \
|
||||
"\n\tcmpxchgw %2, "__percpu_arg(1) \
|
||||
asm("\n\tmov "__percpu_arg(1)",%%ax" \
|
||||
"\n1:\tcmpxchgw %2, "__percpu_arg(1) \
|
||||
"\n\tjnz 1b" \
|
||||
: "=a" (pxo_ret__), "+m" (var) \
|
||||
: "=&a" (pxo_ret__), "+m" (var) \
|
||||
: "r" (pxo_new__) \
|
||||
: "memory"); \
|
||||
break; \
|
||||
case 4: \
|
||||
asm("\n1:mov "__percpu_arg(1)",%%eax" \
|
||||
"\n\tcmpxchgl %2, "__percpu_arg(1) \
|
||||
asm("\n\tmov "__percpu_arg(1)",%%eax" \
|
||||
"\n1:\tcmpxchgl %2, "__percpu_arg(1) \
|
||||
"\n\tjnz 1b" \
|
||||
: "=a" (pxo_ret__), "+m" (var) \
|
||||
: "=&a" (pxo_ret__), "+m" (var) \
|
||||
: "r" (pxo_new__) \
|
||||
: "memory"); \
|
||||
break; \
|
||||
case 8: \
|
||||
asm("\n1:mov "__percpu_arg(1)",%%rax" \
|
||||
"\n\tcmpxchgq %2, "__percpu_arg(1) \
|
||||
asm("\n\tmov "__percpu_arg(1)",%%rax" \
|
||||
"\n1:\tcmpxchgq %2, "__percpu_arg(1) \
|
||||
"\n\tjnz 1b" \
|
||||
: "=a" (pxo_ret__), "+m" (var) \
|
||||
: "=&a" (pxo_ret__), "+m" (var) \
|
||||
: "r" (pxo_new__) \
|
||||
: "memory"); \
|
||||
break; \
|
||||
|
@ -1,22 +0,0 @@
|
||||
#ifndef _ASM_X86_SYSTEM_64_H
|
||||
#define _ASM_X86_SYSTEM_64_H
|
||||
|
||||
#include <asm/segment.h>
|
||||
#include <asm/cmpxchg.h>
|
||||
|
||||
|
||||
static inline unsigned long read_cr8(void)
|
||||
{
|
||||
unsigned long cr8;
|
||||
asm volatile("movq %%cr8,%0" : "=r" (cr8));
|
||||
return cr8;
|
||||
}
|
||||
|
||||
static inline void write_cr8(unsigned long val)
|
||||
{
|
||||
asm volatile("movq %0,%%cr8" :: "r" (val) : "memory");
|
||||
}
|
||||
|
||||
#include <linux/irqflags.h>
|
||||
|
||||
#endif /* _ASM_X86_SYSTEM_64_H */
|
@ -149,13 +149,13 @@ void dump_trace(struct task_struct *task,
|
||||
unsigned used = 0;
|
||||
struct thread_info *tinfo;
|
||||
int graph = 0;
|
||||
unsigned long dummy;
|
||||
unsigned long bp;
|
||||
|
||||
if (!task)
|
||||
task = current;
|
||||
|
||||
if (!stack) {
|
||||
unsigned long dummy;
|
||||
stack = &dummy;
|
||||
if (task && task != current)
|
||||
stack = (unsigned long *)task->thread.sp;
|
||||
|
@ -241,21 +241,15 @@ void __init xen_build_dynamic_phys_to_machine(void)
|
||||
* As long as the mfn_list has enough entries to completely
|
||||
* fill a p2m page, pointing into the array is ok. But if
|
||||
* not the entries beyond the last pfn will be undefined.
|
||||
* And guessing that the 'what-ever-there-is' does not take it
|
||||
* too kindly when changing it to invalid markers, a new page
|
||||
* is allocated, initialized and filled with the valid part.
|
||||
*/
|
||||
if (unlikely(pfn + P2M_PER_PAGE > max_pfn)) {
|
||||
unsigned long p2midx;
|
||||
unsigned long *p2m = extend_brk(PAGE_SIZE, PAGE_SIZE);
|
||||
p2m_init(p2m);
|
||||
|
||||
for (p2midx = 0; pfn + p2midx < max_pfn; p2midx++) {
|
||||
p2m[p2midx] = mfn_list[pfn + p2midx];
|
||||
}
|
||||
p2m_top[topidx][mididx] = p2m;
|
||||
} else
|
||||
p2m_top[topidx][mididx] = &mfn_list[pfn];
|
||||
p2midx = max_pfn % P2M_PER_PAGE;
|
||||
for ( ; p2midx < P2M_PER_PAGE; p2midx++)
|
||||
mfn_list[pfn + p2midx] = INVALID_P2M_ENTRY;
|
||||
}
|
||||
p2m_top[topidx][mididx] = &mfn_list[pfn];
|
||||
}
|
||||
|
||||
m2p_override_init();
|
||||
|
@ -179,8 +179,13 @@ char * __init xen_memory_setup(void)
|
||||
e820.nr_map = 0;
|
||||
xen_extra_mem_start = mem_end;
|
||||
for (i = 0; i < memmap.nr_entries; i++) {
|
||||
unsigned long long end = map[i].addr + map[i].size;
|
||||
unsigned long long end;
|
||||
|
||||
/* Guard against non-page aligned E820 entries. */
|
||||
if (map[i].type == E820_RAM)
|
||||
map[i].size -= (map[i].size + map[i].addr) % PAGE_SIZE;
|
||||
|
||||
end = map[i].addr + map[i].size;
|
||||
if (map[i].type == E820_RAM && end > mem_end) {
|
||||
/* RAM off the end - may be partially included */
|
||||
u64 delta = min(map[i].size, end - mem_end);
|
||||
@ -350,6 +355,7 @@ void __init xen_arch_setup(void)
|
||||
boot_cpu_data.hlt_works_ok = 1;
|
||||
#endif
|
||||
pm_idle = default_idle;
|
||||
boot_option_idle_override = IDLE_HALT;
|
||||
|
||||
fiddle_vdso();
|
||||
}
|
||||
|
@ -260,6 +260,7 @@ static const struct pci_device_id ahci_pci_tbl[] = {
|
||||
{ PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
|
||||
{ PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
|
||||
{ PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
|
||||
{ PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
|
||||
|
||||
/* JMicron 360/1/3/5/6, match class to avoid IDE function */
|
||||
{ PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
|
||||
@ -379,6 +380,8 @@ static const struct pci_device_id ahci_pci_tbl[] = {
|
||||
{ PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
|
||||
{ PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
|
||||
{ PCI_DEVICE(0x1b4b, 0x9123),
|
||||
.class = PCI_CLASS_STORAGE_SATA_AHCI,
|
||||
.class_mask = 0xffffff,
|
||||
.driver_data = board_ahci_yes_fbs }, /* 88se9128 */
|
||||
|
||||
/* Promise */
|
||||
|
@ -4138,6 +4138,7 @@ static const struct ata_blacklist_entry ata_device_blacklist [] = {
|
||||
* device and controller are SATA.
|
||||
*/
|
||||
{ "PIONEER DVD-RW DVRTD08", "1.00", ATA_HORKAGE_NOSETXFER },
|
||||
{ "PIONEER DVD-RW DVR-212D", "1.28", ATA_HORKAGE_NOSETXFER },
|
||||
|
||||
/* End Marker */
|
||||
{ }
|
||||
|
@ -1099,9 +1099,9 @@ static int ata_scsi_dev_config(struct scsi_device *sdev,
|
||||
struct request_queue *q = sdev->request_queue;
|
||||
void *buf;
|
||||
|
||||
/* set the min alignment and padding */
|
||||
blk_queue_update_dma_alignment(sdev->request_queue,
|
||||
ATA_DMA_PAD_SZ - 1);
|
||||
sdev->sector_size = ATA_SECT_SIZE;
|
||||
|
||||
/* set DMA padding */
|
||||
blk_queue_update_dma_pad(sdev->request_queue,
|
||||
ATA_DMA_PAD_SZ - 1);
|
||||
|
||||
@ -1115,13 +1115,25 @@ static int ata_scsi_dev_config(struct scsi_device *sdev,
|
||||
|
||||
blk_queue_dma_drain(q, atapi_drain_needed, buf, ATAPI_MAX_DRAIN);
|
||||
} else {
|
||||
/* ATA devices must be sector aligned */
|
||||
sdev->sector_size = ata_id_logical_sector_size(dev->id);
|
||||
blk_queue_update_dma_alignment(sdev->request_queue,
|
||||
sdev->sector_size - 1);
|
||||
sdev->manage_start_stop = 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* ata_pio_sectors() expects buffer for each sector to not cross
|
||||
* page boundary. Enforce it by requiring buffers to be sector
|
||||
* aligned, which works iff sector_size is not larger than
|
||||
* PAGE_SIZE. ATAPI devices also need the alignment as
|
||||
* IDENTIFY_PACKET is executed as ATA_PROT_PIO.
|
||||
*/
|
||||
if (sdev->sector_size > PAGE_SIZE)
|
||||
ata_dev_printk(dev, KERN_WARNING,
|
||||
"sector_size=%u > PAGE_SIZE, PIO may malfunction\n",
|
||||
sdev->sector_size);
|
||||
|
||||
blk_queue_update_dma_alignment(sdev->request_queue,
|
||||
sdev->sector_size - 1);
|
||||
|
||||
if (dev->flags & ATA_DFLAG_AN)
|
||||
set_bit(SDEV_EVT_MEDIA_CHANGE, sdev->supported_events);
|
||||
|
||||
|
@ -25,7 +25,7 @@
|
||||
#include <linux/libata.h>
|
||||
|
||||
#define DRV_NAME "pata_hpt366"
|
||||
#define DRV_VERSION "0.6.9"
|
||||
#define DRV_VERSION "0.6.10"
|
||||
|
||||
struct hpt_clock {
|
||||
u8 xfer_mode;
|
||||
@ -160,8 +160,8 @@ static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr,
|
||||
|
||||
while (list[i] != NULL) {
|
||||
if (!strcmp(list[i], model_num)) {
|
||||
printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n",
|
||||
modestr, list[i]);
|
||||
pr_warning(DRV_NAME ": %s is not supported for %s.\n",
|
||||
modestr, list[i]);
|
||||
return 1;
|
||||
}
|
||||
i++;
|
||||
|
@ -24,7 +24,7 @@
|
||||
#include <linux/libata.h>
|
||||
|
||||
#define DRV_NAME "pata_hpt37x"
|
||||
#define DRV_VERSION "0.6.18"
|
||||
#define DRV_VERSION "0.6.22"
|
||||
|
||||
struct hpt_clock {
|
||||
u8 xfer_speed;
|
||||
@ -229,8 +229,8 @@ static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr,
|
||||
|
||||
while (list[i] != NULL) {
|
||||
if (!strcmp(list[i], model_num)) {
|
||||
printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n",
|
||||
modestr, list[i]);
|
||||
pr_warning(DRV_NAME ": %s is not supported for %s.\n",
|
||||
modestr, list[i]);
|
||||
return 1;
|
||||
}
|
||||
i++;
|
||||
@ -642,7 +642,6 @@ static struct ata_port_operations hpt372_port_ops = {
|
||||
static struct ata_port_operations hpt374_fn1_port_ops = {
|
||||
.inherits = &hpt372_port_ops,
|
||||
.cable_detect = hpt374_fn1_cable_detect,
|
||||
.prereset = hpt37x_pre_reset,
|
||||
};
|
||||
|
||||
/**
|
||||
@ -803,7 +802,7 @@ static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
|
||||
.udma_mask = ATA_UDMA6,
|
||||
.port_ops = &hpt302_port_ops
|
||||
};
|
||||
/* HPT374 - UDMA100, function 1 uses different prereset method */
|
||||
/* HPT374 - UDMA100, function 1 uses different cable_detect method */
|
||||
static const struct ata_port_info info_hpt374_fn0 = {
|
||||
.flags = ATA_FLAG_SLAVE_POSS,
|
||||
.pio_mask = ATA_PIO4,
|
||||
@ -838,7 +837,8 @@ static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
if (dev->device == PCI_DEVICE_ID_TTI_HPT366) {
|
||||
switch (dev->device) {
|
||||
case PCI_DEVICE_ID_TTI_HPT366:
|
||||
/* May be a later chip in disguise. Check */
|
||||
/* Older chips are in the HPT366 driver. Ignore them */
|
||||
if (rev < 3)
|
||||
@ -863,54 +863,50 @@ static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
|
||||
chip_table = &hpt372;
|
||||
break;
|
||||
default:
|
||||
printk(KERN_ERR "pata_hpt37x: Unknown HPT366 subtype, "
|
||||
pr_err(DRV_NAME ": Unknown HPT366 subtype, "
|
||||
"please report (%d).\n", rev);
|
||||
return -ENODEV;
|
||||
}
|
||||
} else {
|
||||
switch (dev->device) {
|
||||
case PCI_DEVICE_ID_TTI_HPT372:
|
||||
/* 372N if rev >= 2 */
|
||||
if (rev >= 2)
|
||||
return -ENODEV;
|
||||
ppi[0] = &info_hpt372;
|
||||
chip_table = &hpt372a;
|
||||
break;
|
||||
case PCI_DEVICE_ID_TTI_HPT302:
|
||||
/* 302N if rev > 1 */
|
||||
if (rev > 1)
|
||||
return -ENODEV;
|
||||
ppi[0] = &info_hpt302;
|
||||
/* Check this */
|
||||
chip_table = &hpt302;
|
||||
break;
|
||||
case PCI_DEVICE_ID_TTI_HPT371:
|
||||
if (rev > 1)
|
||||
return -ENODEV;
|
||||
ppi[0] = &info_hpt302;
|
||||
chip_table = &hpt371;
|
||||
/*
|
||||
* Single channel device, master is not present
|
||||
* but the BIOS (or us for non x86) must mark it
|
||||
* absent
|
||||
*/
|
||||
pci_read_config_byte(dev, 0x50, &mcr1);
|
||||
mcr1 &= ~0x04;
|
||||
pci_write_config_byte(dev, 0x50, mcr1);
|
||||
break;
|
||||
case PCI_DEVICE_ID_TTI_HPT374:
|
||||
chip_table = &hpt374;
|
||||
if (!(PCI_FUNC(dev->devfn) & 1))
|
||||
*ppi = &info_hpt374_fn0;
|
||||
else
|
||||
*ppi = &info_hpt374_fn1;
|
||||
break;
|
||||
default:
|
||||
printk(KERN_ERR
|
||||
"pata_hpt37x: PCI table is bogus, please report (%d).\n",
|
||||
dev->device);
|
||||
return -ENODEV;
|
||||
}
|
||||
break;
|
||||
case PCI_DEVICE_ID_TTI_HPT372:
|
||||
/* 372N if rev >= 2 */
|
||||
if (rev >= 2)
|
||||
return -ENODEV;
|
||||
ppi[0] = &info_hpt372;
|
||||
chip_table = &hpt372a;
|
||||
break;
|
||||
case PCI_DEVICE_ID_TTI_HPT302:
|
||||
/* 302N if rev > 1 */
|
||||
if (rev > 1)
|
||||
return -ENODEV;
|
||||
ppi[0] = &info_hpt302;
|
||||
/* Check this */
|
||||
chip_table = &hpt302;
|
||||
break;
|
||||
case PCI_DEVICE_ID_TTI_HPT371:
|
||||
if (rev > 1)
|
||||
return -ENODEV;
|
||||
ppi[0] = &info_hpt302;
|
||||
chip_table = &hpt371;
|
||||
/*
|
||||
* Single channel device, master is not present but the BIOS
|
||||
* (or us for non x86) must mark it absent
|
||||
*/
|
||||
pci_read_config_byte(dev, 0x50, &mcr1);
|
||||
mcr1 &= ~0x04;
|
||||
pci_write_config_byte(dev, 0x50, mcr1);
|
||||
break;
|
||||
case PCI_DEVICE_ID_TTI_HPT374:
|
||||
chip_table = &hpt374;
|
||||
if (!(PCI_FUNC(dev->devfn) & 1))
|
||||
*ppi = &info_hpt374_fn0;
|
||||
else
|
||||
*ppi = &info_hpt374_fn1;
|
||||
break;
|
||||
default:
|
||||
pr_err(DRV_NAME ": PCI table is bogus, please report (%d).\n",
|
||||
dev->device);
|
||||
return -ENODEV;
|
||||
}
|
||||
/* Ok so this is a chip we support */
|
||||
|
||||
@ -957,8 +953,7 @@ static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
|
||||
u8 sr;
|
||||
u32 total = 0;
|
||||
|
||||
printk(KERN_WARNING
|
||||
"pata_hpt37x: BIOS has not set timing clocks.\n");
|
||||
pr_warning(DRV_NAME ": BIOS has not set timing clocks.\n");
|
||||
|
||||
/* This is the process the HPT371 BIOS is reported to use */
|
||||
for (i = 0; i < 128; i++) {
|
||||
@ -1014,7 +1009,7 @@ static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
|
||||
(f_high << 16) | f_low | 0x100);
|
||||
}
|
||||
if (adjust == 8) {
|
||||
printk(KERN_ERR "pata_hpt37x: DPLL did not stabilize!\n");
|
||||
pr_err(DRV_NAME ": DPLL did not stabilize!\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
if (dpll == 3)
|
||||
@ -1022,8 +1017,8 @@ static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
|
||||
else
|
||||
private_data = (void *)hpt37x_timings_50;
|
||||
|
||||
printk(KERN_INFO "pata_hpt37x: bus clock %dMHz, using %dMHz DPLL.\n",
|
||||
MHz[clock_slot], MHz[dpll]);
|
||||
pr_info(DRV_NAME ": bus clock %dMHz, using %dMHz DPLL.\n",
|
||||
MHz[clock_slot], MHz[dpll]);
|
||||
} else {
|
||||
private_data = (void *)chip_table->clocks[clock_slot];
|
||||
/*
|
||||
@ -1036,8 +1031,9 @@ static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
|
||||
ppi[0] = &info_hpt370_33;
|
||||
if (clock_slot < 2 && ppi[0] == &info_hpt370a)
|
||||
ppi[0] = &info_hpt370a_33;
|
||||
printk(KERN_INFO "pata_hpt37x: %s using %dMHz bus clock.\n",
|
||||
chip_table->name, MHz[clock_slot]);
|
||||
|
||||
pr_info(DRV_NAME ": %s using %dMHz bus clock.\n",
|
||||
chip_table->name, MHz[clock_slot]);
|
||||
}
|
||||
|
||||
/* Now kick off ATA set up */
|
||||
|
@ -25,7 +25,7 @@
|
||||
#include <linux/libata.h>
|
||||
|
||||
#define DRV_NAME "pata_hpt3x2n"
|
||||
#define DRV_VERSION "0.3.13"
|
||||
#define DRV_VERSION "0.3.14"
|
||||
|
||||
enum {
|
||||
HPT_PCI_FAST = (1 << 31),
|
||||
@ -418,7 +418,7 @@ static int hpt3x2n_pci_clock(struct pci_dev *pdev)
|
||||
u16 sr;
|
||||
u32 total = 0;
|
||||
|
||||
printk(KERN_WARNING "pata_hpt3x2n: BIOS clock data not set.\n");
|
||||
pr_warning(DRV_NAME ": BIOS clock data not set.\n");
|
||||
|
||||
/* This is the process the HPT371 BIOS is reported to use */
|
||||
for (i = 0; i < 128; i++) {
|
||||
@ -528,8 +528,7 @@ hpt372n:
|
||||
ppi[0] = &info_hpt372n;
|
||||
break;
|
||||
default:
|
||||
printk(KERN_ERR
|
||||
"pata_hpt3x2n: PCI table is bogus please report (%d).\n",
|
||||
pr_err(DRV_NAME ": PCI table is bogus, please report (%d).\n",
|
||||
dev->device);
|
||||
return -ENODEV;
|
||||
}
|
||||
@ -579,12 +578,11 @@ hpt372n:
|
||||
pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low);
|
||||
}
|
||||
if (adjust == 8) {
|
||||
printk(KERN_ERR "pata_hpt3x2n: DPLL did not stabilize!\n");
|
||||
pr_err(DRV_NAME ": DPLL did not stabilize!\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
printk(KERN_INFO "pata_hpt37x: bus clock %dMHz, using 66MHz DPLL.\n",
|
||||
pci_mhz);
|
||||
pr_info(DRV_NAME ": bus clock %dMHz, using 66MHz DPLL.\n", pci_mhz);
|
||||
|
||||
/*
|
||||
* Set our private data up. We only need a few flags
|
||||
|
@ -610,7 +610,7 @@ static struct scsi_host_template mpc52xx_ata_sht = {
|
||||
};
|
||||
|
||||
static struct ata_port_operations mpc52xx_ata_port_ops = {
|
||||
.inherits = &ata_sff_port_ops,
|
||||
.inherits = &ata_bmdma_port_ops,
|
||||
.sff_dev_select = mpc52xx_ata_dev_select,
|
||||
.set_piomode = mpc52xx_ata_set_piomode,
|
||||
.set_dmamode = mpc52xx_ata_set_dmamode,
|
||||
|
@ -151,7 +151,7 @@ static int fetch_stats(struct atm_dev *dev,struct idt77105_stats __user *arg,int
|
||||
spin_unlock_irqrestore(&idt77105_priv_lock, flags);
|
||||
if (arg == NULL)
|
||||
return 0;
|
||||
return copy_to_user(arg, &PRIV(dev)->stats,
|
||||
return copy_to_user(arg, &stats,
|
||||
sizeof(struct idt77105_stats)) ? -EFAULT : 0;
|
||||
}
|
||||
|
||||
|
@ -407,12 +407,15 @@ static int rpm_suspend(struct device *dev, int rpmflags)
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* Maybe the parent is now able to suspend. */
|
||||
if (parent && !parent->power.ignore_children && !dev->power.irq_safe) {
|
||||
spin_unlock_irq(&dev->power.lock);
|
||||
spin_unlock(&dev->power.lock);
|
||||
|
||||
pm_request_idle(parent);
|
||||
spin_lock(&parent->power.lock);
|
||||
rpm_idle(parent, RPM_ASYNC);
|
||||
spin_unlock(&parent->power.lock);
|
||||
|
||||
spin_lock_irq(&dev->power.lock);
|
||||
spin_lock(&dev->power.lock);
|
||||
}
|
||||
|
||||
out:
|
||||
|
@ -47,33 +47,16 @@ MODULE_DEVICE_TABLE(usb, ath3k_table);
|
||||
#define USB_REQ_DFU_DNLOAD 1
|
||||
#define BULK_SIZE 4096
|
||||
|
||||
struct ath3k_data {
|
||||
struct usb_device *udev;
|
||||
u8 *fw_data;
|
||||
u32 fw_size;
|
||||
u32 fw_sent;
|
||||
};
|
||||
|
||||
static int ath3k_load_firmware(struct ath3k_data *data,
|
||||
unsigned char *firmware,
|
||||
int count)
|
||||
static int ath3k_load_firmware(struct usb_device *udev,
|
||||
const struct firmware *firmware)
|
||||
{
|
||||
u8 *send_buf;
|
||||
int err, pipe, len, size, sent = 0;
|
||||
int count = firmware->size;
|
||||
|
||||
BT_DBG("ath3k %p udev %p", data, data->udev);
|
||||
BT_DBG("udev %p", udev);
|
||||
|
||||
pipe = usb_sndctrlpipe(data->udev, 0);
|
||||
|
||||
if ((usb_control_msg(data->udev, pipe,
|
||||
USB_REQ_DFU_DNLOAD,
|
||||
USB_TYPE_VENDOR, 0, 0,
|
||||
firmware, 20, USB_CTRL_SET_TIMEOUT)) < 0) {
|
||||
BT_ERR("Can't change to loading configuration err");
|
||||
return -EBUSY;
|
||||
}
|
||||
sent += 20;
|
||||
count -= 20;
|
||||
pipe = usb_sndctrlpipe(udev, 0);
|
||||
|
||||
send_buf = kmalloc(BULK_SIZE, GFP_ATOMIC);
|
||||
if (!send_buf) {
|
||||
@ -81,12 +64,23 @@ static int ath3k_load_firmware(struct ath3k_data *data,
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
memcpy(send_buf, firmware->data, 20);
|
||||
if ((err = usb_control_msg(udev, pipe,
|
||||
USB_REQ_DFU_DNLOAD,
|
||||
USB_TYPE_VENDOR, 0, 0,
|
||||
send_buf, 20, USB_CTRL_SET_TIMEOUT)) < 0) {
|
||||
BT_ERR("Can't change to loading configuration err");
|
||||
goto error;
|
||||
}
|
||||
sent += 20;
|
||||
count -= 20;
|
||||
|
||||
while (count) {
|
||||
size = min_t(uint, count, BULK_SIZE);
|
||||
pipe = usb_sndbulkpipe(data->udev, 0x02);
|
||||
memcpy(send_buf, firmware + sent, size);
|
||||
pipe = usb_sndbulkpipe(udev, 0x02);
|
||||
memcpy(send_buf, firmware->data + sent, size);
|
||||
|
||||
err = usb_bulk_msg(data->udev, pipe, send_buf, size,
|
||||
err = usb_bulk_msg(udev, pipe, send_buf, size,
|
||||
&len, 3000);
|
||||
|
||||
if (err || (len != size)) {
|
||||
@ -112,57 +106,28 @@ static int ath3k_probe(struct usb_interface *intf,
|
||||
{
|
||||
const struct firmware *firmware;
|
||||
struct usb_device *udev = interface_to_usbdev(intf);
|
||||
struct ath3k_data *data;
|
||||
int size;
|
||||
|
||||
BT_DBG("intf %p id %p", intf, id);
|
||||
|
||||
if (intf->cur_altsetting->desc.bInterfaceNumber != 0)
|
||||
return -ENODEV;
|
||||
|
||||
data = kzalloc(sizeof(*data), GFP_KERNEL);
|
||||
if (!data)
|
||||
return -ENOMEM;
|
||||
|
||||
data->udev = udev;
|
||||
|
||||
if (request_firmware(&firmware, "ath3k-1.fw", &udev->dev) < 0) {
|
||||
kfree(data);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
size = max_t(uint, firmware->size, 4096);
|
||||
data->fw_data = kmalloc(size, GFP_KERNEL);
|
||||
if (!data->fw_data) {
|
||||
if (ath3k_load_firmware(udev, firmware)) {
|
||||
release_firmware(firmware);
|
||||
kfree(data);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
memcpy(data->fw_data, firmware->data, firmware->size);
|
||||
data->fw_size = firmware->size;
|
||||
data->fw_sent = 0;
|
||||
release_firmware(firmware);
|
||||
|
||||
usb_set_intfdata(intf, data);
|
||||
if (ath3k_load_firmware(data, data->fw_data, data->fw_size)) {
|
||||
usb_set_intfdata(intf, NULL);
|
||||
kfree(data->fw_data);
|
||||
kfree(data);
|
||||
return -EIO;
|
||||
}
|
||||
release_firmware(firmware);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void ath3k_disconnect(struct usb_interface *intf)
|
||||
{
|
||||
struct ath3k_data *data = usb_get_intfdata(intf);
|
||||
|
||||
BT_DBG("ath3k_disconnect intf %p", intf);
|
||||
|
||||
kfree(data->fw_data);
|
||||
kfree(data);
|
||||
}
|
||||
|
||||
static struct usb_driver ath3k_driver = {
|
||||
|
@ -183,16 +183,16 @@ bfin_jc_circ_write(const unsigned char *buf, int count)
|
||||
}
|
||||
|
||||
#ifndef CONFIG_BFIN_JTAG_COMM_CONSOLE
|
||||
# define acquire_console_sem()
|
||||
# define release_console_sem()
|
||||
# define console_lock()
|
||||
# define console_unlock()
|
||||
#endif
|
||||
static int
|
||||
bfin_jc_write(struct tty_struct *tty, const unsigned char *buf, int count)
|
||||
{
|
||||
int i;
|
||||
acquire_console_sem();
|
||||
console_lock();
|
||||
i = bfin_jc_circ_write(buf, count);
|
||||
release_console_sem();
|
||||
console_unlock();
|
||||
wake_up_process(bfin_jc_kthread);
|
||||
return i;
|
||||
}
|
||||
|
@ -196,9 +196,9 @@ static void __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
|
||||
clkevt.clkevt.min_delta_ns = clockevent_delta2ns(1, &clkevt.clkevt) + 1;
|
||||
clkevt.clkevt.cpumask = cpumask_of(0);
|
||||
|
||||
setup_irq(irq, &tc_irqaction);
|
||||
|
||||
clockevents_register_device(&clkevt.clkevt);
|
||||
|
||||
setup_irq(irq, &tc_irqaction);
|
||||
}
|
||||
|
||||
#else /* !CONFIG_GENERIC_CLOCKEVENTS */
|
||||
|
@ -187,7 +187,7 @@ MODULE_DEVICE_TABLE(pci, lnw_gpio_ids);
|
||||
|
||||
static void lnw_irq_handler(unsigned irq, struct irq_desc *desc)
|
||||
{
|
||||
struct lnw_gpio *lnw = (struct lnw_gpio *)get_irq_data(irq);
|
||||
struct lnw_gpio *lnw = get_irq_data(irq);
|
||||
u32 base, gpio;
|
||||
void __iomem *gedr;
|
||||
u32 gedr_v;
|
||||
@ -206,7 +206,12 @@ static void lnw_irq_handler(unsigned irq, struct irq_desc *desc)
|
||||
/* clear the edge detect status bit */
|
||||
writel(gedr_v, gedr);
|
||||
}
|
||||
desc->chip->eoi(irq);
|
||||
|
||||
if (desc->chip->irq_eoi)
|
||||
desc->chip->irq_eoi(irq_get_irq_data(irq));
|
||||
else
|
||||
dev_warn(lnw->chip.dev, "missing EOI handler for irq %d\n", irq);
|
||||
|
||||
}
|
||||
|
||||
static int __devinit lnw_gpio_probe(struct pci_dev *pdev,
|
||||
|
@ -6310,6 +6310,9 @@ void merge_like_dcb_entries(struct drm_device *dev, struct dcb_table *dcb)
|
||||
static bool
|
||||
apply_dcb_encoder_quirks(struct drm_device *dev, int idx, u32 *conn, u32 *conf)
|
||||
{
|
||||
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
||||
struct dcb_table *dcb = &dev_priv->vbios.dcb;
|
||||
|
||||
/* Dell Precision M6300
|
||||
* DCB entry 2: 02025312 00000010
|
||||
* DCB entry 3: 02026312 00000020
|
||||
@ -6327,6 +6330,18 @@ apply_dcb_encoder_quirks(struct drm_device *dev, int idx, u32 *conn, u32 *conf)
|
||||
return false;
|
||||
}
|
||||
|
||||
/* GeForce3 Ti 200
|
||||
*
|
||||
* DCB reports an LVDS output that should be TMDS:
|
||||
* DCB entry 1: f2005014 ffffffff
|
||||
*/
|
||||
if (nv_match_device(dev, 0x0201, 0x1462, 0x8851)) {
|
||||
if (*conn == 0xf2005014 && *conf == 0xffffffff) {
|
||||
fabricate_dcb_output(dcb, OUTPUT_TMDS, 1, 1, 1);
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
@ -234,9 +234,9 @@ nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state)
|
||||
pci_set_power_state(pdev, PCI_D3hot);
|
||||
}
|
||||
|
||||
acquire_console_sem();
|
||||
console_lock();
|
||||
nouveau_fbcon_set_suspend(dev, 1);
|
||||
release_console_sem();
|
||||
console_unlock();
|
||||
nouveau_fbcon_restore_accel(dev);
|
||||
return 0;
|
||||
|
||||
@ -359,9 +359,9 @@ nouveau_pci_resume(struct pci_dev *pdev)
|
||||
nv_crtc->lut.depth = 0;
|
||||
}
|
||||
|
||||
acquire_console_sem();
|
||||
console_lock();
|
||||
nouveau_fbcon_set_suspend(dev, 0);
|
||||
release_console_sem();
|
||||
console_unlock();
|
||||
|
||||
nouveau_fbcon_zfill_all(dev);
|
||||
|
||||
|
@ -848,9 +848,6 @@ extern void nv10_mem_put_tile_region(struct drm_device *dev,
|
||||
struct nouveau_fence *fence);
|
||||
extern const struct ttm_mem_type_manager_func nouveau_vram_manager;
|
||||
|
||||
/* nvc0_vram.c */
|
||||
extern const struct ttm_mem_type_manager_func nvc0_vram_manager;
|
||||
|
||||
/* nouveau_notifier.c */
|
||||
extern int nouveau_notifier_init_channel(struct nouveau_channel *);
|
||||
extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
|
||||
|
@ -265,8 +265,8 @@ nouveau_temp_probe_i2c(struct drm_device *dev)
|
||||
struct i2c_board_info info[] = {
|
||||
{ I2C_BOARD_INFO("w83l785ts", 0x2d) },
|
||||
{ I2C_BOARD_INFO("w83781d", 0x2d) },
|
||||
{ I2C_BOARD_INFO("f75375", 0x2e) },
|
||||
{ I2C_BOARD_INFO("adt7473", 0x2e) },
|
||||
{ I2C_BOARD_INFO("f75375", 0x2e) },
|
||||
{ I2C_BOARD_INFO("lm99", 0x4c) },
|
||||
{ }
|
||||
};
|
||||
|
@ -256,6 +256,7 @@ nv50_graph_destroy_context(struct nouveau_channel *chan)
|
||||
struct drm_device *dev = chan->dev;
|
||||
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
||||
struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
|
||||
struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
|
||||
int i, hdr = (dev_priv->chipset == 0x50) ? 0x200 : 0x20;
|
||||
unsigned long flags;
|
||||
|
||||
@ -265,6 +266,7 @@ nv50_graph_destroy_context(struct nouveau_channel *chan)
|
||||
return;
|
||||
|
||||
spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
|
||||
pfifo->reassign(dev, false);
|
||||
pgraph->fifo_access(dev, false);
|
||||
|
||||
if (pgraph->channel(dev) == chan)
|
||||
@ -275,6 +277,7 @@ nv50_graph_destroy_context(struct nouveau_channel *chan)
|
||||
dev_priv->engine.instmem.flush(dev);
|
||||
|
||||
pgraph->fifo_access(dev, true);
|
||||
pfifo->reassign(dev, true);
|
||||
spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
|
||||
|
||||
nouveau_gpuobj_ref(NULL, &chan->ramin_grctx);
|
||||
|
@ -45,11 +45,6 @@ nv50_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde,
|
||||
}
|
||||
|
||||
if (phys & 1) {
|
||||
if (dev_priv->vram_sys_base) {
|
||||
phys += dev_priv->vram_sys_base;
|
||||
phys |= 0x30;
|
||||
}
|
||||
|
||||
if (coverage <= 32 * 1024 * 1024)
|
||||
phys |= 0x60;
|
||||
else if (coverage <= 64 * 1024 * 1024)
|
||||
|
@ -31,6 +31,7 @@
|
||||
#include "nvc0_graph.h"
|
||||
|
||||
static void nvc0_graph_isr(struct drm_device *);
|
||||
static void nvc0_runk140_isr(struct drm_device *);
|
||||
static int nvc0_graph_unload_context_to(struct drm_device *dev, u64 chan);
|
||||
|
||||
void
|
||||
@ -281,6 +282,7 @@ nvc0_graph_destroy(struct drm_device *dev)
|
||||
return;
|
||||
|
||||
nouveau_irq_unregister(dev, 12);
|
||||
nouveau_irq_unregister(dev, 25);
|
||||
|
||||
nouveau_gpuobj_ref(NULL, &priv->unk4188b8);
|
||||
nouveau_gpuobj_ref(NULL, &priv->unk4188b4);
|
||||
@ -390,6 +392,7 @@ nvc0_graph_create(struct drm_device *dev)
|
||||
}
|
||||
|
||||
nouveau_irq_register(dev, 12, nvc0_graph_isr);
|
||||
nouveau_irq_register(dev, 25, nvc0_runk140_isr);
|
||||
NVOBJ_CLASS(dev, 0x902d, GR); /* 2D */
|
||||
NVOBJ_CLASS(dev, 0x9039, GR); /* M2MF */
|
||||
NVOBJ_CLASS(dev, 0x9097, GR); /* 3D */
|
||||
@ -512,8 +515,8 @@ nvc0_graph_init_gpc_1(struct drm_device *dev)
|
||||
nv_wr32(dev, TP_UNIT(gpc, tp, 0x224), 0xc0000000);
|
||||
nv_wr32(dev, TP_UNIT(gpc, tp, 0x48c), 0xc0000000);
|
||||
nv_wr32(dev, TP_UNIT(gpc, tp, 0x084), 0xc0000000);
|
||||
nv_wr32(dev, TP_UNIT(gpc, tp, 0xe44), 0x001ffffe);
|
||||
nv_wr32(dev, TP_UNIT(gpc, tp, 0xe4c), 0x0000000f);
|
||||
nv_wr32(dev, TP_UNIT(gpc, tp, 0x644), 0x001ffffe);
|
||||
nv_wr32(dev, TP_UNIT(gpc, tp, 0x64c), 0x0000000f);
|
||||
}
|
||||
nv_wr32(dev, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
|
||||
nv_wr32(dev, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
|
||||
@ -777,3 +780,19 @@ nvc0_graph_isr(struct drm_device *dev)
|
||||
|
||||
nv_wr32(dev, 0x400500, 0x00010001);
|
||||
}
|
||||
|
||||
static void
|
||||
nvc0_runk140_isr(struct drm_device *dev)
|
||||
{
|
||||
u32 units = nv_rd32(dev, 0x00017c) & 0x1f;
|
||||
|
||||
while (units) {
|
||||
u32 unit = ffs(units) - 1;
|
||||
u32 reg = 0x140000 + unit * 0x2000;
|
||||
u32 st0 = nv_mask(dev, reg + 0x1020, 0, 0);
|
||||
u32 st1 = nv_mask(dev, reg + 0x1420, 0, 0);
|
||||
|
||||
NV_INFO(dev, "PRUNK140: %d 0x%08x 0x%08x\n", unit, st0, st1);
|
||||
units &= ~(1 << unit);
|
||||
}
|
||||
}
|
||||
|
@ -1830,7 +1830,7 @@ nvc0_grctx_generate(struct nouveau_channel *chan)
|
||||
|
||||
for (tp = 0, id = 0; tp < 4; tp++) {
|
||||
for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
|
||||
if (tp <= priv->tp_nr[gpc]) {
|
||||
if (tp < priv->tp_nr[gpc]) {
|
||||
nv_wr32(dev, TP_UNIT(gpc, tp, 0x698), id);
|
||||
nv_wr32(dev, TP_UNIT(gpc, tp, 0x4e8), id);
|
||||
nv_wr32(dev, GPC_UNIT(gpc, 0x0c10 + tp * 4), id);
|
||||
|
@ -994,6 +994,7 @@ static int evergreen_crtc_do_set_base(struct drm_crtc *crtc,
|
||||
struct radeon_bo *rbo;
|
||||
uint64_t fb_location;
|
||||
uint32_t fb_format, fb_pitch_pixels, tiling_flags;
|
||||
u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
|
||||
int r;
|
||||
|
||||
/* no fb bound */
|
||||
@ -1045,11 +1046,17 @@ static int evergreen_crtc_do_set_base(struct drm_crtc *crtc,
|
||||
case 16:
|
||||
fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
|
||||
EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
|
||||
#ifdef __BIG_ENDIAN
|
||||
fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
|
||||
#endif
|
||||
break;
|
||||
case 24:
|
||||
case 32:
|
||||
fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
|
||||
EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
|
||||
#ifdef __BIG_ENDIAN
|
||||
fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
|
||||
#endif
|
||||
break;
|
||||
default:
|
||||
DRM_ERROR("Unsupported screen depth %d\n",
|
||||
@ -1094,6 +1101,7 @@ static int evergreen_crtc_do_set_base(struct drm_crtc *crtc,
|
||||
WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
|
||||
(u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
|
||||
WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
|
||||
WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
|
||||
|
||||
WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
|
||||
WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
|
||||
@ -1150,6 +1158,7 @@ static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
|
||||
struct drm_framebuffer *target_fb;
|
||||
uint64_t fb_location;
|
||||
uint32_t fb_format, fb_pitch_pixels, tiling_flags;
|
||||
u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
|
||||
int r;
|
||||
|
||||
/* no fb bound */
|
||||
@ -1203,12 +1212,18 @@ static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
|
||||
fb_format =
|
||||
AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
|
||||
AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
|
||||
#ifdef __BIG_ENDIAN
|
||||
fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
|
||||
#endif
|
||||
break;
|
||||
case 24:
|
||||
case 32:
|
||||
fb_format =
|
||||
AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
|
||||
AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
|
||||
#ifdef __BIG_ENDIAN
|
||||
fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
|
||||
#endif
|
||||
break;
|
||||
default:
|
||||
DRM_ERROR("Unsupported screen depth %d\n",
|
||||
@ -1248,6 +1263,8 @@ static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
|
||||
WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
|
||||
radeon_crtc->crtc_offset, (u32) fb_location);
|
||||
WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
|
||||
if (rdev->family >= CHIP_R600)
|
||||
WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
|
||||
|
||||
WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
|
||||
WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
|
||||
|
@ -187,9 +187,9 @@ static int dp_link_clock_for_mode_clock(u8 dpcd[DP_DPCD_SIZE], int mode_clock)
|
||||
int dp_mode_valid(u8 dpcd[DP_DPCD_SIZE], int mode_clock)
|
||||
{
|
||||
int lanes = dp_lanes_for_mode_clock(dpcd, mode_clock);
|
||||
int bw = dp_lanes_for_mode_clock(dpcd, mode_clock);
|
||||
int dp_clock = dp_link_clock_for_mode_clock(dpcd, mode_clock);
|
||||
|
||||
if ((lanes == 0) || (bw == 0))
|
||||
if ((lanes == 0) || (dp_clock == 0))
|
||||
return MODE_CLOCK_HIGH;
|
||||
|
||||
return MODE_OK;
|
||||
|
@ -232,7 +232,7 @@ draw_auto(struct radeon_device *rdev)
|
||||
|
||||
}
|
||||
|
||||
/* emits 30 */
|
||||
/* emits 34 */
|
||||
static void
|
||||
set_default_state(struct radeon_device *rdev)
|
||||
{
|
||||
@ -245,6 +245,8 @@ set_default_state(struct radeon_device *rdev)
|
||||
int num_hs_threads, num_ls_threads;
|
||||
int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
|
||||
int num_hs_stack_entries, num_ls_stack_entries;
|
||||
u64 gpu_addr;
|
||||
int dwords;
|
||||
|
||||
switch (rdev->family) {
|
||||
case CHIP_CEDAR:
|
||||
@ -497,6 +499,14 @@ set_default_state(struct radeon_device *rdev)
|
||||
radeon_ring_write(rdev, 0x00000000);
|
||||
radeon_ring_write(rdev, 0x00000000);
|
||||
|
||||
/* emit an IB pointing at default state */
|
||||
dwords = ALIGN(rdev->r600_blit.state_len, 0x10);
|
||||
gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
|
||||
radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
|
||||
radeon_ring_write(rdev, gpu_addr & 0xFFFFFFFC);
|
||||
radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF);
|
||||
radeon_ring_write(rdev, dwords);
|
||||
|
||||
}
|
||||
|
||||
static inline uint32_t i2f(uint32_t input)
|
||||
@ -527,8 +537,10 @@ static inline uint32_t i2f(uint32_t input)
|
||||
int evergreen_blit_init(struct radeon_device *rdev)
|
||||
{
|
||||
u32 obj_size;
|
||||
int r;
|
||||
int r, dwords;
|
||||
void *ptr;
|
||||
u32 packet2s[16];
|
||||
int num_packet2s = 0;
|
||||
|
||||
/* pin copy shader into vram if already initialized */
|
||||
if (rdev->r600_blit.shader_obj)
|
||||
@ -536,8 +548,17 @@ int evergreen_blit_init(struct radeon_device *rdev)
|
||||
|
||||
mutex_init(&rdev->r600_blit.mutex);
|
||||
rdev->r600_blit.state_offset = 0;
|
||||
rdev->r600_blit.state_len = 0;
|
||||
obj_size = 0;
|
||||
|
||||
rdev->r600_blit.state_len = evergreen_default_size;
|
||||
|
||||
dwords = rdev->r600_blit.state_len;
|
||||
while (dwords & 0xf) {
|
||||
packet2s[num_packet2s++] = PACKET2(0);
|
||||
dwords++;
|
||||
}
|
||||
|
||||
obj_size = dwords * 4;
|
||||
obj_size = ALIGN(obj_size, 256);
|
||||
|
||||
rdev->r600_blit.vs_offset = obj_size;
|
||||
obj_size += evergreen_vs_size * 4;
|
||||
@ -567,6 +588,12 @@ int evergreen_blit_init(struct radeon_device *rdev)
|
||||
return r;
|
||||
}
|
||||
|
||||
memcpy_toio(ptr + rdev->r600_blit.state_offset,
|
||||
evergreen_default_state, rdev->r600_blit.state_len * 4);
|
||||
|
||||
if (num_packet2s)
|
||||
memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
|
||||
packet2s, num_packet2s * 4);
|
||||
memcpy(ptr + rdev->r600_blit.vs_offset, evergreen_vs, evergreen_vs_size * 4);
|
||||
memcpy(ptr + rdev->r600_blit.ps_offset, evergreen_ps, evergreen_ps_size * 4);
|
||||
radeon_bo_kunmap(rdev->r600_blit.shader_obj);
|
||||
@ -652,7 +679,7 @@ int evergreen_blit_prepare_copy(struct radeon_device *rdev, int size_bytes)
|
||||
/* calculate number of loops correctly */
|
||||
ring_size = num_loops * dwords_per_loop;
|
||||
/* set default + shaders */
|
||||
ring_size += 46; /* shaders + def state */
|
||||
ring_size += 50; /* shaders + def state */
|
||||
ring_size += 10; /* fence emit for VB IB */
|
||||
ring_size += 5; /* done copy */
|
||||
ring_size += 10; /* fence emit for done copy */
|
||||
@ -660,7 +687,7 @@ int evergreen_blit_prepare_copy(struct radeon_device *rdev, int size_bytes)
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
set_default_state(rdev); /* 30 */
|
||||
set_default_state(rdev); /* 34 */
|
||||
set_shaders(rdev); /* 16 */
|
||||
return 0;
|
||||
}
|
||||
|
@ -1031,8 +1031,8 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
|
||||
WREG32(RADEON_CP_CSQ_MODE,
|
||||
REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
|
||||
REG_SET(RADEON_INDIRECT1_START, indirect1_start));
|
||||
WREG32(0x718, 0);
|
||||
WREG32(0x744, 0x00004D4D);
|
||||
WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
|
||||
WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
|
||||
WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
|
||||
radeon_ring_start(rdev);
|
||||
r = radeon_ring_test(rdev);
|
||||
@ -2347,10 +2347,10 @@ void r100_vga_set_state(struct radeon_device *rdev, bool state)
|
||||
|
||||
temp = RREG32(RADEON_CONFIG_CNTL);
|
||||
if (state == false) {
|
||||
temp &= ~(1<<8);
|
||||
temp |= (1<<9);
|
||||
temp &= ~RADEON_CFG_VGA_RAM_EN;
|
||||
temp |= RADEON_CFG_VGA_IO_DIS;
|
||||
} else {
|
||||
temp &= ~(1<<9);
|
||||
temp &= ~RADEON_CFG_VGA_IO_DIS;
|
||||
}
|
||||
WREG32(RADEON_CONFIG_CNTL, temp);
|
||||
}
|
||||
|
@ -69,6 +69,9 @@ void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
|
||||
mb();
|
||||
}
|
||||
|
||||
#define R300_PTE_WRITEABLE (1 << 2)
|
||||
#define R300_PTE_READABLE (1 << 3)
|
||||
|
||||
int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
|
||||
{
|
||||
void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
|
||||
@ -78,7 +81,7 @@ int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
|
||||
}
|
||||
addr = (lower_32_bits(addr) >> 8) |
|
||||
((upper_32_bits(addr) & 0xff) << 24) |
|
||||
0xc;
|
||||
R300_PTE_WRITEABLE | R300_PTE_READABLE;
|
||||
/* on x86 we want this to be CPU endian, on powerpc
|
||||
* on powerpc without HW swappers, it'll get swapped on way
|
||||
* into VRAM - so no need for cpu_to_le32 on VRAM tables */
|
||||
@ -135,7 +138,7 @@ int rv370_pcie_gart_enable(struct radeon_device *rdev)
|
||||
WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start);
|
||||
WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
|
||||
/* Clear error */
|
||||
WREG32_PCIE(0x18, 0);
|
||||
WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0);
|
||||
tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
|
||||
tmp |= RADEON_PCIE_TX_GART_EN;
|
||||
tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
|
||||
|
@ -96,7 +96,7 @@ void r420_pipes_init(struct radeon_device *rdev)
|
||||
"programming pipes. Bad things might happen.\n");
|
||||
}
|
||||
/* get max number of pipes */
|
||||
gb_pipe_select = RREG32(0x402C);
|
||||
gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
|
||||
num_pipes = ((gb_pipe_select >> 12) & 3) + 1;
|
||||
|
||||
/* SE chips have 1 pipe */
|
||||
|
@ -79,8 +79,8 @@ static void r520_gpu_init(struct radeon_device *rdev)
|
||||
WREG32(0x4128, 0xFF);
|
||||
}
|
||||
r420_pipes_init(rdev);
|
||||
gb_pipe_select = RREG32(0x402C);
|
||||
tmp = RREG32(0x170C);
|
||||
gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
|
||||
tmp = RREG32(R300_DST_PIPE_CONFIG);
|
||||
pipe_select_current = (tmp >> 2) & 3;
|
||||
tmp = (1 << pipe_select_current) |
|
||||
(((gb_pipe_select >> 8) & 0xF) << 4);
|
||||
|
@ -81,7 +81,11 @@
|
||||
#define R600_MEDIUM_VID_LOWER_GPIO_CNTL 0x720
|
||||
#define R600_LOW_VID_LOWER_GPIO_CNTL 0x724
|
||||
|
||||
|
||||
#define R600_D1GRPH_SWAP_CONTROL 0x610C
|
||||
# define R600_D1GRPH_SWAP_ENDIAN_NONE (0 << 0)
|
||||
# define R600_D1GRPH_SWAP_ENDIAN_16BIT (1 << 0)
|
||||
# define R600_D1GRPH_SWAP_ENDIAN_32BIT (2 << 0)
|
||||
# define R600_D1GRPH_SWAP_ENDIAN_64BIT (3 << 0)
|
||||
|
||||
#define R600_HDP_NONSURFACE_BASE 0x2c04
|
||||
|
||||
|
@ -891,9 +891,9 @@ int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
|
||||
pci_disable_device(dev->pdev);
|
||||
pci_set_power_state(dev->pdev, PCI_D3hot);
|
||||
}
|
||||
acquire_console_sem();
|
||||
console_lock();
|
||||
radeon_fbdev_set_suspend(rdev, 1);
|
||||
release_console_sem();
|
||||
console_unlock();
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -905,11 +905,11 @@ int radeon_resume_kms(struct drm_device *dev)
|
||||
if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
|
||||
return 0;
|
||||
|
||||
acquire_console_sem();
|
||||
console_lock();
|
||||
pci_set_power_state(dev->pdev, PCI_D0);
|
||||
pci_restore_state(dev->pdev);
|
||||
if (pci_enable_device(dev->pdev)) {
|
||||
release_console_sem();
|
||||
console_unlock();
|
||||
return -1;
|
||||
}
|
||||
pci_set_master(dev->pdev);
|
||||
@ -920,7 +920,7 @@ int radeon_resume_kms(struct drm_device *dev)
|
||||
radeon_restore_bios_scratch_regs(rdev);
|
||||
|
||||
radeon_fbdev_set_suspend(rdev, 0);
|
||||
release_console_sem();
|
||||
console_unlock();
|
||||
|
||||
/* reset hpd state */
|
||||
radeon_hpd_init(rdev);
|
||||
|
@ -641,7 +641,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
|
||||
switch (connector->connector_type) {
|
||||
case DRM_MODE_CONNECTOR_DVII:
|
||||
case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
|
||||
if (drm_detect_monitor_audio(radeon_connector->edid)) {
|
||||
if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
|
||||
/* fix me */
|
||||
if (ASIC_IS_DCE4(rdev))
|
||||
return ATOM_ENCODER_MODE_DVI;
|
||||
@ -655,7 +655,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
|
||||
case DRM_MODE_CONNECTOR_DVID:
|
||||
case DRM_MODE_CONNECTOR_HDMIA:
|
||||
default:
|
||||
if (drm_detect_monitor_audio(radeon_connector->edid)) {
|
||||
if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
|
||||
/* fix me */
|
||||
if (ASIC_IS_DCE4(rdev))
|
||||
return ATOM_ENCODER_MODE_DVI;
|
||||
@ -673,7 +673,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
|
||||
if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
|
||||
(dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
|
||||
return ATOM_ENCODER_MODE_DP;
|
||||
else if (drm_detect_monitor_audio(radeon_connector->edid)) {
|
||||
else if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
|
||||
/* fix me */
|
||||
if (ASIC_IS_DCE4(rdev))
|
||||
return ATOM_ENCODER_MODE_DVI;
|
||||
|
@ -247,6 +247,8 @@ void radeon_driver_preclose_kms(struct drm_device *dev,
|
||||
struct radeon_device *rdev = dev->dev_private;
|
||||
if (rdev->hyperz_filp == file_priv)
|
||||
rdev->hyperz_filp = NULL;
|
||||
if (rdev->cmask_filp == file_priv)
|
||||
rdev->cmask_filp = NULL;
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -375,6 +375,8 @@
|
||||
#define RADEON_CONFIG_APER_SIZE 0x0108
|
||||
#define RADEON_CONFIG_BONDS 0x00e8
|
||||
#define RADEON_CONFIG_CNTL 0x00e0
|
||||
# define RADEON_CFG_VGA_RAM_EN (1 << 8)
|
||||
# define RADEON_CFG_VGA_IO_DIS (1 << 9)
|
||||
# define RADEON_CFG_ATI_REV_A11 (0 << 16)
|
||||
# define RADEON_CFG_ATI_REV_A12 (1 << 16)
|
||||
# define RADEON_CFG_ATI_REV_A13 (2 << 16)
|
||||
|
@ -203,6 +203,9 @@ void rs400_gart_fini(struct radeon_device *rdev)
|
||||
radeon_gart_table_ram_free(rdev);
|
||||
}
|
||||
|
||||
#define RS400_PTE_WRITEABLE (1 << 2)
|
||||
#define RS400_PTE_READABLE (1 << 3)
|
||||
|
||||
int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
|
||||
{
|
||||
uint32_t entry;
|
||||
@ -213,7 +216,7 @@ int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
|
||||
|
||||
entry = (lower_32_bits(addr) & PAGE_MASK) |
|
||||
((upper_32_bits(addr) & 0xff) << 4) |
|
||||
0xc;
|
||||
RS400_PTE_WRITEABLE | RS400_PTE_READABLE;
|
||||
entry = cpu_to_le32(entry);
|
||||
rdev->gart.table.ram.ptr[i] = entry;
|
||||
return 0;
|
||||
@ -226,8 +229,8 @@ int rs400_mc_wait_for_idle(struct radeon_device *rdev)
|
||||
|
||||
for (i = 0; i < rdev->usec_timeout; i++) {
|
||||
/* read MC_STATUS */
|
||||
tmp = RREG32(0x0150);
|
||||
if (tmp & (1 << 2)) {
|
||||
tmp = RREG32(RADEON_MC_STATUS);
|
||||
if (tmp & RADEON_MC_IDLE) {
|
||||
return 0;
|
||||
}
|
||||
DRM_UDELAY(1);
|
||||
@ -241,7 +244,7 @@ void rs400_gpu_init(struct radeon_device *rdev)
|
||||
r420_pipes_init(rdev);
|
||||
if (rs400_mc_wait_for_idle(rdev)) {
|
||||
printk(KERN_WARNING "rs400: Failed to wait MC idle while "
|
||||
"programming pipes. Bad things might happen. %08x\n", RREG32(0x150));
|
||||
"programming pipes. Bad things might happen. %08x\n", RREG32(RADEON_MC_STATUS));
|
||||
}
|
||||
}
|
||||
|
||||
@ -300,9 +303,9 @@ static int rs400_debugfs_gart_info(struct seq_file *m, void *data)
|
||||
seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp);
|
||||
tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION);
|
||||
seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp);
|
||||
tmp = RREG32_MC(0x100);
|
||||
tmp = RREG32_MC(RS690_MCCFG_FB_LOCATION);
|
||||
seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp);
|
||||
tmp = RREG32(0x134);
|
||||
tmp = RREG32(RS690_HDP_FB_LOCATION);
|
||||
seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp);
|
||||
} else {
|
||||
tmp = RREG32(RADEON_AGP_BASE);
|
||||
|
@ -69,13 +69,13 @@ void rv515_ring_start(struct radeon_device *rdev)
|
||||
ISYNC_CPSCRATCH_IDLEGUI);
|
||||
radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0));
|
||||
radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
|
||||
radeon_ring_write(rdev, PACKET0(0x170C, 0));
|
||||
radeon_ring_write(rdev, 1 << 31);
|
||||
radeon_ring_write(rdev, PACKET0(R300_DST_PIPE_CONFIG, 0));
|
||||
radeon_ring_write(rdev, R300_PIPE_AUTO_CONFIG);
|
||||
radeon_ring_write(rdev, PACKET0(GB_SELECT, 0));
|
||||
radeon_ring_write(rdev, 0);
|
||||
radeon_ring_write(rdev, PACKET0(GB_ENABLE, 0));
|
||||
radeon_ring_write(rdev, 0);
|
||||
radeon_ring_write(rdev, PACKET0(0x42C8, 0));
|
||||
radeon_ring_write(rdev, PACKET0(R500_SU_REG_DEST, 0));
|
||||
radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1);
|
||||
radeon_ring_write(rdev, PACKET0(VAP_INDEX_OFFSET, 0));
|
||||
radeon_ring_write(rdev, 0);
|
||||
@ -153,8 +153,8 @@ void rv515_gpu_init(struct radeon_device *rdev)
|
||||
}
|
||||
rv515_vga_render_disable(rdev);
|
||||
r420_pipes_init(rdev);
|
||||
gb_pipe_select = RREG32(0x402C);
|
||||
tmp = RREG32(0x170C);
|
||||
gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
|
||||
tmp = RREG32(R300_DST_PIPE_CONFIG);
|
||||
pipe_select_current = (tmp >> 2) & 3;
|
||||
tmp = (1 << pipe_select_current) |
|
||||
(((gb_pipe_select >> 8) & 0xF) << 4);
|
||||
|
@ -1072,6 +1072,7 @@ static int applesmc_create_nodes(struct applesmc_node_group *groups, int num)
|
||||
node->sda.dev_attr.show = grp->show;
|
||||
node->sda.dev_attr.store = grp->store;
|
||||
attr = &node->sda.dev_attr.attr;
|
||||
sysfs_attr_init(attr);
|
||||
attr->name = node->name;
|
||||
attr->mode = S_IRUGO | (grp->store ? S_IWUSR : 0);
|
||||
ret = sysfs_create_file(&pdev->dev.kobj, attr);
|
||||
|
@ -13,6 +13,7 @@
|
||||
#include <linux/list.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/dmi.h>
|
||||
|
||||
#include <acpi/acpi.h>
|
||||
#include <acpi/acpixf.h>
|
||||
@ -22,6 +23,21 @@
|
||||
|
||||
#define ATK_HID "ATK0110"
|
||||
|
||||
static bool new_if;
|
||||
module_param(new_if, bool, 0);
|
||||
MODULE_PARM_DESC(new_if, "Override detection heuristic and force the use of the new ATK0110 interface");
|
||||
|
||||
static const struct dmi_system_id __initconst atk_force_new_if[] = {
|
||||
{
|
||||
/* Old interface has broken MCH temp monitoring */
|
||||
.ident = "Asus Sabertooth X58",
|
||||
.matches = {
|
||||
DMI_MATCH(DMI_BOARD_NAME, "SABERTOOTH X58")
|
||||
}
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* Minimum time between readings, enforced in order to avoid
|
||||
* hogging the CPU.
|
||||
*/
|
||||
@ -1302,7 +1318,9 @@ static int atk_probe_if(struct atk_data *data)
|
||||
* analysis of multiple DSDTs indicates that when both interfaces
|
||||
* are present the new one (GGRP/GITM) is not functional.
|
||||
*/
|
||||
if (data->rtmp_handle && data->rvlt_handle && data->rfan_handle)
|
||||
if (new_if)
|
||||
dev_info(dev, "Overriding interface detection\n");
|
||||
if (data->rtmp_handle && data->rvlt_handle && data->rfan_handle && !new_if)
|
||||
data->old_interface = true;
|
||||
else if (data->enumerate_handle && data->read_handle &&
|
||||
data->write_handle)
|
||||
@ -1420,6 +1438,9 @@ static int __init atk0110_init(void)
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
if (dmi_check_system(atk_force_new_if))
|
||||
new_if = true;
|
||||
|
||||
ret = acpi_bus_register_driver(&atk_driver);
|
||||
if (ret)
|
||||
pr_info("acpi_bus_register_driver failed: %d\n", ret);
|
||||
|
@ -957,7 +957,7 @@ int lis3lv02d_init_device(struct lis3lv02d *dev)
|
||||
|
||||
/* bail if we did not get an IRQ from the bus layer */
|
||||
if (!dev->irq) {
|
||||
pr_err("No IRQ. Disabling /dev/freefall\n");
|
||||
pr_debug("No IRQ. Disabling /dev/freefall\n");
|
||||
goto out;
|
||||
}
|
||||
|
||||
|
@ -343,6 +343,16 @@ config KEYBOARD_NOMADIK
|
||||
To compile this driver as a module, choose M here: the
|
||||
module will be called nmk-ske-keypad.
|
||||
|
||||
config KEYBOARD_TEGRA
|
||||
tristate "NVIDIA Tegra internal matrix keyboard controller support"
|
||||
depends on ARCH_TEGRA
|
||||
help
|
||||
Say Y here if you want to use a matrix keyboard connected directly
|
||||
to the internal keyboard controller on Tegra SoCs.
|
||||
|
||||
To compile this driver as a module, choose M here: the
|
||||
module will be called tegra-kbc.
|
||||
|
||||
config KEYBOARD_OPENCORES
|
||||
tristate "OpenCores Keyboard Controller"
|
||||
help
|
||||
|
@ -42,6 +42,7 @@ obj-$(CONFIG_KEYBOARD_STMPE) += stmpe-keypad.o
|
||||
obj-$(CONFIG_KEYBOARD_STOWAWAY) += stowaway.o
|
||||
obj-$(CONFIG_KEYBOARD_SUNKBD) += sunkbd.o
|
||||
obj-$(CONFIG_KEYBOARD_TC3589X) += tc3589x-keypad.o
|
||||
obj-$(CONFIG_KEYBOARD_TEGRA) += tegra-kbc.o
|
||||
obj-$(CONFIG_KEYBOARD_TNETV107X) += tnetv107x-keypad.o
|
||||
obj-$(CONFIG_KEYBOARD_TWL4030) += twl4030_keypad.o
|
||||
obj-$(CONFIG_KEYBOARD_XTKBD) += xtkbd.o
|
||||
|
@ -322,7 +322,7 @@ static void gpio_keys_report_event(struct gpio_button_data *bdata)
|
||||
struct gpio_keys_button *button = bdata->button;
|
||||
struct input_dev *input = bdata->input;
|
||||
unsigned int type = button->type ?: EV_KEY;
|
||||
int state = (gpio_get_value(button->gpio) ? 1 : 0) ^ button->active_low;
|
||||
int state = (gpio_get_value_cansleep(button->gpio) ? 1 : 0) ^ button->active_low;
|
||||
|
||||
input_event(input, type, button->code, !!state);
|
||||
input_sync(input);
|
||||
@ -410,8 +410,8 @@ static int __devinit gpio_keys_setup_key(struct platform_device *pdev,
|
||||
if (!button->can_disable)
|
||||
irqflags |= IRQF_SHARED;
|
||||
|
||||
error = request_irq(irq, gpio_keys_isr, irqflags, desc, bdata);
|
||||
if (error) {
|
||||
error = request_any_context_irq(irq, gpio_keys_isr, irqflags, desc, bdata);
|
||||
if (error < 0) {
|
||||
dev_err(dev, "Unable to claim irq %d; error %d\n",
|
||||
irq, error);
|
||||
goto fail3;
|
||||
|
727
drivers/input/keyboard/tegra-kbc.c
Normal file
727
drivers/input/keyboard/tegra-kbc.c
Normal file
@ -0,0 +1,727 @@
|
||||
/*
|
||||
* Keyboard class input driver for the NVIDIA Tegra SoC internal matrix
|
||||
* keyboard controller
|
||||
*
|
||||
* Copyright (c) 2009-2011, NVIDIA Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/input.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/slab.h>
|
||||
#include <mach/clk.h>
|
||||
#include <mach/kbc.h>
|
||||
|
||||
#define KBC_MAX_DEBOUNCE_CNT 0x3ffu
|
||||
|
||||
/* KBC row scan time and delay for beginning the row scan. */
|
||||
#define KBC_ROW_SCAN_TIME 16
|
||||
#define KBC_ROW_SCAN_DLY 5
|
||||
|
||||
/* KBC uses a 32KHz clock so a cycle = 1/32Khz */
|
||||
#define KBC_CYCLE_USEC 32
|
||||
|
||||
/* KBC Registers */
|
||||
|
||||
/* KBC Control Register */
|
||||
#define KBC_CONTROL_0 0x0
|
||||
#define KBC_FIFO_TH_CNT_SHIFT(cnt) (cnt << 14)
|
||||
#define KBC_DEBOUNCE_CNT_SHIFT(cnt) (cnt << 4)
|
||||
#define KBC_CONTROL_FIFO_CNT_INT_EN (1 << 3)
|
||||
#define KBC_CONTROL_KBC_EN (1 << 0)
|
||||
|
||||
/* KBC Interrupt Register */
|
||||
#define KBC_INT_0 0x4
|
||||
#define KBC_INT_FIFO_CNT_INT_STATUS (1 << 2)
|
||||
|
||||
#define KBC_ROW_CFG0_0 0x8
|
||||
#define KBC_COL_CFG0_0 0x18
|
||||
#define KBC_INIT_DLY_0 0x28
|
||||
#define KBC_RPT_DLY_0 0x2c
|
||||
#define KBC_KP_ENT0_0 0x30
|
||||
#define KBC_KP_ENT1_0 0x34
|
||||
#define KBC_ROW0_MASK_0 0x38
|
||||
|
||||
#define KBC_ROW_SHIFT 3
|
||||
|
||||
struct tegra_kbc {
|
||||
void __iomem *mmio;
|
||||
struct input_dev *idev;
|
||||
unsigned int irq;
|
||||
unsigned int wake_enable_rows;
|
||||
unsigned int wake_enable_cols;
|
||||
spinlock_t lock;
|
||||
unsigned int repoll_dly;
|
||||
unsigned long cp_dly_jiffies;
|
||||
const struct tegra_kbc_platform_data *pdata;
|
||||
unsigned short keycode[KBC_MAX_KEY];
|
||||
unsigned short current_keys[KBC_MAX_KPENT];
|
||||
unsigned int num_pressed_keys;
|
||||
struct timer_list timer;
|
||||
struct clk *clk;
|
||||
};
|
||||
|
||||
static const u32 tegra_kbc_default_keymap[] = {
|
||||
KEY(0, 2, KEY_W),
|
||||
KEY(0, 3, KEY_S),
|
||||
KEY(0, 4, KEY_A),
|
||||
KEY(0, 5, KEY_Z),
|
||||
KEY(0, 7, KEY_FN),
|
||||
|
||||
KEY(1, 7, KEY_LEFTMETA),
|
||||
|
||||
KEY(2, 6, KEY_RIGHTALT),
|
||||
KEY(2, 7, KEY_LEFTALT),
|
||||
|
||||
KEY(3, 0, KEY_5),
|
||||
KEY(3, 1, KEY_4),
|
||||
KEY(3, 2, KEY_R),
|
||||
KEY(3, 3, KEY_E),
|
||||
KEY(3, 4, KEY_F),
|
||||
KEY(3, 5, KEY_D),
|
||||
KEY(3, 6, KEY_X),
|
||||
|
||||
KEY(4, 0, KEY_7),
|
||||
KEY(4, 1, KEY_6),
|
||||
KEY(4, 2, KEY_T),
|
||||
KEY(4, 3, KEY_H),
|
||||
KEY(4, 4, KEY_G),
|
||||
KEY(4, 5, KEY_V),
|
||||
KEY(4, 6, KEY_C),
|
||||
KEY(4, 7, KEY_SPACE),
|
||||
|
||||
KEY(5, 0, KEY_9),
|
||||
KEY(5, 1, KEY_8),
|
||||
KEY(5, 2, KEY_U),
|
||||
KEY(5, 3, KEY_Y),
|
||||
KEY(5, 4, KEY_J),
|
||||
KEY(5, 5, KEY_N),
|
||||
KEY(5, 6, KEY_B),
|
||||
KEY(5, 7, KEY_BACKSLASH),
|
||||
|
||||
KEY(6, 0, KEY_MINUS),
|
||||
KEY(6, 1, KEY_0),
|
||||
KEY(6, 2, KEY_O),
|
||||
KEY(6, 3, KEY_I),
|
||||
KEY(6, 4, KEY_L),
|
||||
KEY(6, 5, KEY_K),
|
||||
KEY(6, 6, KEY_COMMA),
|
||||
KEY(6, 7, KEY_M),
|
||||
|
||||
KEY(7, 1, KEY_EQUAL),
|
||||
KEY(7, 2, KEY_RIGHTBRACE),
|
||||
KEY(7, 3, KEY_ENTER),
|
||||
KEY(7, 7, KEY_MENU),
|
||||
|
||||
KEY(8, 4, KEY_RIGHTSHIFT),
|
||||
KEY(8, 5, KEY_LEFTSHIFT),
|
||||
|
||||
KEY(9, 5, KEY_RIGHTCTRL),
|
||||
KEY(9, 7, KEY_LEFTCTRL),
|
||||
|
||||
KEY(11, 0, KEY_LEFTBRACE),
|
||||
KEY(11, 1, KEY_P),
|
||||
KEY(11, 2, KEY_APOSTROPHE),
|
||||
KEY(11, 3, KEY_SEMICOLON),
|
||||
KEY(11, 4, KEY_SLASH),
|
||||
KEY(11, 5, KEY_DOT),
|
||||
|
||||
KEY(12, 0, KEY_F10),
|
||||
KEY(12, 1, KEY_F9),
|
||||
KEY(12, 2, KEY_BACKSPACE),
|
||||
KEY(12, 3, KEY_3),
|
||||
KEY(12, 4, KEY_2),
|
||||
KEY(12, 5, KEY_UP),
|
||||
KEY(12, 6, KEY_PRINT),
|
||||
KEY(12, 7, KEY_PAUSE),
|
||||
|
||||
KEY(13, 0, KEY_INSERT),
|
||||
KEY(13, 1, KEY_DELETE),
|
||||
KEY(13, 3, KEY_PAGEUP),
|
||||
KEY(13, 4, KEY_PAGEDOWN),
|
||||
KEY(13, 5, KEY_RIGHT),
|
||||
KEY(13, 6, KEY_DOWN),
|
||||
KEY(13, 7, KEY_LEFT),
|
||||
|
||||
KEY(14, 0, KEY_F11),
|
||||
KEY(14, 1, KEY_F12),
|
||||
KEY(14, 2, KEY_F8),
|
||||
KEY(14, 3, KEY_Q),
|
||||
KEY(14, 4, KEY_F4),
|
||||
KEY(14, 5, KEY_F3),
|
||||
KEY(14, 6, KEY_1),
|
||||
KEY(14, 7, KEY_F7),
|
||||
|
||||
KEY(15, 0, KEY_ESC),
|
||||
KEY(15, 1, KEY_GRAVE),
|
||||
KEY(15, 2, KEY_F5),
|
||||
KEY(15, 3, KEY_TAB),
|
||||
KEY(15, 4, KEY_F1),
|
||||
KEY(15, 5, KEY_F2),
|
||||
KEY(15, 6, KEY_CAPSLOCK),
|
||||
KEY(15, 7, KEY_F6),
|
||||
};
|
||||
|
||||
static const struct matrix_keymap_data tegra_kbc_default_keymap_data = {
|
||||
.keymap = tegra_kbc_default_keymap,
|
||||
.keymap_size = ARRAY_SIZE(tegra_kbc_default_keymap),
|
||||
};
|
||||
|
||||
static void tegra_kbc_report_released_keys(struct input_dev *input,
|
||||
unsigned short old_keycodes[],
|
||||
unsigned int old_num_keys,
|
||||
unsigned short new_keycodes[],
|
||||
unsigned int new_num_keys)
|
||||
{
|
||||
unsigned int i, j;
|
||||
|
||||
for (i = 0; i < old_num_keys; i++) {
|
||||
for (j = 0; j < new_num_keys; j++)
|
||||
if (old_keycodes[i] == new_keycodes[j])
|
||||
break;
|
||||
|
||||
if (j == new_num_keys)
|
||||
input_report_key(input, old_keycodes[i], 0);
|
||||
}
|
||||
}
|
||||
|
||||
static void tegra_kbc_report_pressed_keys(struct input_dev *input,
|
||||
unsigned char scancodes[],
|
||||
unsigned short keycodes[],
|
||||
unsigned int num_pressed_keys)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < num_pressed_keys; i++) {
|
||||
input_event(input, EV_MSC, MSC_SCAN, scancodes[i]);
|
||||
input_report_key(input, keycodes[i], 1);
|
||||
}
|
||||
}
|
||||
|
||||
static void tegra_kbc_report_keys(struct tegra_kbc *kbc)
|
||||
{
|
||||
unsigned char scancodes[KBC_MAX_KPENT];
|
||||
unsigned short keycodes[KBC_MAX_KPENT];
|
||||
u32 val = 0;
|
||||
unsigned int i;
|
||||
unsigned int num_down = 0;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&kbc->lock, flags);
|
||||
for (i = 0; i < KBC_MAX_KPENT; i++) {
|
||||
if ((i % 4) == 0)
|
||||
val = readl(kbc->mmio + KBC_KP_ENT0_0 + i);
|
||||
|
||||
if (val & 0x80) {
|
||||
unsigned int col = val & 0x07;
|
||||
unsigned int row = (val >> 3) & 0x0f;
|
||||
unsigned char scancode =
|
||||
MATRIX_SCAN_CODE(row, col, KBC_ROW_SHIFT);
|
||||
|
||||
scancodes[num_down] = scancode;
|
||||
keycodes[num_down++] = kbc->keycode[scancode];
|
||||
}
|
||||
|
||||
val >>= 8;
|
||||
}
|
||||
spin_unlock_irqrestore(&kbc->lock, flags);
|
||||
|
||||
tegra_kbc_report_released_keys(kbc->idev,
|
||||
kbc->current_keys, kbc->num_pressed_keys,
|
||||
keycodes, num_down);
|
||||
tegra_kbc_report_pressed_keys(kbc->idev, scancodes, keycodes, num_down);
|
||||
input_sync(kbc->idev);
|
||||
|
||||
memcpy(kbc->current_keys, keycodes, sizeof(kbc->current_keys));
|
||||
kbc->num_pressed_keys = num_down;
|
||||
}
|
||||
|
||||
static void tegra_kbc_keypress_timer(unsigned long data)
|
||||
{
|
||||
struct tegra_kbc *kbc = (struct tegra_kbc *)data;
|
||||
unsigned long flags;
|
||||
u32 val;
|
||||
unsigned int i;
|
||||
|
||||
val = (readl(kbc->mmio + KBC_INT_0) >> 4) & 0xf;
|
||||
if (val) {
|
||||
unsigned long dly;
|
||||
|
||||
tegra_kbc_report_keys(kbc);
|
||||
|
||||
/*
|
||||
* If more than one keys are pressed we need not wait
|
||||
* for the repoll delay.
|
||||
*/
|
||||
dly = (val == 1) ? kbc->repoll_dly : 1;
|
||||
mod_timer(&kbc->timer, jiffies + msecs_to_jiffies(dly));
|
||||
} else {
|
||||
/* Release any pressed keys and exit the polling loop */
|
||||
for (i = 0; i < kbc->num_pressed_keys; i++)
|
||||
input_report_key(kbc->idev, kbc->current_keys[i], 0);
|
||||
input_sync(kbc->idev);
|
||||
|
||||
kbc->num_pressed_keys = 0;
|
||||
|
||||
/* All keys are released so enable the keypress interrupt */
|
||||
spin_lock_irqsave(&kbc->lock, flags);
|
||||
val = readl(kbc->mmio + KBC_CONTROL_0);
|
||||
val |= KBC_CONTROL_FIFO_CNT_INT_EN;
|
||||
writel(val, kbc->mmio + KBC_CONTROL_0);
|
||||
spin_unlock_irqrestore(&kbc->lock, flags);
|
||||
}
|
||||
}
|
||||
|
||||
static irqreturn_t tegra_kbc_isr(int irq, void *args)
|
||||
{
|
||||
struct tegra_kbc *kbc = args;
|
||||
u32 val, ctl;
|
||||
|
||||
/*
|
||||
* Until all keys are released, defer further processing to
|
||||
* the polling loop in tegra_kbc_keypress_timer
|
||||
*/
|
||||
ctl = readl(kbc->mmio + KBC_CONTROL_0);
|
||||
ctl &= ~KBC_CONTROL_FIFO_CNT_INT_EN;
|
||||
writel(ctl, kbc->mmio + KBC_CONTROL_0);
|
||||
|
||||
/*
|
||||
* Quickly bail out & reenable interrupts if the fifo threshold
|
||||
* count interrupt wasn't the interrupt source
|
||||
*/
|
||||
val = readl(kbc->mmio + KBC_INT_0);
|
||||
writel(val, kbc->mmio + KBC_INT_0);
|
||||
|
||||
if (val & KBC_INT_FIFO_CNT_INT_STATUS) {
|
||||
/*
|
||||
* Schedule timer to run when hardware is in continuous
|
||||
* polling mode.
|
||||
*/
|
||||
mod_timer(&kbc->timer, jiffies + kbc->cp_dly_jiffies);
|
||||
} else {
|
||||
ctl |= KBC_CONTROL_FIFO_CNT_INT_EN;
|
||||
writel(ctl, kbc->mmio + KBC_CONTROL_0);
|
||||
}
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static void tegra_kbc_setup_wakekeys(struct tegra_kbc *kbc, bool filter)
|
||||
{
|
||||
const struct tegra_kbc_platform_data *pdata = kbc->pdata;
|
||||
int i;
|
||||
unsigned int rst_val;
|
||||
|
||||
BUG_ON(pdata->wake_cnt > KBC_MAX_KEY);
|
||||
rst_val = (filter && pdata->wake_cnt) ? ~0 : 0;
|
||||
|
||||
for (i = 0; i < KBC_MAX_ROW; i++)
|
||||
writel(rst_val, kbc->mmio + KBC_ROW0_MASK_0 + i * 4);
|
||||
|
||||
if (filter) {
|
||||
for (i = 0; i < pdata->wake_cnt; i++) {
|
||||
u32 val, addr;
|
||||
addr = pdata->wake_cfg[i].row * 4 + KBC_ROW0_MASK_0;
|
||||
val = readl(kbc->mmio + addr);
|
||||
val &= ~(1 << pdata->wake_cfg[i].col);
|
||||
writel(val, kbc->mmio + addr);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void tegra_kbc_config_pins(struct tegra_kbc *kbc)
|
||||
{
|
||||
const struct tegra_kbc_platform_data *pdata = kbc->pdata;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < KBC_MAX_GPIO; i++) {
|
||||
u32 r_shft = 5 * (i % 6);
|
||||
u32 c_shft = 4 * (i % 8);
|
||||
u32 r_mask = 0x1f << r_shft;
|
||||
u32 c_mask = 0x0f << c_shft;
|
||||
u32 r_offs = (i / 6) * 4 + KBC_ROW_CFG0_0;
|
||||
u32 c_offs = (i / 8) * 4 + KBC_COL_CFG0_0;
|
||||
u32 row_cfg = readl(kbc->mmio + r_offs);
|
||||
u32 col_cfg = readl(kbc->mmio + c_offs);
|
||||
|
||||
row_cfg &= ~r_mask;
|
||||
col_cfg &= ~c_mask;
|
||||
|
||||
if (pdata->pin_cfg[i].is_row)
|
||||
row_cfg |= ((pdata->pin_cfg[i].num << 1) | 1) << r_shft;
|
||||
else
|
||||
col_cfg |= ((pdata->pin_cfg[i].num << 1) | 1) << c_shft;
|
||||
|
||||
writel(row_cfg, kbc->mmio + r_offs);
|
||||
writel(col_cfg, kbc->mmio + c_offs);
|
||||
}
|
||||
}
|
||||
|
||||
static int tegra_kbc_start(struct tegra_kbc *kbc)
|
||||
{
|
||||
const struct tegra_kbc_platform_data *pdata = kbc->pdata;
|
||||
unsigned long flags;
|
||||
unsigned int debounce_cnt;
|
||||
u32 val = 0;
|
||||
|
||||
clk_enable(kbc->clk);
|
||||
|
||||
/* Reset the KBC controller to clear all previous status.*/
|
||||
tegra_periph_reset_assert(kbc->clk);
|
||||
udelay(100);
|
||||
tegra_periph_reset_deassert(kbc->clk);
|
||||
udelay(100);
|
||||
|
||||
tegra_kbc_config_pins(kbc);
|
||||
tegra_kbc_setup_wakekeys(kbc, false);
|
||||
|
||||
writel(pdata->repeat_cnt, kbc->mmio + KBC_RPT_DLY_0);
|
||||
|
||||
/* Keyboard debounce count is maximum of 12 bits. */
|
||||
debounce_cnt = min(pdata->debounce_cnt, KBC_MAX_DEBOUNCE_CNT);
|
||||
val = KBC_DEBOUNCE_CNT_SHIFT(debounce_cnt);
|
||||
val |= KBC_FIFO_TH_CNT_SHIFT(1); /* set fifo interrupt threshold to 1 */
|
||||
val |= KBC_CONTROL_FIFO_CNT_INT_EN; /* interrupt on FIFO threshold */
|
||||
val |= KBC_CONTROL_KBC_EN; /* enable */
|
||||
writel(val, kbc->mmio + KBC_CONTROL_0);
|
||||
|
||||
/*
|
||||
* Compute the delay(ns) from interrupt mode to continuous polling
|
||||
* mode so the timer routine is scheduled appropriately.
|
||||
*/
|
||||
val = readl(kbc->mmio + KBC_INIT_DLY_0);
|
||||
kbc->cp_dly_jiffies = usecs_to_jiffies((val & 0xfffff) * 32);
|
||||
|
||||
kbc->num_pressed_keys = 0;
|
||||
|
||||
/*
|
||||
* Atomically clear out any remaining entries in the key FIFO
|
||||
* and enable keyboard interrupts.
|
||||
*/
|
||||
spin_lock_irqsave(&kbc->lock, flags);
|
||||
while (1) {
|
||||
val = readl(kbc->mmio + KBC_INT_0);
|
||||
val >>= 4;
|
||||
if (!val)
|
||||
break;
|
||||
|
||||
val = readl(kbc->mmio + KBC_KP_ENT0_0);
|
||||
val = readl(kbc->mmio + KBC_KP_ENT1_0);
|
||||
}
|
||||
writel(0x7, kbc->mmio + KBC_INT_0);
|
||||
spin_unlock_irqrestore(&kbc->lock, flags);
|
||||
|
||||
enable_irq(kbc->irq);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void tegra_kbc_stop(struct tegra_kbc *kbc)
|
||||
{
|
||||
unsigned long flags;
|
||||
u32 val;
|
||||
|
||||
spin_lock_irqsave(&kbc->lock, flags);
|
||||
val = readl(kbc->mmio + KBC_CONTROL_0);
|
||||
val &= ~1;
|
||||
writel(val, kbc->mmio + KBC_CONTROL_0);
|
||||
spin_unlock_irqrestore(&kbc->lock, flags);
|
||||
|
||||
disable_irq(kbc->irq);
|
||||
del_timer_sync(&kbc->timer);
|
||||
|
||||
clk_disable(kbc->clk);
|
||||
}
|
||||
|
||||
static int tegra_kbc_open(struct input_dev *dev)
|
||||
{
|
||||
struct tegra_kbc *kbc = input_get_drvdata(dev);
|
||||
|
||||
return tegra_kbc_start(kbc);
|
||||
}
|
||||
|
||||
static void tegra_kbc_close(struct input_dev *dev)
|
||||
{
|
||||
struct tegra_kbc *kbc = input_get_drvdata(dev);
|
||||
|
||||
return tegra_kbc_stop(kbc);
|
||||
}
|
||||
|
||||
static bool __devinit
|
||||
tegra_kbc_check_pin_cfg(const struct tegra_kbc_platform_data *pdata,
|
||||
struct device *dev, unsigned int *num_rows)
|
||||
{
|
||||
int i;
|
||||
|
||||
*num_rows = 0;
|
||||
|
||||
for (i = 0; i < KBC_MAX_GPIO; i++) {
|
||||
const struct tegra_kbc_pin_cfg *pin_cfg = &pdata->pin_cfg[i];
|
||||
|
||||
if (pin_cfg->is_row) {
|
||||
if (pin_cfg->num >= KBC_MAX_ROW) {
|
||||
dev_err(dev,
|
||||
"pin_cfg[%d]: invalid row number %d\n",
|
||||
i, pin_cfg->num);
|
||||
return false;
|
||||
}
|
||||
(*num_rows)++;
|
||||
} else {
|
||||
if (pin_cfg->num >= KBC_MAX_COL) {
|
||||
dev_err(dev,
|
||||
"pin_cfg[%d]: invalid column number %d\n",
|
||||
i, pin_cfg->num);
|
||||
return false;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static int __devinit tegra_kbc_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct tegra_kbc_platform_data *pdata = pdev->dev.platform_data;
|
||||
const struct matrix_keymap_data *keymap_data;
|
||||
struct tegra_kbc *kbc;
|
||||
struct input_dev *input_dev;
|
||||
struct resource *res;
|
||||
int irq;
|
||||
int err;
|
||||
int i;
|
||||
int num_rows = 0;
|
||||
unsigned int debounce_cnt;
|
||||
unsigned int scan_time_rows;
|
||||
|
||||
if (!pdata)
|
||||
return -EINVAL;
|
||||
|
||||
if (!tegra_kbc_check_pin_cfg(pdata, &pdev->dev, &num_rows))
|
||||
return -EINVAL;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res) {
|
||||
dev_err(&pdev->dev, "failed to get I/O memory\n");
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0) {
|
||||
dev_err(&pdev->dev, "failed to get keyboard IRQ\n");
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
kbc = kzalloc(sizeof(*kbc), GFP_KERNEL);
|
||||
input_dev = input_allocate_device();
|
||||
if (!kbc || !input_dev) {
|
||||
err = -ENOMEM;
|
||||
goto err_free_mem;
|
||||
}
|
||||
|
||||
kbc->pdata = pdata;
|
||||
kbc->idev = input_dev;
|
||||
kbc->irq = irq;
|
||||
spin_lock_init(&kbc->lock);
|
||||
setup_timer(&kbc->timer, tegra_kbc_keypress_timer, (unsigned long)kbc);
|
||||
|
||||
res = request_mem_region(res->start, resource_size(res), pdev->name);
|
||||
if (!res) {
|
||||
dev_err(&pdev->dev, "failed to request I/O memory\n");
|
||||
err = -EBUSY;
|
||||
goto err_free_mem;
|
||||
}
|
||||
|
||||
kbc->mmio = ioremap(res->start, resource_size(res));
|
||||
if (!kbc->mmio) {
|
||||
dev_err(&pdev->dev, "failed to remap I/O memory\n");
|
||||
err = -ENXIO;
|
||||
goto err_free_mem_region;
|
||||
}
|
||||
|
||||
kbc->clk = clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(kbc->clk)) {
|
||||
dev_err(&pdev->dev, "failed to get keyboard clock\n");
|
||||
err = PTR_ERR(kbc->clk);
|
||||
goto err_iounmap;
|
||||
}
|
||||
|
||||
kbc->wake_enable_rows = 0;
|
||||
kbc->wake_enable_cols = 0;
|
||||
for (i = 0; i < pdata->wake_cnt; i++) {
|
||||
kbc->wake_enable_rows |= (1 << pdata->wake_cfg[i].row);
|
||||
kbc->wake_enable_cols |= (1 << pdata->wake_cfg[i].col);
|
||||
}
|
||||
|
||||
/*
|
||||
* The time delay between two consecutive reads of the FIFO is
|
||||
* the sum of the repeat time and the time taken for scanning
|
||||
* the rows. There is an additional delay before the row scanning
|
||||
* starts. The repoll delay is computed in milliseconds.
|
||||
*/
|
||||
debounce_cnt = min(pdata->debounce_cnt, KBC_MAX_DEBOUNCE_CNT);
|
||||
scan_time_rows = (KBC_ROW_SCAN_TIME + debounce_cnt) * num_rows;
|
||||
kbc->repoll_dly = KBC_ROW_SCAN_DLY + scan_time_rows + pdata->repeat_cnt;
|
||||
kbc->repoll_dly = ((kbc->repoll_dly * KBC_CYCLE_USEC) + 999) / 1000;
|
||||
|
||||
input_dev->name = pdev->name;
|
||||
input_dev->id.bustype = BUS_HOST;
|
||||
input_dev->dev.parent = &pdev->dev;
|
||||
input_dev->open = tegra_kbc_open;
|
||||
input_dev->close = tegra_kbc_close;
|
||||
|
||||
input_set_drvdata(input_dev, kbc);
|
||||
|
||||
input_dev->evbit[0] = BIT_MASK(EV_KEY);
|
||||
input_set_capability(input_dev, EV_MSC, MSC_SCAN);
|
||||
|
||||
input_dev->keycode = kbc->keycode;
|
||||
input_dev->keycodesize = sizeof(kbc->keycode[0]);
|
||||
input_dev->keycodemax = ARRAY_SIZE(kbc->keycode);
|
||||
|
||||
keymap_data = pdata->keymap_data ?: &tegra_kbc_default_keymap_data;
|
||||
matrix_keypad_build_keymap(keymap_data, KBC_ROW_SHIFT,
|
||||
input_dev->keycode, input_dev->keybit);
|
||||
|
||||
err = request_irq(kbc->irq, tegra_kbc_isr, IRQF_TRIGGER_HIGH,
|
||||
pdev->name, kbc);
|
||||
if (err) {
|
||||
dev_err(&pdev->dev, "failed to request keyboard IRQ\n");
|
||||
goto err_put_clk;
|
||||
}
|
||||
|
||||
disable_irq(kbc->irq);
|
||||
|
||||
err = input_register_device(kbc->idev);
|
||||
if (err) {
|
||||
dev_err(&pdev->dev, "failed to register input device\n");
|
||||
goto err_free_irq;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, kbc);
|
||||
device_init_wakeup(&pdev->dev, pdata->wakeup);
|
||||
|
||||
return 0;
|
||||
|
||||
err_free_irq:
|
||||
free_irq(kbc->irq, pdev);
|
||||
err_put_clk:
|
||||
clk_put(kbc->clk);
|
||||
err_iounmap:
|
||||
iounmap(kbc->mmio);
|
||||
err_free_mem_region:
|
||||
release_mem_region(res->start, resource_size(res));
|
||||
err_free_mem:
|
||||
input_free_device(kbc->idev);
|
||||
kfree(kbc);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int __devexit tegra_kbc_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct tegra_kbc *kbc = platform_get_drvdata(pdev);
|
||||
struct resource *res;
|
||||
|
||||
free_irq(kbc->irq, pdev);
|
||||
clk_put(kbc->clk);
|
||||
|
||||
input_unregister_device(kbc->idev);
|
||||
iounmap(kbc->mmio);
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
release_mem_region(res->start, resource_size(res));
|
||||
|
||||
kfree(kbc);
|
||||
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static int tegra_kbc_suspend(struct device *dev)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(dev);
|
||||
struct tegra_kbc *kbc = platform_get_drvdata(pdev);
|
||||
|
||||
if (device_may_wakeup(&pdev->dev)) {
|
||||
tegra_kbc_setup_wakekeys(kbc, true);
|
||||
enable_irq_wake(kbc->irq);
|
||||
/* Forcefully clear the interrupt status */
|
||||
writel(0x7, kbc->mmio + KBC_INT_0);
|
||||
msleep(30);
|
||||
} else {
|
||||
mutex_lock(&kbc->idev->mutex);
|
||||
if (kbc->idev->users)
|
||||
tegra_kbc_stop(kbc);
|
||||
mutex_unlock(&kbc->idev->mutex);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra_kbc_resume(struct device *dev)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(dev);
|
||||
struct tegra_kbc *kbc = platform_get_drvdata(pdev);
|
||||
int err = 0;
|
||||
|
||||
if (device_may_wakeup(&pdev->dev)) {
|
||||
disable_irq_wake(kbc->irq);
|
||||
tegra_kbc_setup_wakekeys(kbc, false);
|
||||
} else {
|
||||
mutex_lock(&kbc->idev->mutex);
|
||||
if (kbc->idev->users)
|
||||
err = tegra_kbc_start(kbc);
|
||||
mutex_unlock(&kbc->idev->mutex);
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
#endif
|
||||
|
||||
static SIMPLE_DEV_PM_OPS(tegra_kbc_pm_ops, tegra_kbc_suspend, tegra_kbc_resume);
|
||||
|
||||
static struct platform_driver tegra_kbc_driver = {
|
||||
.probe = tegra_kbc_probe,
|
||||
.remove = __devexit_p(tegra_kbc_remove),
|
||||
.driver = {
|
||||
.name = "tegra-kbc",
|
||||
.owner = THIS_MODULE,
|
||||
.pm = &tegra_kbc_pm_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static void __exit tegra_kbc_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&tegra_kbc_driver);
|
||||
}
|
||||
module_exit(tegra_kbc_exit);
|
||||
|
||||
static int __init tegra_kbc_init(void)
|
||||
{
|
||||
return platform_driver_register(&tegra_kbc_driver);
|
||||
}
|
||||
module_init(tegra_kbc_init);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_AUTHOR("Rakesh Iyer <riyer@nvidia.com>");
|
||||
MODULE_DESCRIPTION("Tegra matrix keyboard controller driver");
|
||||
MODULE_ALIAS("platform:tegra-kbc");
|
@ -14,6 +14,7 @@
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/input.h>
|
||||
#include <linux/platform_device.h>
|
||||
@ -219,9 +220,9 @@ static int __devinit keypad_probe(struct platform_device *pdev)
|
||||
}
|
||||
|
||||
kp->clk = clk_get(dev, NULL);
|
||||
if (!kp->clk) {
|
||||
if (IS_ERR(kp->clk)) {
|
||||
dev_err(dev, "cannot claim device clock\n");
|
||||
error = -EINVAL;
|
||||
error = PTR_ERR(kp->clk);
|
||||
goto error_clk;
|
||||
}
|
||||
|
||||
|
@ -755,23 +755,26 @@ static int synaptics_reconnect(struct psmouse *psmouse)
|
||||
{
|
||||
struct synaptics_data *priv = psmouse->private;
|
||||
struct synaptics_data old_priv = *priv;
|
||||
int retry = 0;
|
||||
int error;
|
||||
|
||||
psmouse_reset(psmouse);
|
||||
do {
|
||||
psmouse_reset(psmouse);
|
||||
error = synaptics_detect(psmouse, 0);
|
||||
} while (error && ++retry < 3);
|
||||
|
||||
if (synaptics_detect(psmouse, 0))
|
||||
if (error)
|
||||
return -1;
|
||||
|
||||
if (retry > 1)
|
||||
printk(KERN_DEBUG "Synaptics reconnected after %d tries\n",
|
||||
retry);
|
||||
|
||||
if (synaptics_query_hardware(psmouse)) {
|
||||
printk(KERN_ERR "Unable to query Synaptics hardware.\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (old_priv.identity != priv->identity ||
|
||||
old_priv.model_id != priv->model_id ||
|
||||
old_priv.capabilities != priv->capabilities ||
|
||||
old_priv.ext_cap != priv->ext_cap)
|
||||
return -1;
|
||||
|
||||
if (synaptics_set_absolute_mode(psmouse)) {
|
||||
printk(KERN_ERR "Unable to initialize Synaptics hardware.\n");
|
||||
return -1;
|
||||
@ -782,6 +785,19 @@ static int synaptics_reconnect(struct psmouse *psmouse)
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (old_priv.identity != priv->identity ||
|
||||
old_priv.model_id != priv->model_id ||
|
||||
old_priv.capabilities != priv->capabilities ||
|
||||
old_priv.ext_cap != priv->ext_cap) {
|
||||
printk(KERN_ERR "Synaptics hardware appears to be different: "
|
||||
"id(%ld-%ld), model(%ld-%ld), caps(%lx-%lx), ext(%lx-%lx).\n",
|
||||
old_priv.identity, priv->identity,
|
||||
old_priv.model_id, priv->model_id,
|
||||
old_priv.capabilities, priv->capabilities,
|
||||
old_priv.ext_cap, priv->ext_cap);
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -111,9 +111,11 @@ static void ct82c710_close(struct serio *serio)
|
||||
static int ct82c710_open(struct serio *serio)
|
||||
{
|
||||
unsigned char status;
|
||||
int err;
|
||||
|
||||
if (request_irq(CT82C710_IRQ, ct82c710_interrupt, 0, "ct82c710", NULL))
|
||||
return -1;
|
||||
err = request_irq(CT82C710_IRQ, ct82c710_interrupt, 0, "ct82c710", NULL);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
status = inb_p(CT82C710_STATUS);
|
||||
|
||||
@ -131,7 +133,7 @@ static int ct82c710_open(struct serio *serio)
|
||||
status &= ~(CT82C710_ENABLE | CT82C710_INTS_ON);
|
||||
outb_p(status, CT82C710_STATUS);
|
||||
free_irq(CT82C710_IRQ, NULL);
|
||||
return -1;
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
@ -116,14 +116,15 @@ static void serport_ldisc_close(struct tty_struct *tty)
|
||||
|
||||
/*
|
||||
* serport_ldisc_receive() is called by the low level tty driver when characters
|
||||
* are ready for us. We forward the characters, one by one to the 'interrupt'
|
||||
* routine.
|
||||
* are ready for us. We forward the characters and flags, one by one to the
|
||||
* 'interrupt' routine.
|
||||
*/
|
||||
|
||||
static void serport_ldisc_receive(struct tty_struct *tty, const unsigned char *cp, char *fp, int count)
|
||||
{
|
||||
struct serport *serport = (struct serport*) tty->disc_data;
|
||||
unsigned long flags;
|
||||
unsigned int ch_flags;
|
||||
int i;
|
||||
|
||||
spin_lock_irqsave(&serport->lock, flags);
|
||||
@ -131,8 +132,23 @@ static void serport_ldisc_receive(struct tty_struct *tty, const unsigned char *c
|
||||
if (!test_bit(SERPORT_ACTIVE, &serport->flags))
|
||||
goto out;
|
||||
|
||||
for (i = 0; i < count; i++)
|
||||
serio_interrupt(serport->serio, cp[i], 0);
|
||||
for (i = 0; i < count; i++) {
|
||||
switch (fp[i]) {
|
||||
case TTY_FRAME:
|
||||
ch_flags = SERIO_FRAME;
|
||||
break;
|
||||
|
||||
case TTY_PARITY:
|
||||
ch_flags = SERIO_PARITY;
|
||||
break;
|
||||
|
||||
default:
|
||||
ch_flags = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
serio_interrupt(serport->serio, cp[i], ch_flags);
|
||||
}
|
||||
|
||||
out:
|
||||
spin_unlock_irqrestore(&serport->lock, flags);
|
||||
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user