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drm/msm/mdp5: Misc cursor plane bits
These are various changes added in preparation for cursor planes: - Add a pipe_cursor block for 8x96 in mdp5_cfg. - Add a new pipe CAP called MDP_PIPE_CAP_CURSOR. Use this to ensure we assign a cursor SSPP for a drm_plane with type DRM_PLANE_TYPE_CURSOR. - Update mdp5_ctl_blend_mask/ext_blend_mask funcs to incorporate cursor SSPPs. - In mdp5_ctl_blend, iterate through MAX_STAGES instead of stage_cnt, we need to do this because we can now have empty stages in between. - In mdp5_crtc_atomic_check, make sure that the cursor plane has the highest zorder, and stage the cursor plane to the maximum stage # present on the HW. - Create drm_crtc_funcs that doesn't try to implement cursors using the older LM cursor HW. - Pass drm_plane_type in mdp5_plane_init instead of a bool telling whether plane is primary or not. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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829200ac91
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5798c8e0d3
@ -421,6 +421,16 @@ const struct mdp5_cfg_hw msm8x96_config = {
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MDP_PIPE_CAP_SW_PIX_EXT |
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0,
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},
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.pipe_cursor = {
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.count = 2,
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.base = { 0x34000, 0x36000 },
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.caps = MDP_PIPE_CAP_HFLIP |
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MDP_PIPE_CAP_VFLIP |
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MDP_PIPE_CAP_SW_PIX_EXT |
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MDP_PIPE_CAP_CURSOR |
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0,
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},
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.lm = {
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.count = 6,
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.base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 },
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@ -400,6 +400,7 @@ static int mdp5_crtc_atomic_check(struct drm_crtc *crtc,
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struct plane_state pstates[STAGE_MAX + 1];
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const struct mdp5_cfg_hw *hw_cfg;
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const struct drm_plane_state *pstate;
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bool cursor_plane = false;
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int cnt = 0, base = 0, i;
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DBG("%s: check", crtc->name);
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@ -409,6 +410,9 @@ static int mdp5_crtc_atomic_check(struct drm_crtc *crtc,
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pstates[cnt].state = to_mdp5_plane_state(pstate);
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cnt++;
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if (plane->type == DRM_PLANE_TYPE_CURSOR)
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cursor_plane = true;
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}
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/* assign a stage based on sorted zpos property */
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@ -420,6 +424,10 @@ static int mdp5_crtc_atomic_check(struct drm_crtc *crtc,
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if ((cnt > 0) && !is_fullscreen(state, &pstates[0].state->base))
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base++;
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/* trigger a warning if cursor isn't the highest zorder */
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WARN_ON(cursor_plane &&
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(pstates[cnt - 1].plane->type != DRM_PLANE_TYPE_CURSOR));
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/* verify that there are not too many planes attached to crtc
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* and that we don't have conflicting mixer stages:
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*/
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@ -431,7 +439,10 @@ static int mdp5_crtc_atomic_check(struct drm_crtc *crtc,
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}
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for (i = 0; i < cnt; i++) {
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pstates[i].state->stage = STAGE_BASE + i + base;
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if (cursor_plane && (i == (cnt - 1)))
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pstates[i].state->stage = hw_cfg->lm.nb_stages;
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else
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pstates[i].state->stage = STAGE_BASE + i + base;
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DBG("%s: assign pipe %s on stage=%d", crtc->name,
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pstates[i].plane->name,
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pstates[i].state->stage);
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@ -642,6 +653,16 @@ static const struct drm_crtc_funcs mdp5_crtc_funcs = {
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.cursor_move = mdp5_crtc_cursor_move,
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};
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static const struct drm_crtc_funcs mdp5_crtc_no_lm_cursor_funcs = {
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.set_config = drm_atomic_helper_set_config,
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.destroy = mdp5_crtc_destroy,
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.page_flip = drm_atomic_helper_page_flip,
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.set_property = drm_atomic_helper_crtc_set_property,
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.reset = drm_atomic_helper_crtc_reset,
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.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
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.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
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};
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static const struct drm_crtc_helper_funcs mdp5_crtc_helper_funcs = {
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.mode_set_nofb = mdp5_crtc_mode_set_nofb,
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.disable = mdp5_crtc_disable,
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@ -775,7 +796,8 @@ void mdp5_crtc_wait_for_commit_done(struct drm_crtc *crtc)
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/* initialize crtc */
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struct drm_crtc *mdp5_crtc_init(struct drm_device *dev,
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struct drm_plane *plane, int id)
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struct drm_plane *plane,
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struct drm_plane *cursor_plane, int id)
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{
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struct drm_crtc *crtc = NULL;
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struct mdp5_crtc *mdp5_crtc;
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@ -796,8 +818,12 @@ struct drm_crtc *mdp5_crtc_init(struct drm_device *dev,
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mdp5_crtc->vblank.irq = mdp5_crtc_vblank_irq;
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mdp5_crtc->err.irq = mdp5_crtc_err_irq;
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drm_crtc_init_with_planes(dev, crtc, plane, NULL, &mdp5_crtc_funcs,
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NULL);
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if (cursor_plane)
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drm_crtc_init_with_planes(dev, crtc, plane, cursor_plane,
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&mdp5_crtc_no_lm_cursor_funcs, NULL);
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else
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drm_crtc_init_with_planes(dev, crtc, plane, NULL,
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&mdp5_crtc_funcs, NULL);
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drm_flip_work_init(&mdp5_crtc->unref_cursor_work,
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"unref cursor", unref_cursor_worker);
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@ -326,6 +326,8 @@ static u32 mdp_ctl_blend_mask(enum mdp5_pipe pipe,
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case SSPP_DMA1: return MDP5_CTL_LAYER_REG_DMA1(stage);
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case SSPP_VIG3: return MDP5_CTL_LAYER_REG_VIG3(stage);
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case SSPP_RGB3: return MDP5_CTL_LAYER_REG_RGB3(stage);
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case SSPP_CURSOR0:
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case SSPP_CURSOR1:
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default: return 0;
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}
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}
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@ -333,7 +335,7 @@ static u32 mdp_ctl_blend_mask(enum mdp5_pipe pipe,
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static u32 mdp_ctl_blend_ext_mask(enum mdp5_pipe pipe,
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enum mdp_mixer_stage_id stage)
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{
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if (stage < STAGE6)
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if (stage < STAGE6 && (pipe != SSPP_CURSOR0 && pipe != SSPP_CURSOR1))
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return 0;
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switch (pipe) {
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@ -347,6 +349,8 @@ static u32 mdp_ctl_blend_ext_mask(enum mdp5_pipe pipe,
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case SSPP_DMA1: return MDP5_CTL_LAYER_EXT_REG_DMA1_BIT3;
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case SSPP_VIG3: return MDP5_CTL_LAYER_EXT_REG_VIG3_BIT3;
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case SSPP_RGB3: return MDP5_CTL_LAYER_EXT_REG_RGB3_BIT3;
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case SSPP_CURSOR0: return MDP5_CTL_LAYER_EXT_REG_CURSOR0(stage);
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case SSPP_CURSOR1: return MDP5_CTL_LAYER_EXT_REG_CURSOR1(stage);
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default: return 0;
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}
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}
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@ -365,7 +369,7 @@ int mdp5_ctl_blend(struct mdp5_ctl *ctl, enum mdp5_pipe *stage, u32 stage_cnt,
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start_stage = STAGE_BASE;
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}
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for (i = start_stage; i < start_stage + stage_cnt; i++) {
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for (i = start_stage; stage_cnt && i <= STAGE_MAX; i++) {
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blend_cfg |= mdp_ctl_blend_mask(stage[i], i);
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blend_ext_cfg |= mdp_ctl_blend_ext_mask(stage[i], i);
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}
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@ -422,6 +426,8 @@ u32 mdp_ctl_flush_mask_pipe(enum mdp5_pipe pipe)
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case SSPP_DMA1: return MDP5_CTL_FLUSH_DMA1;
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case SSPP_VIG3: return MDP5_CTL_FLUSH_VIG3;
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case SSPP_RGB3: return MDP5_CTL_FLUSH_RGB3;
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case SSPP_CURSOR0: return MDP5_CTL_FLUSH_CURSOR_0;
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case SSPP_CURSOR1: return MDP5_CTL_FLUSH_CURSOR_1;
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default: return 0;
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}
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}
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@ -441,8 +441,14 @@ static int modeset_init(struct mdp5_kms *mdp5_kms)
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bool primary = i < num_crtcs;
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struct drm_plane *plane;
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struct drm_crtc *crtc;
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enum drm_plane_type type;
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plane = mdp5_plane_init(dev, primary);
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if (primary)
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type = DRM_PLANE_TYPE_PRIMARY;
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else
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type = DRM_PLANE_TYPE_OVERLAY;
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plane = mdp5_plane_init(dev, type);
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if (IS_ERR(plane)) {
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ret = PTR_ERR(plane);
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dev_err(dev->dev, "failed to construct plane %d (%d)\n", i, ret);
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@ -453,7 +459,7 @@ static int modeset_init(struct mdp5_kms *mdp5_kms)
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if (!primary)
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continue;
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crtc = mdp5_crtc_init(dev, plane, i);
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crtc = mdp5_crtc_init(dev, plane, NULL, i);
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if (IS_ERR(crtc)) {
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ret = PTR_ERR(crtc);
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dev_err(dev->dev, "failed to construct crtc %d (%d)\n", i, ret);
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@ -167,6 +167,7 @@ static inline const char *pipe2name(enum mdp5_pipe pipe)
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NAME(RGB0), NAME(RGB1), NAME(RGB2),
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NAME(DMA0), NAME(DMA1),
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NAME(VIG3), NAME(RGB3),
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NAME(CURSOR0), NAME(CURSOR1),
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#undef NAME
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};
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return names[pipe];
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@ -242,7 +243,8 @@ void mdp5_irq_domain_fini(struct mdp5_kms *mdp5_kms);
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uint32_t mdp5_plane_get_flush(struct drm_plane *plane);
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enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane);
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struct drm_plane *mdp5_plane_init(struct drm_device *dev, bool primary);
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struct drm_plane *mdp5_plane_init(struct drm_device *dev,
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enum drm_plane_type type);
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uint32_t mdp5_crtc_vblank(struct drm_crtc *crtc);
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@ -251,7 +253,8 @@ void mdp5_crtc_set_pipeline(struct drm_crtc *crtc,
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struct mdp5_interface *intf, struct mdp5_ctl *ctl);
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void mdp5_crtc_wait_for_commit_done(struct drm_crtc *crtc);
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struct drm_crtc *mdp5_crtc_init(struct drm_device *dev,
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struct drm_plane *plane, int id);
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struct drm_plane *plane,
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struct drm_plane *cursor_plane, int id);
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struct drm_encoder *mdp5_encoder_init(struct drm_device *dev,
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struct mdp5_interface *intf, struct mdp5_ctl *ctl);
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@ -53,6 +53,14 @@ struct mdp5_hw_pipe *mdp5_pipe_assign(struct drm_atomic_state *s,
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if (caps & ~cur->caps)
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continue;
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/*
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* don't assign a cursor pipe to a plane that isn't going to
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* be used as a cursor
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*/
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if (cur->caps & MDP_PIPE_CAP_CURSOR &&
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plane->type != DRM_PLANE_TYPE_CURSOR)
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continue;
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/* possible candidate, take the one with the
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* fewest unneeded caps bits set:
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*/
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@ -344,6 +344,9 @@ static int mdp5_plane_atomic_check(struct drm_plane *plane,
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if (rotation & DRM_REFLECT_Y)
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caps |= MDP_PIPE_CAP_VFLIP;
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if (plane->type == DRM_PLANE_TYPE_CURSOR)
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caps |= MDP_PIPE_CAP_CURSOR;
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/* (re)allocate hw pipe if we don't have one or caps-mismatch: */
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if (!mdp5_state->hwpipe || (caps & ~mdp5_state->hwpipe->caps))
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new_hwpipe = true;
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@ -870,12 +873,12 @@ uint32_t mdp5_plane_get_flush(struct drm_plane *plane)
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}
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/* initialize plane */
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struct drm_plane *mdp5_plane_init(struct drm_device *dev, bool primary)
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struct drm_plane *mdp5_plane_init(struct drm_device *dev,
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enum drm_plane_type type)
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{
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struct drm_plane *plane = NULL;
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struct mdp5_plane *mdp5_plane;
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int ret;
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enum drm_plane_type type;
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mdp5_plane = kzalloc(sizeof(*mdp5_plane), GFP_KERNEL);
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if (!mdp5_plane) {
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@ -888,7 +891,6 @@ struct drm_plane *mdp5_plane_init(struct drm_device *dev, bool primary)
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mdp5_plane->nformats = mdp_get_formats(mdp5_plane->formats,
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ARRAY_SIZE(mdp5_plane->formats), false);
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type = primary ? DRM_PLANE_TYPE_PRIMARY : DRM_PLANE_TYPE_OVERLAY;
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ret = drm_universal_plane_init(dev, plane, 0xff, &mdp5_plane_funcs,
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mdp5_plane->formats, mdp5_plane->nformats,
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type, NULL);
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@ -112,6 +112,7 @@ const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format);
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#define MDP_PIPE_CAP_CSC BIT(3)
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#define MDP_PIPE_CAP_DECIMATION BIT(4)
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#define MDP_PIPE_CAP_SW_PIX_EXT BIT(5)
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#define MDP_PIPE_CAP_CURSOR BIT(6)
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static inline bool pipe_supports_yuv(uint32_t pipe_caps)
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{
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