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MIPS: octeon: Replace the homebrewn flow handler
The gpio interrupt handling of octeon contains a homebrewn flow handler which calls either handle_level_irq or handle_edge_irq depending on the trigger type. Thats an extra conditional and call in the interrupt handling path. The proper way to handle different types and therefor different flows is to update the handler in the irq_set_type() callback. Remove the extra indirection and add the handler update to octeon_irq_ciu_gpio_set_type(). At mapping time it defaults to handle_level_irq which gets updated if the device tree contains a different trigger type. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: David Daney <david.daney@cavium.com> Cc: Jiang Liu <jiang.liu@linux.intel.com> Cc: linux-mips@linux-mips.org Cc: LKML <linux-kernel@vger.kernel.org> Patchwork: https://patchwork.linux-mips.org/patch/10704/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -663,6 +663,11 @@ static int octeon_irq_ciu_gpio_set_type(struct irq_data *data, unsigned int t)
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irqd_set_trigger_type(data, t);
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octeon_irq_gpio_setup(data);
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if (irqd_get_trigger_type(data) & IRQ_TYPE_EDGE_BOTH)
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irq_set_handler_locked(data, handle_edge_irq);
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else
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irq_set_handler_locked(data, handle_level_irq);
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return IRQ_SET_MASK_OK;
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}
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@ -697,16 +702,6 @@ static void octeon_irq_ciu_gpio_ack(struct irq_data *data)
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cvmx_write_csr(CVMX_GPIO_INT_CLR, mask);
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}
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static void octeon_irq_handle_trigger(unsigned int irq, struct irq_desc *desc)
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{
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struct irq_data *data = irq_desc_get_irq_data(desc);
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if (irqd_get_trigger_type(data) & IRQ_TYPE_EDGE_BOTH)
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handle_edge_irq(irq, desc);
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else
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handle_level_irq(irq, desc);
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}
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#ifdef CONFIG_SMP
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static void octeon_irq_cpu_offline_ciu(struct irq_data *data)
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@ -1229,8 +1224,13 @@ static int octeon_irq_gpio_map(struct irq_domain *d,
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octeon_irq_ciu_to_irq[line][bit] != 0)
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return -EINVAL;
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/*
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* Default to handle_level_irq. If the DT contains a different
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* trigger type, it will call the irq_set_type callback and
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* the handler gets updated.
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*/
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r = octeon_irq_set_ciu_mapping(virq, line, bit, hw,
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octeon_irq_gpio_chip, octeon_irq_handle_trigger);
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octeon_irq_gpio_chip, handle_level_irq);
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return r;
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}
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