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x86/oprofile: add IBS support for AMD CPUs, model specific code
This patchset supports the new profiling hardware available in the latest AMD CPUs in the oProfile driver. Signed-off-by: Barry Kasindorf <barry.kasindorf@amd.com> Signed-off-by: Robert Richter <robert.richter@amd.com> Cc: oprofile-list <oprofile-list@lists.sourceforge.net> Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Barry Kasindorf
Ingo Molnar
parent
345c25730d
commit
56784f11df
@ -9,9 +9,13 @@
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* @author Philippe Elie
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* @author Graydon Hoare
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* @author Robert Richter <robert.richter@amd.com>
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* @author Barry Kasindorf
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*/
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#include <linux/oprofile.h>
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#include <linux/device.h>
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#include <linux/pci.h>
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#include <asm/ptrace.h>
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#include <asm/msr.h>
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#include <asm/nmi.h>
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@ -43,7 +47,83 @@
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#define CTRL_SET_HOST_ONLY(val, h) (val |= ((h & 1) << 9))
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#define CTRL_SET_GUEST_ONLY(val, h) (val |= ((h & 1) << 8))
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#define IBS_FETCH_CTL_HIGH_MASK 0xFFFFFFFF
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/* high dword bit IbsFetchCtl[bit 49] */
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#define IBS_FETCH_VALID_BIT (1UL << 17)
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/* high dword bit IbsFetchCtl[bit 52] */
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#define IBS_FETCH_PHY_ADDR_VALID_BIT (1UL << 20)
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/* high dword bit IbsFetchCtl[bit 48] */
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#define IBS_FETCH_ENABLE (1UL << 16)
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#define IBS_FETCH_CTL_CNT_MASK 0x00000000FFFF0000UL
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#define IBS_FETCH_CTL_MAX_CNT_MASK 0x000000000000FFFFUL
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/*IbsOpCtl masks/bits */
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#define IBS_OP_VALID_BIT (1ULL<<18) /* IbsOpCtl[bit18] */
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#define IBS_OP_ENABLE (1ULL<<17) /* IBS_OP_ENABLE[bit17]*/
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/* Codes used in cpu_buffer.c */
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#define IBS_FETCH_BEGIN 3
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#define IBS_OP_BEGIN 4
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/*IbsOpData3 masks */
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#define IBS_CTL_LVT_OFFSET_VALID_BIT (1ULL<<8)
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/*PCI Extended Configuration Constants */
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/* MSR to set the IBS control register APIC LVT offset */
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#define IBS_LVT_OFFSET_PCI 0x1CC
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struct ibs_fetch_sample {
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/* MSRC001_1031 IBS Fetch Linear Address Register */
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unsigned int ibs_fetch_lin_addr_low;
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unsigned int ibs_fetch_lin_addr_high;
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/* MSRC001_1030 IBS Fetch Control Register */
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unsigned int ibs_fetch_ctl_low;
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unsigned int ibs_fetch_ctl_high;
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/* MSRC001_1032 IBS Fetch Physical Address Register */
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unsigned int ibs_fetch_phys_addr_low;
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unsigned int ibs_fetch_phys_addr_high;
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};
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struct ibs_op_sample {
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/* MSRC001_1034 IBS Op Logical Address Register (IbsRIP) */
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unsigned int ibs_op_rip_low;
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unsigned int ibs_op_rip_high;
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/* MSRC001_1035 IBS Op Data Register */
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unsigned int ibs_op_data1_low;
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unsigned int ibs_op_data1_high;
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/* MSRC001_1036 IBS Op Data 2 Register */
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unsigned int ibs_op_data2_low;
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unsigned int ibs_op_data2_high;
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/* MSRC001_1037 IBS Op Data 3 Register */
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unsigned int ibs_op_data3_low;
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unsigned int ibs_op_data3_high;
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/* MSRC001_1038 IBS DC Linear Address Register (IbsDcLinAd) */
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unsigned int ibs_dc_linear_low;
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unsigned int ibs_dc_linear_high;
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/* MSRC001_1039 IBS DC Physical Address Register (IbsDcPhysAd) */
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unsigned int ibs_dc_phys_low;
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unsigned int ibs_dc_phys_high;
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};
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/*
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* unitialize the APIC for the IBS interrupts if needed on AMD Family10h+
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*/
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static void clear_ibs_nmi(void);
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static unsigned long reset_value[NUM_COUNTERS];
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static int ibs_allowed; /* AMD Family10h and later */
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struct op_ibs_config {
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unsigned long op_enabled;
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unsigned long fetch_enabled;
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unsigned long max_cnt_fetch;
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unsigned long max_cnt_op;
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unsigned long rand_en;
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unsigned long dispatched_ops;
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};
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static struct op_ibs_config ibs_config;
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/* functions for op_amd_spec */
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@ -121,6 +201,8 @@ static int op_amd_check_ctrs(struct pt_regs * const regs,
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{
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unsigned int low, high;
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int i;
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struct ibs_fetch_sample ibs_fetch;
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struct ibs_op_sample ibs_op;
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for (i = 0 ; i < NUM_COUNTERS; ++i) {
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if (!reset_value[i])
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@ -132,6 +214,65 @@ static int op_amd_check_ctrs(struct pt_regs * const regs,
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}
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}
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/*If AMD and IBS is available */
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if (ibs_allowed && ibs_config.fetch_enabled) {
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rdmsr(MSR_AMD64_IBSFETCHCTL, low, high);
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if (high & IBS_FETCH_VALID_BIT) {
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ibs_fetch.ibs_fetch_ctl_high = high;
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ibs_fetch.ibs_fetch_ctl_low = low;
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rdmsr(MSR_AMD64_IBSFETCHLINAD, low, high);
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ibs_fetch.ibs_fetch_lin_addr_high = high;
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ibs_fetch.ibs_fetch_lin_addr_low = low;
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rdmsr(MSR_AMD64_IBSFETCHPHYSAD, low, high);
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ibs_fetch.ibs_fetch_phys_addr_high = high;
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ibs_fetch.ibs_fetch_phys_addr_low = low;
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oprofile_add_ibs_sample(regs,
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(unsigned int *)&ibs_fetch,
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IBS_FETCH_BEGIN);
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/*reenable the IRQ */
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rdmsr(MSR_AMD64_IBSFETCHCTL, low, high);
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high &= ~(IBS_FETCH_VALID_BIT);
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high |= IBS_FETCH_ENABLE;
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low &= IBS_FETCH_CTL_MAX_CNT_MASK;
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wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
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}
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}
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if (ibs_allowed && ibs_config.op_enabled) {
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rdmsr(MSR_AMD64_IBSOPCTL, low, high);
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if (low & IBS_OP_VALID_BIT) {
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rdmsr(MSR_AMD64_IBSOPRIP, low, high);
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ibs_op.ibs_op_rip_low = low;
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ibs_op.ibs_op_rip_high = high;
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rdmsr(MSR_AMD64_IBSOPDATA, low, high);
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ibs_op.ibs_op_data1_low = low;
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ibs_op.ibs_op_data1_high = high;
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rdmsr(MSR_AMD64_IBSOPDATA2, low, high);
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ibs_op.ibs_op_data2_low = low;
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ibs_op.ibs_op_data2_high = high;
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rdmsr(MSR_AMD64_IBSOPDATA3, low, high);
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ibs_op.ibs_op_data3_low = low;
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ibs_op.ibs_op_data3_high = high;
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rdmsr(MSR_AMD64_IBSDCLINAD, low, high);
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ibs_op.ibs_dc_linear_low = low;
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ibs_op.ibs_dc_linear_high = high;
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rdmsr(MSR_AMD64_IBSDCPHYSAD, low, high);
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ibs_op.ibs_dc_phys_low = low;
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ibs_op.ibs_dc_phys_high = high;
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/* reenable the IRQ */
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oprofile_add_ibs_sample(regs,
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(unsigned int *)&ibs_op,
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IBS_OP_BEGIN);
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rdmsr(MSR_AMD64_IBSOPCTL, low, high);
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low &= ~(IBS_OP_VALID_BIT);
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low |= IBS_OP_ENABLE;
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wrmsr(MSR_AMD64_IBSOPCTL, low, high);
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}
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}
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/* See op_model_ppro.c */
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return 1;
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}
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@ -148,6 +289,17 @@ static void op_amd_start(struct op_msrs const * const msrs)
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CTRL_WRITE(low, high, msrs, i);
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}
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}
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if (ibs_allowed && ibs_config.fetch_enabled) {
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low = (ibs_config.max_cnt_fetch >> 4) & 0xFFFF;
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high = IBS_FETCH_ENABLE;
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wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
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}
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if (ibs_allowed && ibs_config.op_enabled) {
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low = ((ibs_config.max_cnt_op >> 4) & 0xFFFF) + IBS_OP_ENABLE;
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high = 0;
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wrmsr(MSR_AMD64_IBSOPCTL, low, high);
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}
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}
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@ -165,6 +317,18 @@ static void op_amd_stop(struct op_msrs const * const msrs)
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CTRL_SET_INACTIVE(low);
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CTRL_WRITE(low, high, msrs, i);
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}
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if (ibs_allowed && ibs_config.fetch_enabled) {
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low = 0; /* clear max count and enable */
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high = 0;
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wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
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}
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if (ibs_allowed && ibs_config.op_enabled) {
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low = 0; /* clear max count and enable */
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high = 0;
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wrmsr(MSR_AMD64_IBSOPCTL, low, high);
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}
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}
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static void op_amd_shutdown(struct op_msrs const * const msrs)
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@ -181,6 +345,99 @@ static void op_amd_shutdown(struct op_msrs const * const msrs)
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}
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}
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static inline void apic_init_ibs_nmi_per_cpu(void *arg)
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{
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setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_NMI, 0);
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}
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static inline void apic_clear_ibs_nmi_per_cpu(void *arg)
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{
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setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_FIX, 1);
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}
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/*
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* initialize the APIC for the IBS interrupts
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* if needed on AMD Family10h rev B0 and later
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*/
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static void setup_ibs(void)
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{
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struct pci_dev *gh_device = NULL;
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u32 low, high;
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u8 vector;
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ibs_allowed = boot_cpu_has(X86_FEATURE_IBS);
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if (!ibs_allowed)
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return;
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/* This gets the APIC_EILVT_LVTOFF_IBS value */
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vector = setup_APIC_eilvt_ibs(0, 0, 1);
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/*see if the IBS control register is already set correctly*/
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/*remove this when we know for sure it is done
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in the kernel init*/
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rdmsr(MSR_AMD64_IBSCTL, low, high);
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if ((low & (IBS_CTL_LVT_OFFSET_VALID_BIT | vector)) !=
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(IBS_CTL_LVT_OFFSET_VALID_BIT | vector)) {
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/**** Be sure to run loop until NULL is returned to
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decrement reference count on any pci_dev structures
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returned ****/
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while ((gh_device = pci_get_device(PCI_VENDOR_ID_AMD,
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PCI_DEVICE_ID_AMD_10H_NB_MISC, gh_device))
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!= NULL) {
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/* This code may change if we can find a proper
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* way to get at the PCI extended config space */
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pci_write_config_dword(
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gh_device, IBS_LVT_OFFSET_PCI,
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(vector | IBS_CTL_LVT_OFFSET_VALID_BIT));
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}
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}
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on_each_cpu(apic_init_ibs_nmi_per_cpu, NULL, 1, 1);
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}
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/*
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* unitialize the APIC for the IBS interrupts if needed on AMD Family10h
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* rev B0 and later */
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static void clear_ibs_nmi(void)
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{
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if (ibs_allowed)
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on_each_cpu(apic_clear_ibs_nmi_per_cpu, NULL, 1, 1);
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}
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static void setup_ibs_files(struct super_block *sb, struct dentry *root)
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{
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char buf[12];
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struct dentry *dir;
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if (!ibs_allowed)
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return;
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/* setup some reasonable defaults */
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ibs_config.max_cnt_fetch = 250000;
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ibs_config.fetch_enabled = 0;
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ibs_config.max_cnt_op = 250000;
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ibs_config.op_enabled = 0;
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ibs_config.dispatched_ops = 1;
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snprintf(buf, sizeof(buf), "ibs_fetch");
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dir = oprofilefs_mkdir(sb, root, buf);
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oprofilefs_create_ulong(sb, dir, "rand_enable",
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&ibs_config.rand_en);
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oprofilefs_create_ulong(sb, dir, "enable",
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&ibs_config.fetch_enabled);
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oprofilefs_create_ulong(sb, dir, "max_count",
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&ibs_config.max_cnt_fetch);
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snprintf(buf, sizeof(buf), "ibs_uops");
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dir = oprofilefs_mkdir(sb, root, buf);
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oprofilefs_create_ulong(sb, dir, "enable",
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&ibs_config.op_enabled);
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oprofilefs_create_ulong(sb, dir, "max_count",
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&ibs_config.max_cnt_op);
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oprofilefs_create_ulong(sb, dir, "dispatched_ops",
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&ibs_config.dispatched_ops);
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}
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static int op_amd_init(struct oprofile_operations *ops)
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{
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return 0;
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