mirror of
https://github.com/edk2-porting/linux-next.git
synced 2025-01-04 03:33:58 +08:00
ARMv8 Juno/Vexpress/Fast Models updates for v5.8
Various miscellaneous device tree source fixes to make them fully binding compliant. It includes fixing various device node names, order of interrupt properties, compatible names, address and size cell fields and their aligment with children nodes as well as moving some fixed devices out of bus node. -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEunHlEgbzHrJD3ZPhAEG6vDF+4pgFAl7DqaoACgkQAEG6vDF+ 4phj+xAAw0pYfFBqH89qx7dl+BgKl4SMpue0WlhUgiZhbBS2RgrlGTW5TfBb6IVa boU30Vw4rOdPozy7xizC0JnHsoD8PTxWKbA2t6s3VtTra3iGU0gT7wua/rzQ9pC2 yrk7mTMpa6j5FUdTNSkQwr3x5g95K5haTZV2kRZFBNHzgjZmh02BhGmfQ1TX+sbw 4vEde0xi1dOi9/A78gIWSUbvpdniFrYBkOAbMN8bo37KoCvnuvm2OU6t0UF6nj3h 51eKZjWbxxxh5Jj2DyFZzOaEW9T2vIeW6aqoNEinvz9blSUBmX8Dx8n2YZbUVr/O ZsnfMXwU3SeRlIt4avNguGk0+xQuHAzy+Jls+A/ypTUL1vX8kTwO7Gs6gOZHsQ9n DwFhoWesk86EQyzBy3t1mmvWU7Ic2YMjfW6WjmWxgccuTfTEbSZ6VAA/TQWQtvop 6xUtUbLJr1yuBshVsoJyO/yR1MoAnVKsOjB+AbiTW+nqs4oAoQ4q6TLti/z20G/k l3cTdKVC97cqhXa9hEuIP5wTTBJ7uQJ0boR7fvdrfk0doRvEAI5Xh/OyCWKi2SUH 6nqUEtDoXFfUBfqLEj/uETQzHCo2CQPIyubJB0XhWkT+52/0Gi6KHzq6GvNrb7gt tx27VizSRz1f1nbZ6jYi0MMnyGBjnRw+HIDBuiUU7kgFIGkJheI= =Z5QL -----END PGP SIGNATURE----- Merge tag 'juno-updates-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/dt ARMv8 Juno/Vexpress/Fast Models updates for v5.8 Various miscellaneous device tree source fixes to make them fully binding compliant. It includes fixing various device node names, order of interrupt properties, compatible names, address and size cell fields and their aligment with children nodes as well as moving some fixed devices out of bus node. * tag 'juno-updates-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: arm64: dts: juno: Fix SCPI shared mem node name arm64: dts: vexpress: Fix VExpress LED names arm64: dts: juno: Fix GPU interrupt order arm64: dts: fvp/juno: Fix bus node names arm64: dts: fvp: Fix SMMU DT node arm64: dts: fvp/juno: Fix serial node names arm64: dts: juno: Use proper DT node name for USB arm64: dts: fvp: Fix ITS node names and #msi-cells arm64: dts: fvp: Fix GIC child nodes arm64: dts: juno: Fix GIC child nodes arm64: dts: fvp: Fix GIC compatible names arm64: dts: juno: Fix mem-timer arm64: dts: juno: Move fixed devices out of bus node arm64: dts: fvp: Move fixed clocks out of bus node arm64: dts: vexpress: Move fixed devices out of bus node arm64: dts: fvp: Move fixed devices out of bus node arm64: dts: fvp/juno: Fix node address fields Link: https://lore.kernel.org/r/20200519094702.GA32975@bogus Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
564ef85341
@ -19,8 +19,162 @@
|
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*/
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||||
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/ {
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v2m_fixed_3v3: fixed-regulator-0 {
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compatible = "regulator-fixed";
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regulator-name = "3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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v2m_clk24mhz: clk24mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "v2m:clk24mhz";
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};
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v2m_refclk1mhz: refclk1mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <1000000>;
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clock-output-names = "v2m:refclk1mhz";
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};
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v2m_refclk32khz: refclk32khz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "v2m:refclk32khz";
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};
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leds {
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compatible = "gpio-leds";
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led-1 {
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label = "v2m:green:user1";
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gpios = <&v2m_led_gpios 0 0>;
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linux,default-trigger = "heartbeat";
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};
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led-2 {
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label = "v2m:green:user2";
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gpios = <&v2m_led_gpios 1 0>;
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linux,default-trigger = "disk-activity";
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};
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led-3 {
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label = "v2m:green:user3";
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gpios = <&v2m_led_gpios 2 0>;
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linux,default-trigger = "cpu0";
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};
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led-4 {
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label = "v2m:green:user4";
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gpios = <&v2m_led_gpios 3 0>;
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linux,default-trigger = "cpu1";
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};
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led-5 {
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label = "v2m:green:user5";
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gpios = <&v2m_led_gpios 4 0>;
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linux,default-trigger = "cpu2";
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};
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led-6 {
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label = "v2m:green:user6";
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gpios = <&v2m_led_gpios 5 0>;
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linux,default-trigger = "cpu3";
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};
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led-7 {
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label = "v2m:green:user7";
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gpios = <&v2m_led_gpios 6 0>;
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linux,default-trigger = "cpu4";
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};
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led-8 {
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label = "v2m:green:user8";
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gpios = <&v2m_led_gpios 7 0>;
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linux,default-trigger = "cpu5";
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};
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};
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mcc {
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compatible = "arm,vexpress,config-bus";
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arm,vexpress,config-bridge = <&v2m_sysreg>;
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oscclk0 {
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/* MCC static memory clock */
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 0>;
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freq-range = <25000000 60000000>;
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#clock-cells = <0>;
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clock-output-names = "v2m:oscclk0";
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};
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v2m_oscclk1: oscclk1 {
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/* CLCD clock */
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 1>;
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freq-range = <23750000 65000000>;
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#clock-cells = <0>;
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clock-output-names = "v2m:oscclk1";
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};
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v2m_oscclk2: oscclk2 {
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/* IO FPGA peripheral clock */
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 2>;
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freq-range = <24000000 24000000>;
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#clock-cells = <0>;
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clock-output-names = "v2m:oscclk2";
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};
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volt-vio {
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/* Logic level voltage */
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compatible = "arm,vexpress-volt";
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arm,vexpress-sysreg,func = <2 0>;
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regulator-name = "VIO";
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regulator-always-on;
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label = "VIO";
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};
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temp-mcc {
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/* MCC internal operating temperature */
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compatible = "arm,vexpress-temp";
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arm,vexpress-sysreg,func = <4 0>;
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label = "MCC";
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};
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reset {
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compatible = "arm,vexpress-reset";
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arm,vexpress-sysreg,func = <5 0>;
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};
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muxfpga {
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compatible = "arm,vexpress-muxfpga";
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arm,vexpress-sysreg,func = <7 0>;
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};
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shutdown {
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compatible = "arm,vexpress-shutdown";
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arm,vexpress-sysreg,func = <8 0>;
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};
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reboot {
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compatible = "arm,vexpress-reboot";
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arm,vexpress-sysreg,func = <9 0>;
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};
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dvimode {
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compatible = "arm,vexpress-dvimode";
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arm,vexpress-sysreg,func = <11 0>;
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};
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};
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bus@8000000 {
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motherboard {
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motherboard-bus {
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model = "V2M-P1";
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arm,hbi = <0x190>;
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arm,vexpress,site = <0>;
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@ -31,7 +185,7 @@
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#interrupt-cells = <1>;
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ranges;
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nor_flash: flash@0,00000000 {
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nor_flash: flash@0 {
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compatible = "arm,vexpress-flash", "cfi-flash";
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reg = <0 0x00000000 0x04000000>,
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<4 0x00000000 0x04000000>;
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@ -41,13 +195,13 @@
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};
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};
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psram@1,00000000 {
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psram@100000000 {
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compatible = "arm,vexpress-psram", "mtd-ram";
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reg = <1 0x00000000 0x02000000>;
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bank-width = <4>;
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};
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ethernet@2,02000000 {
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ethernet@202000000 {
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compatible = "smsc,lan9118", "smsc,lan9115";
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reg = <2 0x02000000 0x10000>;
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interrupts = <15>;
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@ -59,14 +213,14 @@
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vddvario-supply = <&v2m_fixed_3v3>;
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};
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usb@2,03000000 {
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usb@203000000 {
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compatible = "nxp,usb-isp1761";
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reg = <2 0x03000000 0x20000>;
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interrupts = <16>;
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port1-otg;
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};
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iofpga@3,00000000 {
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iofpga-bus@300000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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@ -162,7 +316,7 @@
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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v2m_serial0: uart@90000 {
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v2m_serial0: serial@90000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x090000 0x1000>;
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interrupts = <5>;
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@ -170,7 +324,7 @@
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clock-names = "uartclk", "apb_pclk";
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};
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v2m_serial1: uart@a0000 {
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v2m_serial1: serial@a0000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0a0000 0x1000>;
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interrupts = <6>;
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@ -178,7 +332,7 @@
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clock-names = "uartclk", "apb_pclk";
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};
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v2m_serial2: uart@b0000 {
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v2m_serial2: serial@b0000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0b0000 0x1000>;
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interrupts = <7>;
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@ -186,7 +340,7 @@
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clock-names = "uartclk", "apb_pclk";
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};
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v2m_serial3: uart@c0000 {
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v2m_serial3: serial@c0000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0c0000 0x1000>;
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interrupts = <8>;
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@ -282,160 +436,6 @@
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};
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};
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};
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v2m_fixed_3v3: fixed-regulator-0 {
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compatible = "regulator-fixed";
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regulator-name = "3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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v2m_clk24mhz: clk24mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "v2m:clk24mhz";
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};
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v2m_refclk1mhz: refclk1mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <1000000>;
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clock-output-names = "v2m:refclk1mhz";
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};
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v2m_refclk32khz: refclk32khz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "v2m:refclk32khz";
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};
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leds {
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compatible = "gpio-leds";
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user1 {
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label = "v2m:green:user1";
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gpios = <&v2m_led_gpios 0 0>;
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linux,default-trigger = "heartbeat";
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};
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user2 {
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label = "v2m:green:user2";
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gpios = <&v2m_led_gpios 1 0>;
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linux,default-trigger = "mmc0";
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};
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user3 {
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label = "v2m:green:user3";
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gpios = <&v2m_led_gpios 2 0>;
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linux,default-trigger = "cpu0";
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};
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user4 {
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label = "v2m:green:user4";
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gpios = <&v2m_led_gpios 3 0>;
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linux,default-trigger = "cpu1";
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};
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user5 {
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label = "v2m:green:user5";
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gpios = <&v2m_led_gpios 4 0>;
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linux,default-trigger = "cpu2";
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};
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user6 {
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label = "v2m:green:user6";
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gpios = <&v2m_led_gpios 5 0>;
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linux,default-trigger = "cpu3";
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||||
};
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user7 {
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label = "v2m:green:user7";
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gpios = <&v2m_led_gpios 6 0>;
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linux,default-trigger = "cpu4";
|
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};
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user8 {
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label = "v2m:green:user8";
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gpios = <&v2m_led_gpios 7 0>;
|
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linux,default-trigger = "cpu5";
|
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};
|
||||
};
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mcc {
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compatible = "arm,vexpress,config-bus";
|
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arm,vexpress,config-bridge = <&v2m_sysreg>;
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oscclk0 {
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/* MCC static memory clock */
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compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 0>;
|
||||
freq-range = <25000000 60000000>;
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#clock-cells = <0>;
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clock-output-names = "v2m:oscclk0";
|
||||
};
|
||||
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||||
v2m_oscclk1: oscclk1 {
|
||||
/* CLCD clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 1>;
|
||||
freq-range = <23750000 65000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "v2m:oscclk1";
|
||||
};
|
||||
|
||||
v2m_oscclk2: oscclk2 {
|
||||
/* IO FPGA peripheral clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 2>;
|
||||
freq-range = <24000000 24000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "v2m:oscclk2";
|
||||
};
|
||||
|
||||
volt-vio {
|
||||
/* Logic level voltage */
|
||||
compatible = "arm,vexpress-volt";
|
||||
arm,vexpress-sysreg,func = <2 0>;
|
||||
regulator-name = "VIO";
|
||||
regulator-always-on;
|
||||
label = "VIO";
|
||||
};
|
||||
|
||||
temp-mcc {
|
||||
/* MCC internal operating temperature */
|
||||
compatible = "arm,vexpress-temp";
|
||||
arm,vexpress-sysreg,func = <4 0>;
|
||||
label = "MCC";
|
||||
};
|
||||
|
||||
reset {
|
||||
compatible = "arm,vexpress-reset";
|
||||
arm,vexpress-sysreg,func = <5 0>;
|
||||
};
|
||||
|
||||
muxfpga {
|
||||
compatible = "arm,vexpress-muxfpga";
|
||||
arm,vexpress-sysreg,func = <7 0>;
|
||||
};
|
||||
|
||||
shutdown {
|
||||
compatible = "arm,vexpress-shutdown";
|
||||
arm,vexpress-sysreg,func = <8 0>;
|
||||
};
|
||||
|
||||
reboot {
|
||||
compatible = "arm,vexpress-reboot";
|
||||
arm,vexpress-sysreg,func = <9 0>;
|
||||
};
|
||||
|
||||
dvimode {
|
||||
compatible = "arm,vexpress-dvimode";
|
||||
arm,vexpress-sysreg,func = <11 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -6,9 +6,9 @@
|
||||
|
||||
/ {
|
||||
gic: interrupt-controller@2c001000 {
|
||||
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
|
||||
compatible = "arm,gic-400", "arm,cortex-a15-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <2>;
|
||||
#address-cells = <1>;
|
||||
interrupt-controller;
|
||||
reg = <0x0 0x2c001000 0 0x1000>,
|
||||
<0x0 0x2c002000 0 0x2000>,
|
||||
|
||||
@ -8,9 +8,9 @@
|
||||
gic: interrupt-controller@2f000000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x0 0x2f000000 0x100000>;
|
||||
interrupt-controller;
|
||||
reg = <0x0 0x2f000000 0x0 0x10000>,
|
||||
<0x0 0x2f100000 0x0 0x200000>,
|
||||
@ -19,10 +19,11 @@
|
||||
<0x0 0x2c02f000 0x0 0x2000>;
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
its: its@2f020000 {
|
||||
its: msi-controller@2f020000 {
|
||||
compatible = "arm,gic-v3-its";
|
||||
msi-controller;
|
||||
reg = <0x0 0x2f020000 0x0 0x20000>;
|
||||
#msi-cells = <1>;
|
||||
reg = <0x20000 0x20000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -92,6 +92,27 @@
|
||||
timeout-sec = <30>;
|
||||
};
|
||||
|
||||
v2m_clk24mhz: clk24mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "v2m:clk24mhz";
|
||||
};
|
||||
|
||||
v2m_refclk1mhz: refclk1mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <1000000>;
|
||||
clock-output-names = "v2m:refclk1mhz";
|
||||
};
|
||||
|
||||
v2m_refclk32khz: refclk32khz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "v2m:refclk32khz";
|
||||
};
|
||||
|
||||
bus@8000000 {
|
||||
compatible = "arm,vexpress,v2m-p1", "simple-bus";
|
||||
arm,v2m-memory-map = "rs1";
|
||||
@ -107,78 +128,57 @@
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 63>;
|
||||
interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 1 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 2 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 3 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 4 &gic 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 5 &gic 0 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 6 &gic 0 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 7 &gic 0 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 8 &gic 0 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 9 &gic 0 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 10 &gic 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 11 &gic 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 12 &gic 0 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 13 &gic 0 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 14 &gic 0 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 15 &gic 0 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 16 &gic 0 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 17 &gic 0 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 18 &gic 0 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 19 &gic 0 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 20 &gic 0 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 21 &gic 0 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 22 &gic 0 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 23 &gic 0 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 24 &gic 0 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 25 &gic 0 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 26 &gic 0 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 27 &gic 0 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 28 &gic 0 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 29 &gic 0 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 30 &gic 0 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 31 &gic 0 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 32 &gic 0 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 33 &gic 0 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 34 &gic 0 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 35 &gic 0 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 36 &gic 0 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 37 &gic 0 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 38 &gic 0 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 39 &gic 0 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 40 &gic 0 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 41 &gic 0 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 42 &gic 0 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-map = <0 0 0 &gic 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 1 &gic 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 2 &gic 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 3 &gic 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 4 &gic 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 5 &gic 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 6 &gic 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 7 &gic 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 8 &gic 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 9 &gic 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 10 &gic 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 11 &gic 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 12 &gic 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 13 &gic 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 14 &gic 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 15 &gic 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 16 &gic 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 17 &gic 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 18 &gic 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 19 &gic 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 20 &gic 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 21 &gic 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 22 &gic 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 23 &gic 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 24 &gic 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 25 &gic 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 26 &gic 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 27 &gic 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 28 &gic 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 29 &gic 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 30 &gic 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 31 &gic 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 32 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 33 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 34 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 35 &gic 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 36 &gic 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 37 &gic 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 38 &gic 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 39 &gic 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 40 &gic 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 41 &gic 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 42 &gic 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
ethernet@2,02000000 {
|
||||
ethernet@202000000 {
|
||||
compatible = "smsc,lan91c111";
|
||||
reg = <2 0x02000000 0x10000>;
|
||||
interrupts = <15>;
|
||||
};
|
||||
|
||||
v2m_clk24mhz: clk24mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "v2m:clk24mhz";
|
||||
};
|
||||
|
||||
v2m_refclk1mhz: refclk1mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <1000000>;
|
||||
clock-output-names = "v2m:refclk1mhz";
|
||||
};
|
||||
|
||||
v2m_refclk32khz: refclk32khz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "v2m:refclk32khz";
|
||||
};
|
||||
|
||||
iofpga@3,00000000 {
|
||||
iofpga-bus@300000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
@ -189,7 +189,7 @@
|
||||
reg = <0x010000 0x1000>;
|
||||
};
|
||||
|
||||
v2m_serial0: uart@90000 {
|
||||
v2m_serial0: serial@90000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x090000 0x1000>;
|
||||
interrupts = <5>;
|
||||
@ -197,7 +197,7 @@
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_serial1: uart@a0000 {
|
||||
v2m_serial1: serial@a0000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x0a0000 0x1000>;
|
||||
interrupts = <6>;
|
||||
@ -205,7 +205,7 @@
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_serial2: uart@b0000 {
|
||||
v2m_serial2: serial@b0000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x0b0000 0x1000>;
|
||||
interrupts = <7>;
|
||||
@ -213,7 +213,7 @@
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_serial3: uart@c0000 {
|
||||
v2m_serial3: serial@c0000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x0c0000 0x1000>;
|
||||
interrupts = <8>;
|
||||
|
||||
@ -126,7 +126,7 @@
|
||||
<0x0 0x2c02f000 0 0x2000>; // GICV
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
its: its@2f020000 {
|
||||
its: msi-controller@2f020000 {
|
||||
#msi-cells = <1>;
|
||||
compatible = "arm,gic-v3-its";
|
||||
reg = <0x0 0x2f020000 0x0 0x20000>; // GITS
|
||||
@ -172,14 +172,14 @@
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
smmu: smmu@2b400000 {
|
||||
smmu: iommu@2b400000 {
|
||||
compatible = "arm,smmu-v3";
|
||||
reg = <0x0 0x2b400000 0x0 0x100000>;
|
||||
interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 79 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";
|
||||
<GIC_SPI 77 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
|
||||
dma-coherent;
|
||||
#iommu-cells = <1>;
|
||||
msi-parent = <&its 0x10000>;
|
||||
|
||||
@ -11,14 +11,14 @@
|
||||
compatible = "arm,armv7-timer-mem";
|
||||
reg = <0x0 0x2a810000 0x0 0x10000>;
|
||||
clock-frequency = <50000000>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x0 0x2a820000 0x20000>;
|
||||
status = "disabled";
|
||||
frame@2a830000 {
|
||||
frame-number = <1>;
|
||||
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x0 0x2a830000 0x0 0x10000>;
|
||||
reg = <0x10000 0x10000>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -74,35 +74,35 @@
|
||||
<0x0 0x2c02f000 0 0x2000>,
|
||||
<0x0 0x2c04f000 0 0x2000>,
|
||||
<0x0 0x2c06f000 0 0x2000>;
|
||||
#address-cells = <2>;
|
||||
#address-cells = <1>;
|
||||
#interrupt-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
ranges = <0 0 0 0x2c1c0000 0 0x40000>;
|
||||
ranges = <0 0 0x2c1c0000 0x40000>;
|
||||
|
||||
v2m_0: v2m@0 {
|
||||
compatible = "arm,gic-v2m-frame";
|
||||
msi-controller;
|
||||
reg = <0 0 0 0x10000>;
|
||||
reg = <0 0x10000>;
|
||||
};
|
||||
|
||||
v2m@10000 {
|
||||
compatible = "arm,gic-v2m-frame";
|
||||
msi-controller;
|
||||
reg = <0 0x10000 0 0x10000>;
|
||||
reg = <0x10000 0x10000>;
|
||||
};
|
||||
|
||||
v2m@20000 {
|
||||
compatible = "arm,gic-v2m-frame";
|
||||
msi-controller;
|
||||
reg = <0 0x20000 0 0x10000>;
|
||||
reg = <0x20000 0x10000>;
|
||||
};
|
||||
|
||||
v2m@30000 {
|
||||
compatible = "arm,gic-v2m-frame";
|
||||
msi-controller;
|
||||
reg = <0 0x30000 0 0x10000>;
|
||||
reg = <0x30000 0x10000>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -501,10 +501,10 @@
|
||||
gpu: gpu@2d000000 {
|
||||
compatible = "arm,juno-mali", "arm,mali-t624";
|
||||
reg = <0 0x2d000000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "gpu", "job", "mmu";
|
||||
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "job", "mmu", "gpu";
|
||||
clocks = <&scpi_dvfs 2>;
|
||||
power-domains = <&scpi_devpd 1>;
|
||||
dma-coherent;
|
||||
@ -521,12 +521,12 @@
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x0 0x2e000000 0x8000>;
|
||||
|
||||
cpu_scp_lpri: scp-shmem@0 {
|
||||
cpu_scp_lpri: scp-sram@0 {
|
||||
compatible = "arm,juno-scp-shmem";
|
||||
reg = <0x0 0x200>;
|
||||
};
|
||||
|
||||
cpu_scp_hpri: scp-shmem@200 {
|
||||
cpu_scp_hpri: scp-sram@200 {
|
||||
compatible = "arm,juno-scp-shmem";
|
||||
reg = <0x200 0x200>;
|
||||
};
|
||||
@ -546,10 +546,10 @@
|
||||
<0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 2 &gic 0 0 GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 3 &gic 0 0 GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 4 &gic 0 0 GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-map = <0 0 0 1 &gic 0 GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 2 &gic 0 GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 3 &gic 0 GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 4 &gic 0 GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
|
||||
msi-parent = <&v2m_0>;
|
||||
status = "disabled";
|
||||
iommu-map-mask = <0x0>; /* RC has no means to output PCI RID */
|
||||
@ -729,7 +729,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
soc_uart0: uart@7ff80000 {
|
||||
soc_uart0: serial@7ff80000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x0 0x7ff80000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
@ -768,7 +768,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
ohci@7ffb0000 {
|
||||
usb@7ffb0000 {
|
||||
compatible = "generic-ohci";
|
||||
reg = <0x0 0x7ffb0000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
|
||||
@ -776,7 +776,7 @@
|
||||
clocks = <&soc_usb48mhz>;
|
||||
};
|
||||
|
||||
ehci@7ffc0000 {
|
||||
usb@7ffc0000 {
|
||||
compatible = "generic-ehci";
|
||||
reg = <0x0 0x7ffc0000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
||||
@ -813,28 +813,28 @@
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 15>;
|
||||
interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 1 &gic 0 0 GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 2 &gic 0 0 GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 3 &gic 0 0 GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 4 &gic 0 0 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 5 &gic 0 0 GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 6 &gic 0 0 GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 7 &gic 0 0 GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 8 &gic 0 0 GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 9 &gic 0 0 GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 10 &gic 0 0 GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 11 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 12 &gic 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-map = <0 0 0 &gic 0 GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 1 &gic 0 GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 2 &gic 0 GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 3 &gic 0 GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 4 &gic 0 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 5 &gic 0 GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 6 &gic 0 GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 7 &gic 0 GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 8 &gic 0 GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 9 &gic 0 GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 10 &gic 0 GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 11 &gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 12 &gic 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
site2: tlx@60000000 {
|
||||
site2: tlx-bus@60000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x60000000 0x10000000>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0>;
|
||||
interrupt-map = <0 0 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-map = <0 0 &gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -8,36 +8,91 @@
|
||||
*/
|
||||
|
||||
/ {
|
||||
mb_clk24mhz: clk24mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "juno_mb:clk24mhz";
|
||||
};
|
||||
|
||||
mb_clk25mhz: clk25mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <25000000>;
|
||||
clock-output-names = "juno_mb:clk25mhz";
|
||||
};
|
||||
|
||||
v2m_refclk1mhz: refclk1mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <1000000>;
|
||||
clock-output-names = "juno_mb:refclk1mhz";
|
||||
};
|
||||
|
||||
v2m_refclk32khz: refclk32khz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "juno_mb:refclk32khz";
|
||||
};
|
||||
|
||||
mb_fixed_3v3: mcc-sb-3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "MCC_SB_3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
power-button {
|
||||
debounce-interval = <50>;
|
||||
wakeup-source;
|
||||
linux,code = <116>;
|
||||
label = "POWER";
|
||||
gpios = <&iofpga_gpio0 0 0x4>;
|
||||
};
|
||||
home-button {
|
||||
debounce-interval = <50>;
|
||||
wakeup-source;
|
||||
linux,code = <102>;
|
||||
label = "HOME";
|
||||
gpios = <&iofpga_gpio0 1 0x4>;
|
||||
};
|
||||
rlock-button {
|
||||
debounce-interval = <50>;
|
||||
wakeup-source;
|
||||
linux,code = <152>;
|
||||
label = "RLOCK";
|
||||
gpios = <&iofpga_gpio0 2 0x4>;
|
||||
};
|
||||
vol-up-button {
|
||||
debounce-interval = <50>;
|
||||
wakeup-source;
|
||||
linux,code = <115>;
|
||||
label = "VOL+";
|
||||
gpios = <&iofpga_gpio0 3 0x4>;
|
||||
};
|
||||
vol-down-button {
|
||||
debounce-interval = <50>;
|
||||
wakeup-source;
|
||||
linux,code = <114>;
|
||||
label = "VOL-";
|
||||
gpios = <&iofpga_gpio0 4 0x4>;
|
||||
};
|
||||
nmi-button {
|
||||
debounce-interval = <50>;
|
||||
wakeup-source;
|
||||
linux,code = <99>;
|
||||
label = "NMI";
|
||||
gpios = <&iofpga_gpio0 5 0x4>;
|
||||
};
|
||||
};
|
||||
|
||||
bus@8000000 {
|
||||
mb_clk24mhz: clk24mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "juno_mb:clk24mhz";
|
||||
};
|
||||
|
||||
mb_clk25mhz: clk25mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <25000000>;
|
||||
clock-output-names = "juno_mb:clk25mhz";
|
||||
};
|
||||
|
||||
v2m_refclk1mhz: refclk1mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <1000000>;
|
||||
clock-output-names = "juno_mb:refclk1mhz";
|
||||
};
|
||||
|
||||
v2m_refclk32khz: refclk32khz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "juno_mb:refclk32khz";
|
||||
};
|
||||
|
||||
motherboard {
|
||||
motherboard-bus {
|
||||
compatible = "arm,vexpress,v2p-p1", "simple-bus";
|
||||
#address-cells = <2>; /* SMB chipselect number and offset */
|
||||
#size-cells = <1>;
|
||||
@ -48,62 +103,7 @@
|
||||
arm,vexpress,site = <0>;
|
||||
arm,v2m-memory-map = "rs1";
|
||||
|
||||
mb_fixed_3v3: mcc-sb-3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "MCC_SB_3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
power-button {
|
||||
debounce-interval = <50>;
|
||||
wakeup-source;
|
||||
linux,code = <116>;
|
||||
label = "POWER";
|
||||
gpios = <&iofpga_gpio0 0 0x4>;
|
||||
};
|
||||
home-button {
|
||||
debounce-interval = <50>;
|
||||
wakeup-source;
|
||||
linux,code = <102>;
|
||||
label = "HOME";
|
||||
gpios = <&iofpga_gpio0 1 0x4>;
|
||||
};
|
||||
rlock-button {
|
||||
debounce-interval = <50>;
|
||||
wakeup-source;
|
||||
linux,code = <152>;
|
||||
label = "RLOCK";
|
||||
gpios = <&iofpga_gpio0 2 0x4>;
|
||||
};
|
||||
vol-up-button {
|
||||
debounce-interval = <50>;
|
||||
wakeup-source;
|
||||
linux,code = <115>;
|
||||
label = "VOL+";
|
||||
gpios = <&iofpga_gpio0 3 0x4>;
|
||||
};
|
||||
vol-down-button {
|
||||
debounce-interval = <50>;
|
||||
wakeup-source;
|
||||
linux,code = <114>;
|
||||
label = "VOL-";
|
||||
gpios = <&iofpga_gpio0 4 0x4>;
|
||||
};
|
||||
nmi-button {
|
||||
debounce-interval = <50>;
|
||||
wakeup-source;
|
||||
linux,code = <99>;
|
||||
label = "NMI";
|
||||
gpios = <&iofpga_gpio0 5 0x4>;
|
||||
};
|
||||
};
|
||||
|
||||
flash@0,00000000 {
|
||||
flash@0 {
|
||||
/* 2 * 32MiB NOR Flash memory mounted on CS0 */
|
||||
compatible = "arm,vexpress-flash", "cfi-flash";
|
||||
reg = <0 0x00000000 0x04000000>;
|
||||
@ -120,7 +120,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
ethernet@2,00000000 {
|
||||
ethernet@200000000 {
|
||||
compatible = "smsc,lan9118", "smsc,lan9115";
|
||||
reg = <2 0x00000000 0x10000>;
|
||||
interrupts = <3>;
|
||||
@ -133,7 +133,7 @@
|
||||
vddvario-supply = <&mb_fixed_3v3>;
|
||||
};
|
||||
|
||||
iofpga@3,00000000 {
|
||||
iofpga-bus@300000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
@ -95,7 +95,7 @@
|
||||
};
|
||||
|
||||
gic: interrupt-controller@2c001000 {
|
||||
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
|
||||
compatible = "arm,gic-400", "arm,cortex-a15-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
|
||||
@ -6,10 +6,10 @@
|
||||
*/
|
||||
/ {
|
||||
bus@8000000 {
|
||||
motherboard {
|
||||
motherboard-bus {
|
||||
arm,v2m-memory-map = "rs2";
|
||||
|
||||
iofpga@3,00000000 {
|
||||
iofpga-bus@300000000 {
|
||||
virtio-p9@140000 {
|
||||
compatible = "virtio,mmio";
|
||||
reg = <0x140000 0x200>;
|
||||
|
||||
@ -8,8 +8,76 @@
|
||||
* VEMotherBoard.lisa
|
||||
*/
|
||||
/ {
|
||||
v2m_clk24mhz: clk24mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "v2m:clk24mhz";
|
||||
};
|
||||
|
||||
v2m_refclk1mhz: refclk1mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <1000000>;
|
||||
clock-output-names = "v2m:refclk1mhz";
|
||||
};
|
||||
|
||||
v2m_refclk32khz: refclk32khz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "v2m:refclk32khz";
|
||||
};
|
||||
|
||||
v2m_fixed_3v3: v2m-3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
mcc {
|
||||
compatible = "arm,vexpress,config-bus";
|
||||
arm,vexpress,config-bridge = <&v2m_sysreg>;
|
||||
|
||||
v2m_oscclk1: oscclk1 {
|
||||
/* CLCD clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 1>;
|
||||
freq-range = <23750000 63500000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "v2m:oscclk1";
|
||||
};
|
||||
|
||||
reset {
|
||||
compatible = "arm,vexpress-reset";
|
||||
arm,vexpress-sysreg,func = <5 0>;
|
||||
};
|
||||
|
||||
muxfpga {
|
||||
compatible = "arm,vexpress-muxfpga";
|
||||
arm,vexpress-sysreg,func = <7 0>;
|
||||
};
|
||||
|
||||
shutdown {
|
||||
compatible = "arm,vexpress-shutdown";
|
||||
arm,vexpress-sysreg,func = <8 0>;
|
||||
};
|
||||
|
||||
reboot {
|
||||
compatible = "arm,vexpress-reboot";
|
||||
arm,vexpress-sysreg,func = <9 0>;
|
||||
};
|
||||
|
||||
dvimode {
|
||||
compatible = "arm,vexpress-dvimode";
|
||||
arm,vexpress-sysreg,func = <11 0>;
|
||||
};
|
||||
};
|
||||
|
||||
bus@8000000 {
|
||||
motherboard {
|
||||
motherboard-bus {
|
||||
arm,v2m-memory-map = "rs1";
|
||||
compatible = "arm,vexpress,v2m-p1", "simple-bus";
|
||||
#address-cells = <2>; /* SMB chipselect number and offset */
|
||||
@ -17,41 +85,20 @@
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
|
||||
flash@0,00000000 {
|
||||
flash@0 {
|
||||
compatible = "arm,vexpress-flash", "cfi-flash";
|
||||
reg = <0 0x00000000 0x04000000>,
|
||||
<4 0x00000000 0x04000000>;
|
||||
bank-width = <4>;
|
||||
};
|
||||
|
||||
ethernet@2,02000000 {
|
||||
ethernet@202000000 {
|
||||
compatible = "smsc,lan91c111";
|
||||
reg = <2 0x02000000 0x10000>;
|
||||
interrupts = <15>;
|
||||
};
|
||||
|
||||
v2m_clk24mhz: clk24mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "v2m:clk24mhz";
|
||||
};
|
||||
|
||||
v2m_refclk1mhz: refclk1mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <1000000>;
|
||||
clock-output-names = "v2m:refclk1mhz";
|
||||
};
|
||||
|
||||
v2m_refclk32khz: refclk32khz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "v2m:refclk32khz";
|
||||
};
|
||||
|
||||
iofpga@3,00000000 {
|
||||
iofpga-bus@300000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
@ -111,7 +158,7 @@
|
||||
clock-names = "KMIREFCLK", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_serial0: uart@90000 {
|
||||
v2m_serial0: serial@90000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x090000 0x1000>;
|
||||
interrupts = <5>;
|
||||
@ -119,7 +166,7 @@
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_serial1: uart@a0000 {
|
||||
v2m_serial1: serial@a0000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x0a0000 0x1000>;
|
||||
interrupts = <6>;
|
||||
@ -127,7 +174,7 @@
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_serial2: uart@b0000 {
|
||||
v2m_serial2: serial@b0000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x0b0000 0x1000>;
|
||||
interrupts = <7>;
|
||||
@ -135,7 +182,7 @@
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_serial3: uart@c0000 {
|
||||
v2m_serial3: serial@c0000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x0c0000 0x1000>;
|
||||
interrupts = <8>;
|
||||
@ -198,53 +245,6 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
v2m_fixed_3v3: v2m-3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
mcc {
|
||||
compatible = "arm,vexpress,config-bus";
|
||||
arm,vexpress,config-bridge = <&v2m_sysreg>;
|
||||
|
||||
v2m_oscclk1: oscclk1 {
|
||||
/* CLCD clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 1>;
|
||||
freq-range = <23750000 63500000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "v2m:oscclk1";
|
||||
};
|
||||
|
||||
reset {
|
||||
compatible = "arm,vexpress-reset";
|
||||
arm,vexpress-sysreg,func = <5 0>;
|
||||
};
|
||||
|
||||
muxfpga {
|
||||
compatible = "arm,vexpress-muxfpga";
|
||||
arm,vexpress-sysreg,func = <7 0>;
|
||||
};
|
||||
|
||||
shutdown {
|
||||
compatible = "arm,vexpress-shutdown";
|
||||
arm,vexpress-sysreg,func = <8 0>;
|
||||
};
|
||||
|
||||
reboot {
|
||||
compatible = "arm,vexpress-reboot";
|
||||
arm,vexpress-sysreg,func = <9 0>;
|
||||
};
|
||||
|
||||
dvimode {
|
||||
compatible = "arm,vexpress-dvimode";
|
||||
arm,vexpress-sysreg,func = <11 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
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