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mmc: dw_mmc: Reset DMA before enabling IDMAC
We've already got a reset of DMA after it's done. Add one before we start DMA too. This fixes a data corruption on Rockchip SoCs which will get bad data when doing a DMA transfer after doing a PIO transfer. We tested this on an Exynos 5800 with HS200 and didn't notice any difference in sequential read throughput. Signed-off-by: Sonny Rao <sonnyrao@chromium.org> Signed-off-by: Doug Anderson <dianders@chromium.org> Tested-by: Doug Anderson <dianders@chromium.org> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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@ -83,6 +83,7 @@ struct idmac_desc {
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#endif /* CONFIG_MMC_DW_IDMAC */
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static bool dw_mci_reset(struct dw_mci *host);
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static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
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#if defined(CONFIG_DEBUG_FS)
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static int dw_mci_req_show(struct seq_file *s, void *v)
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@ -448,6 +449,10 @@ static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
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dw_mci_translate_sglist(host, host->data, sg_len);
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/* Make sure to reset DMA in case we did PIO before this */
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dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
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dw_mci_idmac_reset(host);
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/* Select IDMAC interface */
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temp = mci_readl(host, CTRL);
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temp |= SDMMC_CTRL_USE_IDMAC;
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