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drm/i915 fixes for v5.6-rc7:
- Track active elements during dequeue - Fix failure to handle all MCR ranges - Revert unnecessary workaround -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEFWWmW3ewYy4RJOWc05gHnSar7m8FAl5zJl4ACgkQ05gHnSar 7m+wJhAAreffDNdNJQ7aNspMJiysrSaknCGQGdFtgih0qb3f9t/A7VccpHBNN2GB d5CKrBE72PWQT6r4PYux56Fg1mj0wq8ajkvyqvVImkG2NWGWN6hl2Vo7vwGBa35Z INSCSKSMOfQfWzJGhl5SAp8ieF12gFTB251THFQ/4lt0DlMlYDfq48UxXyr7TdXs 1Cmrgch4zDzntqMXvCrSkX3WjoPrWXqpHJFIO3AuQ6+EA14Zb4TVB7VetbpKqm26 4TUtKPjDYaNQ2JHE9KW82vq4P1Hw55fuP0P4umL4l2M5NXkbGkWGCQiOaoaKfzM9 u6JRhSGtg5ho4Hj05L2ai7082tH2ME1/o4nC2Wi2DHR8FW6QnMl3XC6oSmK3lpDx 3P72D1jxW15lFpmarT/BTP9C4Puk8iyDtdkf6XRtFy2SkfEtfG8qBlBuXEcK8sz7 LEJbJDbBr1CAWSqVkQfno1hQWdRY4847OeksVgLgAufI4bhPNxQNrZvENv1IdOwx 78tf+y0L1dlArvYuCzNjTNotedsJcDBCgqIeMsBUYvlw7mJuWnWScU5eK7YRFviK AxZ0ZLxCyj9mBZp1S9Y20awjUTjjR6O1TMVmpFWYoK7UZm97CfoIAkV5Fl1Bm1CT epssLTY7Bbp7NdGY5bcEMRmslJj94Wm13VCtL+h7jY6rjE8h7IU= =ELTv -----END PGP SIGNATURE----- Merge tag 'drm-intel-fixes-2020-03-19' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes drm/i915 fixes for v5.6-rc7: - Track active elements during dequeue - Fix failure to handle all MCR ranges - Revert unnecessary workaround Signed-off-by: Dave Airlie <airlied@redhat.com> From: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/877dzgepvu.fsf@intel.com
This commit is contained in:
Dave Airlie
commit
5366b96b19
@ -1600,17 +1600,6 @@ static void virtual_xfer_breadcrumbs(struct virtual_engine *ve,
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spin_unlock(&old->breadcrumbs.irq_lock);
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}
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static struct i915_request *
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last_active(const struct intel_engine_execlists *execlists)
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{
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struct i915_request * const *last = READ_ONCE(execlists->active);
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while (*last && i915_request_completed(*last))
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last++;
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return *last;
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}
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#define for_each_waiter(p__, rq__) \
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list_for_each_entry_lockless(p__, \
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&(rq__)->sched.waiters_list, \
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@ -1740,11 +1729,9 @@ static void record_preemption(struct intel_engine_execlists *execlists)
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(void)I915_SELFTEST_ONLY(execlists->preempt_hang.count++);
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}
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static unsigned long active_preempt_timeout(struct intel_engine_cs *engine)
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static unsigned long active_preempt_timeout(struct intel_engine_cs *engine,
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const struct i915_request *rq)
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{
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struct i915_request *rq;
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rq = last_active(&engine->execlists);
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if (!rq)
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return 0;
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@ -1755,13 +1742,14 @@ static unsigned long active_preempt_timeout(struct intel_engine_cs *engine)
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return READ_ONCE(engine->props.preempt_timeout_ms);
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}
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static void set_preempt_timeout(struct intel_engine_cs *engine)
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static void set_preempt_timeout(struct intel_engine_cs *engine,
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const struct i915_request *rq)
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{
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if (!intel_engine_has_preempt_reset(engine))
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return;
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set_timer_ms(&engine->execlists.preempt,
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active_preempt_timeout(engine));
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active_preempt_timeout(engine, rq));
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}
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static inline void clear_ports(struct i915_request **ports, int count)
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@ -1774,6 +1762,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
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struct intel_engine_execlists * const execlists = &engine->execlists;
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struct i915_request **port = execlists->pending;
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struct i915_request ** const last_port = port + execlists->port_mask;
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struct i915_request * const *active;
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struct i915_request *last;
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struct rb_node *rb;
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bool submit = false;
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@ -1828,7 +1817,10 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
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* i.e. we will retrigger preemption following the ack in case
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* of trouble.
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*/
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last = last_active(execlists);
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active = READ_ONCE(execlists->active);
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while ((last = *active) && i915_request_completed(last))
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active++;
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if (last) {
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if (need_preempt(engine, last, rb)) {
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ENGINE_TRACE(engine,
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@ -2110,7 +2102,7 @@ done:
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* Skip if we ended up with exactly the same set of requests,
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* e.g. trying to timeslice a pair of ordered contexts
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*/
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if (!memcmp(execlists->active, execlists->pending,
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if (!memcmp(active, execlists->pending,
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(port - execlists->pending + 1) * sizeof(*port))) {
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do
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execlists_schedule_out(fetch_and_zero(port));
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@ -2121,7 +2113,7 @@ done:
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clear_ports(port + 1, last_port - port);
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execlists_submit_ports(engine);
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set_preempt_timeout(engine);
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set_preempt_timeout(engine, *active);
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} else {
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skip_submit:
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ring_set_paused(engine, 0);
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@ -4008,26 +4000,6 @@ static int gen12_emit_flush_render(struct i915_request *request,
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*cs++ = preparser_disable(false);
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intel_ring_advance(request, cs);
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/*
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* Wa_1604544889:tgl
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*/
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if (IS_TGL_REVID(request->i915, TGL_REVID_A0, TGL_REVID_A0)) {
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flags = 0;
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flags |= PIPE_CONTROL_CS_STALL;
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flags |= PIPE_CONTROL_HDC_PIPELINE_FLUSH;
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flags |= PIPE_CONTROL_STORE_DATA_INDEX;
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flags |= PIPE_CONTROL_QW_WRITE;
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cs = intel_ring_begin(request, 6);
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if (IS_ERR(cs))
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return PTR_ERR(cs);
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cs = gen8_emit_pipe_control(cs, flags,
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LRC_PPHWSP_SCRATCH_ADDR);
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intel_ring_advance(request, cs);
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}
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}
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return 0;
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@ -1529,15 +1529,34 @@ err_obj:
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return ERR_PTR(err);
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}
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static const struct {
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u32 start;
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u32 end;
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} mcr_ranges_gen8[] = {
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{ .start = 0x5500, .end = 0x55ff },
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{ .start = 0x7000, .end = 0x7fff },
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{ .start = 0x9400, .end = 0x97ff },
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{ .start = 0xb000, .end = 0xb3ff },
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{ .start = 0xe000, .end = 0xe7ff },
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{},
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};
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static bool mcr_range(struct drm_i915_private *i915, u32 offset)
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{
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int i;
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if (INTEL_GEN(i915) < 8)
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return false;
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/*
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* Registers in this range are affected by the MCR selector
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* Registers in these ranges are affected by the MCR selector
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* which only controls CPU initiated MMIO. Routing does not
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* work for CS access so we cannot verify them on this path.
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*/
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if (INTEL_GEN(i915) >= 8 && (offset >= 0xb000 && offset <= 0xb4ff))
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return true;
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for (i = 0; mcr_ranges_gen8[i].start; i++)
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if (offset >= mcr_ranges_gen8[i].start &&
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offset <= mcr_ranges_gen8[i].end)
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return true;
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return false;
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}
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