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ARM: MX3: fix CPU revision number detection

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The macro mx31_revision() used to take the global variable system_rev to
determine the CPU revision number. However, this number is expected to
be set by the bootloader and is usually zero (at least on my MX31 based
boards here). More than that, it is usually taken to identify the
board's revision, not the CPU's.

Fix that by reading the the CPU's SREV register instead.

Right now, mx31_read_cpu_rev() is called from mx31_clocks_init() which
is admittedly not a good place for it. However, we need to enable the
IIM clock first, and the clock code also has conditional code that
depends on mx31_revision() returning the right thing.

Signed-off-by: Daniel Mack <daniel@caiaq.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Daniel Mack 2009-11-21 20:17:18 +01:00 committed by Sascha Hauer
parent 2cc326833f
commit 52939c03e5
4 changed files with 63 additions and 3 deletions
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2
arch/arm/mach-mx3/Makefile
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@ -4,7 +4,7 @@
# Object file lists.
obj-y := mm.o devices.o
obj-y := mm.o devices.o cpu.o
obj-$(CONFIG_ARCH_MX31) += clock.o iomux.o
obj-$(CONFIG_ARCH_MX35) += clock-imx35.o
obj-$(CONFIG_MACH_MX31ADS) += mx31ads.o

2
arch/arm/mach-mx3/clock.c
View File

@ -616,6 +616,8 @@ int __init mx31_clocks_init(unsigned long fref)
clk_enable(&serial_pll_clk);
mx31_read_cpu_rev();
if (mx31_revision() >= CHIP_REV_2_0) {
reg = __raw_readl(MXC_CCM_PMCR1);
/* No PLL restart on DVFS switch; enable auto EMI handshake */

57
arch/arm/mach-mx3/cpu.c Normal file
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@ -0,0 +1,57 @@
/*
* MX3 CPU type detection
*
* Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/module.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <mach/iim.h>
unsigned int mx31_cpu_rev;
EXPORT_SYMBOL(mx31_cpu_rev);
struct mx3_cpu_type {
u8 srev;
const char *name;
const char *v;
unsigned int rev;
};
static struct mx3_cpu_type mx31_cpu_type[] __initdata = {
{ .srev = 0x00, .name = "i.MX31(L)", .v = "1.0", .rev = CHIP_REV_1_0 },
{ .srev = 0x10, .name = "i.MX31", .v = "1.1", .rev = CHIP_REV_1_1 },
{ .srev = 0x11, .name = "i.MX31L", .v = "1.1", .rev = CHIP_REV_1_1 },
{ .srev = 0x12, .name = "i.MX31", .v = "1.15", .rev = CHIP_REV_1_1 },
{ .srev = 0x13, .name = "i.MX31L", .v = "1.15", .rev = CHIP_REV_1_1 },
{ .srev = 0x14, .name = "i.MX31", .v = "1.2", .rev = CHIP_REV_1_2 },
{ .srev = 0x15, .name = "i.MX31L", .v = "1.2", .rev = CHIP_REV_1_2 },
{ .srev = 0x28, .name = "i.MX31", .v = "2.0", .rev = CHIP_REV_2_0 },
{ .srev = 0x29, .name = "i.MX31L", .v = "2.0", .rev = CHIP_REV_2_0 },
};
void __init mx31_read_cpu_rev(void)
{
u32 i, srev;
/* read SREV register from IIM module */
srev = __raw_readl(IO_ADDRESS(IIM_BASE_ADDR) + MXC_IIMSREV);
for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
if (srev == mx31_cpu_type[i].srev) {
printk(KERN_INFO
"CPU identified as %s, silicon rev %s\n",
mx31_cpu_type[i].name, mx31_cpu_type[i].v);
mx31_cpu_rev = mx31_cpu_type[i].rev;
return;
}
printk(KERN_WARNING "Unknown CPU identifier. srev = %02x\n", srev);
}

5
arch/arm/plat-mxc/include/mach/mx3x.h
View File

@ -260,11 +260,12 @@
#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
extern unsigned int system_rev;
extern unsigned int mx31_cpu_rev;
extern void mx31_read_cpu_rev(void);
static inline int mx31_revision(void)
{
return system_rev;
return mx31_cpu_rev;
}
#endif