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soc / drm: mediatek: Move DDP component defines into mtk-mmsys.h
MMSYS is the driver which controls the routing of these DDP components, so the definition of the mtk_ddp_comp_id enum should be placed in mtk-mmsys.h Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Link: https://lore.kernel.org/r/20201006193320.405529-2-enric.balletbo@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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@ -7,6 +7,7 @@
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#define MTK_DRM_DDP_COMP_H
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#define MTK_DRM_DDP_COMP_H
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#include <linux/io.h>
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#include <linux/io.h>
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#include <linux/soc/mediatek/mtk-mmsys.h>
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struct device;
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struct device;
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struct device_node;
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struct device_node;
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@ -35,39 +36,6 @@ enum mtk_ddp_comp_type {
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MTK_DDP_COMP_TYPE_MAX,
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MTK_DDP_COMP_TYPE_MAX,
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};
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};
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enum mtk_ddp_comp_id {
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DDP_COMPONENT_AAL0,
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DDP_COMPONENT_AAL1,
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DDP_COMPONENT_BLS,
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DDP_COMPONENT_CCORR,
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DDP_COMPONENT_COLOR0,
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DDP_COMPONENT_COLOR1,
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DDP_COMPONENT_DITHER,
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DDP_COMPONENT_DPI0,
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DDP_COMPONENT_DPI1,
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DDP_COMPONENT_DSI0,
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DDP_COMPONENT_DSI1,
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DDP_COMPONENT_DSI2,
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DDP_COMPONENT_DSI3,
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DDP_COMPONENT_GAMMA,
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DDP_COMPONENT_OD0,
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DDP_COMPONENT_OD1,
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DDP_COMPONENT_OVL0,
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DDP_COMPONENT_OVL_2L0,
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DDP_COMPONENT_OVL_2L1,
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DDP_COMPONENT_OVL1,
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DDP_COMPONENT_PWM0,
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DDP_COMPONENT_PWM1,
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DDP_COMPONENT_PWM2,
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DDP_COMPONENT_RDMA0,
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DDP_COMPONENT_RDMA1,
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DDP_COMPONENT_RDMA2,
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DDP_COMPONENT_UFOE,
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DDP_COMPONENT_WDMA0,
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DDP_COMPONENT_WDMA1,
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DDP_COMPONENT_ID_MAX,
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};
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struct mtk_ddp_comp;
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struct mtk_ddp_comp;
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struct cmdq_pkt;
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struct cmdq_pkt;
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struct mtk_ddp_comp_funcs {
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struct mtk_ddp_comp_funcs {
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@ -5,13 +5,11 @@
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*/
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*/
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#include <linux/device.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/of_device.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/platform_device.h>
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#include <linux/soc/mediatek/mtk-mmsys.h>
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#include <linux/soc/mediatek/mtk-mmsys.h>
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#include "../../gpu/drm/mediatek/mtk_drm_ddp.h"
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#include "../../gpu/drm/mediatek/mtk_drm_ddp_comp.h"
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#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
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#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
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#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044
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#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044
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#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048
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#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048
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@ -9,6 +9,39 @@
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enum mtk_ddp_comp_id;
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enum mtk_ddp_comp_id;
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struct device;
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struct device;
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enum mtk_ddp_comp_id {
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DDP_COMPONENT_AAL0,
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DDP_COMPONENT_AAL1,
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DDP_COMPONENT_BLS,
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DDP_COMPONENT_CCORR,
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DDP_COMPONENT_COLOR0,
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DDP_COMPONENT_COLOR1,
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DDP_COMPONENT_DITHER,
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DDP_COMPONENT_DPI0,
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DDP_COMPONENT_DPI1,
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DDP_COMPONENT_DSI0,
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DDP_COMPONENT_DSI1,
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DDP_COMPONENT_DSI2,
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DDP_COMPONENT_DSI3,
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DDP_COMPONENT_GAMMA,
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DDP_COMPONENT_OD0,
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DDP_COMPONENT_OD1,
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DDP_COMPONENT_OVL0,
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DDP_COMPONENT_OVL_2L0,
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DDP_COMPONENT_OVL_2L1,
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DDP_COMPONENT_OVL1,
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DDP_COMPONENT_PWM0,
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DDP_COMPONENT_PWM1,
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DDP_COMPONENT_PWM2,
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DDP_COMPONENT_RDMA0,
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DDP_COMPONENT_RDMA1,
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DDP_COMPONENT_RDMA2,
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DDP_COMPONENT_UFOE,
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DDP_COMPONENT_WDMA0,
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DDP_COMPONENT_WDMA1,
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DDP_COMPONENT_ID_MAX,
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};
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void mtk_mmsys_ddp_connect(struct device *dev,
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void mtk_mmsys_ddp_connect(struct device *dev,
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enum mtk_ddp_comp_id cur,
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enum mtk_ddp_comp_id cur,
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enum mtk_ddp_comp_id next);
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enum mtk_ddp_comp_id next);
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