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media: staging: atomisp: Remove driver

Browse Source 
The atomisp driver has a long list of todo items and little has been done
to address these lately while more has been added. The driver is also not
functional. In other words, the driver would not be getting out of staging
in the foreseeable future. At the same time it consumes developer
resources in order to maintain the flaky code base. Remove it.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
This commit is contained in:
Sakari Ailus 2018-05-09 17:34:45 +03:00 committed by Mauro Carvalho Chehab
parent 6522aa1b19
commit 51b8dc5163
767 changed files with 0 additions and 168056 deletions
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7
MAINTAINERS
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@ -13272,13 +13272,6 @@ L: stable@vger.kernel.org
S: Supported
F: Documentation/process/stable-kernel-rules.rst
STAGING - ATOMISP DRIVER
M: Alan Cox <alan@linux.intel.com>
M: Sakari Ailus <sakari.ailus@linux.intel.com>
L: linux-media@vger.kernel.org
S: Maintained
F: drivers/staging/media/atomisp/
STAGING - COMEDI
M: Ian Abbott <abbotti@mev.co.uk>
M: H Hartley Sweeten <hsweeten@visionengravers.com>

2
drivers/staging/media/Kconfig
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@ -19,8 +19,6 @@ menuconfig STAGING_MEDIA
if STAGING_MEDIA && MEDIA_SUPPORT
# Please keep them in alphabetic order
source "drivers/staging/media/atomisp/Kconfig"
source "drivers/staging/media/bcm2048/Kconfig"
source "drivers/staging/media/davinci_vpfe/Kconfig"

1
drivers/staging/media/Makefile
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@ -5,5 +5,4 @@ obj-$(CONFIG_SOC_CAMERA_IMX074) += imx074/
obj-$(CONFIG_SOC_CAMERA_MT9T031) += mt9t031/
obj-$(CONFIG_VIDEO_DM365_VPFE) += davinci_vpfe/
obj-$(CONFIG_VIDEO_OMAP4) += omap4iss/
obj-$(CONFIG_INTEL_ATOMISP) += atomisp/
obj-$(CONFIG_TEGRA_VDE) += tegra-vde/

12
drivers/staging/media/atomisp/Kconfig
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@ -1,12 +0,0 @@
menuconfig INTEL_ATOMISP
bool "Enable support to Intel MIPI camera drivers"
depends on X86 && EFI && MEDIA_CONTROLLER && PCI && ACPI
select COMMON_CLK
help
Enable support for the Intel ISP2 camera interfaces and MIPI
sensor drivers.
if INTEL_ATOMISP
source "drivers/staging/media/atomisp/pci/Kconfig"
source "drivers/staging/media/atomisp/i2c/Kconfig"
endif

6
drivers/staging/media/atomisp/Makefile
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@ -1,6 +0,0 @@
#
# Makefile for camera drivers.
#
obj-$(CONFIG_INTEL_ATOMISP) += pci/
obj-$(CONFIG_INTEL_ATOMISP) += i2c/
obj-$(CONFIG_INTEL_ATOMISP) += platform/

74
drivers/staging/media/atomisp/TODO
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@ -1,74 +0,0 @@
1. A single AtomISP driver needs to be implemented to support both BYT and
CHT platforms. The current driver is a mechanical and hand combined merge
of the two using an ifdef ISP2401 to select the CHT version, which at the
moment is not enabled. Eventually this should become a runtime if check,
but there are some quite tricky things that need sorting out before that
will be possible.
2. The file structure needs to get tidied up to resemble a normal Linux
driver.
3. Lots of the midlayer glue. unused code and abstraction needs removing.
3. The sensor drivers read MIPI settings from EFI variables or default to the
settings hard-coded in the platform data file for different platforms.
This isn't ideal but may be hard to improve as this is how existing
platforms work.
4. The sensor drivers use the regulator framework API. In the ideal world it
would be using ACPI but that's not how the existing devices work.
5. The AtomISP driver includes some special IOCTLS (ATOMISP_IOC_XXXX_XXXX)
that may need some cleaning up.
6. Correct Coding Style. Please don't send coding style patches for this
driver until the other work is done.
7. The ISP code depends on the exact FW version. The version defined in
BYT:
drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_firmware.c
static const char *release_version = STR(irci_stable_candrpv_0415_20150521_0458);
CHT:
drivers/staging/media/atomisp/pci/atomisp2/css/sh_css_firmware.c
static const char *release_version = STR(irci_ecr-master_20150911_0724);
At some point we may need to round up a few driver versions and see if
there are any specific things that can be done to fold in support for
multiple firmware versions.
8. Switch to V4L2 async API to set up sensor, lens and flash devices.
Control those devices using V4L2 sub-device API without custom
extensions.
9. Switch to standard V4L2 sub-device API for sensor and lens. In
particular, the user space API needs to support V4L2 controls as
defined in the V4L2 spec and references to atomisp must be removed from
these drivers.
10. Use LED flash API for flash LED drivers such as LM3554 (which already
has a LED class driver).
11. Switch from videobuf1 to videobuf2. Videobuf1 is being removed!
Limitations:
1. To test the patches, you also need the ISP firmware
for BYT:/lib/firmware/shisp_2400b0_v21.bin
for CHT:/lib/firmware/shisp_2401a0_v21.bin
The firmware files will usually be found in /etc/firmware on an Android
device but can also be extracted from the upgrade kit if you've managed
to lose them somehow.
2. Without a 3A libary the capture behaviour is not very good. To take a good
picture, you need tune ISP parameters by IOCTL functions or use a 3A libary
such as libxcam.
3. The driver is intended to drive the PCI exposed versions of the device.
It will not detect those devices enumerated via ACPI as a field of the
i915 GPU driver.
4. The driver supports only v2 of the IPU/Camera. It will not work with the
versions of the hardware in other SoCs.

86
drivers/staging/media/atomisp/i2c/Kconfig
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@ -1,86 +0,0 @@
#
# Kconfig for sensor drivers
#
source "drivers/staging/media/atomisp/i2c/ov5693/Kconfig"
config VIDEO_ATOMISP_OV2722
tristate "OVT ov2722 sensor support"
depends on ACPI
depends on I2C && VIDEO_V4L2
---help---
This is a Video4Linux2 sensor-level driver for the OVT
OV2722 raw camera.
OVT is a 2M raw sensor.
It currently only works with the atomisp driver.
config VIDEO_ATOMISP_GC2235
tristate "Galaxy gc2235 sensor support"
depends on ACPI
depends on I2C && VIDEO_V4L2
---help---
This is a Video4Linux2 sensor-level driver for the OVT
GC2235 raw camera.
GC2235 is a 2M raw sensor.
It currently only works with the atomisp driver.
config VIDEO_ATOMISP_MSRLIST_HELPER
tristate "Helper library to load, parse and apply large register lists."
depends on I2C
---help---
This is a helper library to be used from a sensor driver to load, parse
and apply large register lists.
To compile this driver as a module, choose M here: the
module will be called libmsrlisthelper.
config VIDEO_ATOMISP_MT9M114
tristate "Aptina mt9m114 sensor support"
depends on ACPI
depends on I2C && VIDEO_V4L2
---help---
This is a Video4Linux2 sensor-level driver for the Micron
mt9m114 1.3 Mpixel camera.
mt9m114 is video camera sensor.
It currently only works with the atomisp driver.
config VIDEO_ATOMISP_GC0310
tristate "GC0310 sensor support"
depends on ACPI
depends on I2C && VIDEO_V4L2
---help---
This is a Video4Linux2 sensor-level driver for the Galaxycore
GC0310 0.3MP sensor.
config VIDEO_ATOMISP_OV2680
tristate "Omnivision OV2680 sensor support"
depends on ACPI
depends on I2C && VIDEO_V4L2
---help---
This is a Video4Linux2 sensor-level driver for the Omnivision
OV2680 raw camera.
ov2680 is a 2M raw sensor.
It currently only works with the atomisp driver.
#
# Kconfig for flash drivers
#
config VIDEO_ATOMISP_LM3554
tristate "LM3554 flash light driver"
depends on ACPI
depends on VIDEO_V4L2 && I2C
---help---
This is a Video4Linux2 sub-dev driver for the LM3554
flash light driver.
To compile this driver as a module, choose M here: the
module will be called lm3554

18
drivers/staging/media/atomisp/i2c/Makefile
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@ -1,18 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
#
# Makefile for sensor drivers
#
obj-$(CONFIG_VIDEO_ATOMISP_OV5693) += ov5693/
obj-$(CONFIG_VIDEO_ATOMISP_MT9M114) += atomisp-mt9m114.o
obj-$(CONFIG_VIDEO_ATOMISP_GC2235) += atomisp-gc2235.o
obj-$(CONFIG_VIDEO_ATOMISP_OV2722) += atomisp-ov2722.o
obj-$(CONFIG_VIDEO_ATOMISP_OV2680) += atomisp-ov2680.o
obj-$(CONFIG_VIDEO_ATOMISP_GC0310) += atomisp-gc0310.o
obj-$(CONFIG_VIDEO_ATOMISP_MSRLIST_HELPER) += atomisp-libmsrlisthelper.o
# Makefile for flash drivers
#
obj-$(CONFIG_VIDEO_ATOMISP_LM3554) += atomisp-lm3554.o

1392
drivers/staging/media/atomisp/i2c/atomisp-gc0310.c
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File diff suppressed because it is too large Load Diff

1124
drivers/staging/media/atomisp/i2c/atomisp-gc2235.c
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File diff suppressed because it is too large Load Diff

205
drivers/staging/media/atomisp/i2c/atomisp-libmsrlisthelper.c
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@ -1,205 +0,0 @@
/*
* Copyright (c) 2013 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
*/
#include <linux/i2c.h>
#include <linux/firmware.h>
#include <linux/device.h>
#include <linux/export.h>
#include "../include/linux/libmsrlisthelper.h"
#include <linux/module.h>
#include <linux/slab.h>
/* Tagged binary data container structure definitions. */
struct tbd_header {
uint32_t tag; /*!< Tag identifier, also checks endianness */
uint32_t size; /*!< Container size including this header */
uint32_t version; /*!< Version, format 0xYYMMDDVV */
uint32_t revision; /*!< Revision, format 0xYYMMDDVV */
uint32_t config_bits; /*!< Configuration flag bits set */
uint32_t checksum; /*!< Global checksum, header included */
} __packed;
struct tbd_record_header {
uint32_t size; /*!< Size of record including header */
uint8_t format_id; /*!< tbd_format_t enumeration values used */
uint8_t packing_key; /*!< Packing method; 0 = no packing */
uint16_t class_id; /*!< tbd_class_t enumeration values used */
} __packed;
struct tbd_data_record_header {
uint16_t next_offset;
uint16_t flags;
uint16_t data_offset;
uint16_t data_size;
} __packed;
#define TBD_CLASS_DRV_ID 2
static int set_msr_configuration(struct i2c_client *client, uint8_t *bufptr,
unsigned int size)
{
/* The configuration data contains any number of sequences where
* the first byte (that is, uint8_t) that marks the number of bytes
* in the sequence to follow, is indeed followed by the indicated
* number of bytes of actual data to be written to sensor.
* By convention, the first two bytes of actual data should be
* understood as an address in the sensor address space (hibyte
* followed by lobyte) where the remaining data in the sequence
* will be written. */
uint8_t *ptr = bufptr;
while (ptr < bufptr + size) {
struct i2c_msg msg = {
.addr = client->addr,
.flags = 0,
};
int ret;
/* How many bytes */
msg.len = *ptr++;
/* Where the bytes are located */
msg.buf = ptr;
ptr += msg.len;
if (ptr > bufptr + size)
/* Accessing data beyond bounds is not tolerated */
return -EINVAL;
ret = i2c_transfer(client->adapter, &msg, 1);
if (ret < 0) {
dev_err(&client->dev, "i2c write error: %d", ret);
return ret;
}
}
return 0;
}
static int parse_and_apply(struct i2c_client *client, uint8_t *buffer,
unsigned int size)
{
uint8_t *endptr8 = buffer + size;
struct tbd_data_record_header *header =
(struct tbd_data_record_header *)buffer;
/* There may be any number of datasets present */
unsigned int dataset = 0;
do {
/* In below, four variables are read from buffer */
if ((uint8_t *)header + sizeof(*header) > endptr8)
return -EINVAL;
/* All data should be located within given buffer */
if ((uint8_t *)header + header->data_offset +
header->data_size > endptr8)
return -EINVAL;
/* We have a new valid dataset */
dataset++;
/* See whether there is MSR data */
/* If yes, update the reg info */
if (header->data_size && (header->flags & 1)) {
int ret;
dev_info(&client->dev,
"New MSR data for sensor driver (dataset %02d) size:%d\n",
dataset, header->data_size);
ret = set_msr_configuration(client,
buffer + header->data_offset,
header->data_size);
if (ret)
return ret;
}
header = (struct tbd_data_record_header *)(buffer +
header->next_offset);
} while (header->next_offset);
return 0;
}
int apply_msr_data(struct i2c_client *client, const struct firmware *fw)
{
struct tbd_header *header;
struct tbd_record_header *record;
if (!fw) {
dev_warn(&client->dev, "Drv data is not loaded.\n");
return -EINVAL;
}
if (sizeof(*header) > fw->size)
return -EINVAL;
header = (struct tbd_header *)fw->data;
/* Check that we have drvb block. */
if (memcmp(&header->tag, "DRVB", 4))
return -EINVAL;
/* Check the size */
if (header->size != fw->size)
return -EINVAL;
if (sizeof(*header) + sizeof(*record) > fw->size)
return -EINVAL;
record = (struct tbd_record_header *)(header + 1);
/* Check that class id mathes tbd's drv id. */
if (record->class_id != TBD_CLASS_DRV_ID)
return -EINVAL;
/* Size 0 shall not be treated as an error */
if (!record->size)
return 0;
return parse_and_apply(client, (uint8_t *)(record + 1), record->size);
}
EXPORT_SYMBOL_GPL(apply_msr_data);
int load_msr_list(struct i2c_client *client, char *name,
const struct firmware **fw)
{
int ret = request_firmware(fw, name, &client->dev);
if (ret) {
dev_err(&client->dev,
"Error %d while requesting firmware %s\n",
ret, name);
return ret;
}
dev_info(&client->dev, "Received %lu bytes drv data\n",
(unsigned long)(*fw)->size);
return 0;
}
EXPORT_SYMBOL_GPL(load_msr_list);
void release_msr_list(struct i2c_client *client, const struct firmware *fw)
{
release_firmware(fw);
}
EXPORT_SYMBOL_GPL(release_msr_list);
static int init_msrlisthelper(void)
{
return 0;
}
static void exit_msrlisthelper(void)
{
}
module_init(init_msrlisthelper);
module_exit(exit_msrlisthelper);
MODULE_AUTHOR("Jukka Kaartinen <jukka.o.kaartinen@intel.com>");
MODULE_LICENSE("GPL");

968
drivers/staging/media/atomisp/i2c/atomisp-lm3554.c
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@ -1,968 +0,0 @@
/*
* LED flash driver for LM3554
*
* Copyright (c) 2010-2012 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
*/
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/mutex.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/slab.h>
#include "../include/media/lm3554.h"
#include <media/v4l2-ctrls.h>
#include <media/v4l2-device.h>
#include <linux/acpi.h>
#include <linux/gpio/consumer.h>
#include "../include/linux/atomisp_gmin_platform.h"
#include "../include/linux/atomisp.h"
/* Registers */
#define LM3554_TORCH_BRIGHTNESS_REG 0xA0
#define LM3554_TORCH_MODE_SHIFT 0
#define LM3554_TORCH_CURRENT_SHIFT 3
#define LM3554_INDICATOR_CURRENT_SHIFT 6
#define LM3554_FLASH_BRIGHTNESS_REG 0xB0
#define LM3554_FLASH_MODE_SHIFT 0
#define LM3554_FLASH_CURRENT_SHIFT 3
#define LM3554_STROBE_SENSITIVITY_SHIFT 7
#define LM3554_FLASH_DURATION_REG 0xC0
#define LM3554_FLASH_TIMEOUT_SHIFT 0
#define LM3554_CURRENT_LIMIT_SHIFT 5
#define LM3554_FLAGS_REG 0xD0
#define LM3554_FLAG_TIMEOUT (1 << 0)
#define LM3554_FLAG_THERMAL_SHUTDOWN (1 << 1)
#define LM3554_FLAG_LED_FAULT (1 << 2)
#define LM3554_FLAG_TX1_INTERRUPT (1 << 3)
#define LM3554_FLAG_TX2_INTERRUPT (1 << 4)
#define LM3554_FLAG_LED_THERMAL_FAULT (1 << 5)
#define LM3554_FLAG_UNUSED (1 << 6)
#define LM3554_FLAG_INPUT_VOLTAGE_LOW (1 << 7)
#define LM3554_CONFIG_REG_1 0xE0
#define LM3554_ENVM_TX2_SHIFT 5
#define LM3554_TX2_POLARITY_SHIFT 6
struct lm3554 {
struct v4l2_subdev sd;
struct mutex power_lock;
struct v4l2_ctrl_handler ctrl_handler;
int power_count;
unsigned int mode;
int timeout;
u8 torch_current;
u8 indicator_current;
u8 flash_current;
struct timer_list flash_off_delay;
struct lm3554_platform_data *pdata;
};
#define to_lm3554(p_sd) container_of(p_sd, struct lm3554, sd)
/* Return negative errno else zero on success */
static int lm3554_write(struct lm3554 *flash, u8 addr, u8 val)
{
struct i2c_client *client = v4l2_get_subdevdata(&flash->sd);
int ret;
ret = i2c_smbus_write_byte_data(client, addr, val);
dev_dbg(&client->dev, "Write Addr:%02X Val:%02X %s\n", addr, val,
ret < 0 ? "fail" : "ok");
return ret;
}
/* Return negative errno else a data byte received from the device. */
static int lm3554_read(struct lm3554 *flash, u8 addr)
{
struct i2c_client *client = v4l2_get_subdevdata(&flash->sd);
int ret;
ret = i2c_smbus_read_byte_data(client, addr);
dev_dbg(&client->dev, "Read Addr:%02X Val:%02X %s\n", addr, ret,
ret < 0 ? "fail" : "ok");
return ret;
}
/* -----------------------------------------------------------------------------
* Hardware configuration
*/
static int lm3554_set_mode(struct lm3554 *flash, unsigned int mode)
{
u8 val;
int ret;
val = (mode << LM3554_FLASH_MODE_SHIFT) |
(flash->flash_current << LM3554_FLASH_CURRENT_SHIFT);
ret = lm3554_write(flash, LM3554_FLASH_BRIGHTNESS_REG, val);
if (ret == 0)
flash->mode = mode;
return ret;
}
static int lm3554_set_torch(struct lm3554 *flash)
{
u8 val;
val = (flash->mode << LM3554_TORCH_MODE_SHIFT) |
(flash->torch_current << LM3554_TORCH_CURRENT_SHIFT) |
(flash->indicator_current << LM3554_INDICATOR_CURRENT_SHIFT);
return lm3554_write(flash, LM3554_TORCH_BRIGHTNESS_REG, val);
}
static int lm3554_set_flash(struct lm3554 *flash)
{
u8 val;
val = (flash->mode << LM3554_FLASH_MODE_SHIFT) |
(flash->flash_current << LM3554_FLASH_CURRENT_SHIFT);
return lm3554_write(flash, LM3554_FLASH_BRIGHTNESS_REG, val);
}
static int lm3554_set_duration(struct lm3554 *flash)
{
u8 val;
val = (flash->timeout << LM3554_FLASH_TIMEOUT_SHIFT) |
(flash->pdata->current_limit << LM3554_CURRENT_LIMIT_SHIFT);
return lm3554_write(flash, LM3554_FLASH_DURATION_REG, val);
}
static int lm3554_set_config1(struct lm3554 *flash)
{
u8 val;
val = (flash->pdata->envm_tx2 << LM3554_ENVM_TX2_SHIFT) |
(flash->pdata->tx2_polarity << LM3554_TX2_POLARITY_SHIFT);
return lm3554_write(flash, LM3554_CONFIG_REG_1, val);
}
/* -----------------------------------------------------------------------------
* Hardware trigger
*/
static void lm3554_flash_off_delay(struct timer_list *t)
{
struct lm3554 *flash = from_timer(flash, t, flash_off_delay);
struct lm3554_platform_data *pdata = flash->pdata;
gpio_set_value(pdata->gpio_strobe, 0);
}
static int lm3554_hw_strobe(struct i2c_client *client, bool strobe)
{
int ret, timer_pending;
struct v4l2_subdev *sd = i2c_get_clientdata(client);
struct lm3554 *flash = to_lm3554(sd);
struct lm3554_platform_data *pdata = flash->pdata;
/*
* An abnormal high flash current is observed when strobe off the
* flash. Workaround here is firstly set flash current to lower level,
* wait a short moment, and then strobe off the flash.
*/
timer_pending = del_timer_sync(&flash->flash_off_delay);
/* Flash off */
if (!strobe) {
/* set current to 70mA and wait a while */
ret = lm3554_write(flash, LM3554_FLASH_BRIGHTNESS_REG, 0);
if (ret < 0)
goto err;
mod_timer(&flash->flash_off_delay,
jiffies + msecs_to_jiffies(LM3554_TIMER_DELAY));
return 0;
}
/* Flash on */
/*
* If timer is killed before run, flash is not strobe off,
* so must strobe off here
*/
if (timer_pending)
gpio_set_value(pdata->gpio_strobe, 0);
/* Restore flash current settings */
ret = lm3554_set_flash(flash);
if (ret < 0)
goto err;
/* Strobe on Flash */
gpio_set_value(pdata->gpio_strobe, 1);
return 0;
err:
dev_err(&client->dev, "failed to %s flash strobe (%d)\n",
strobe ? "on" : "off", ret);
return ret;
}
/* -----------------------------------------------------------------------------
* V4L2 controls
*/
static int lm3554_read_status(struct lm3554 *flash)
{
int ret;
struct i2c_client *client = v4l2_get_subdevdata(&flash->sd);
/* NOTE: reading register clear fault status */
ret = lm3554_read(flash, LM3554_FLAGS_REG);
if (ret < 0)
return ret;
/*
* Accordingly to datasheet we read back '1' in bit 6.
* Clear it first.
*/
ret &= ~LM3554_FLAG_UNUSED;
/*
* Do not take TX1/TX2 signal as an error
* because MSIC will not turn off flash, but turn to
* torch mode according to gsm modem signal by hardware.
*/
ret &= ~(LM3554_FLAG_TX1_INTERRUPT | LM3554_FLAG_TX2_INTERRUPT);
if (ret > 0)
dev_dbg(&client->dev, "LM3554 flag status: %02x\n", ret);
return ret;
}
static int lm3554_s_flash_timeout(struct v4l2_subdev *sd, u32 val)
{
struct lm3554 *flash = to_lm3554(sd);
val = clamp(val, LM3554_MIN_TIMEOUT, LM3554_MAX_TIMEOUT);
val = val / LM3554_TIMEOUT_STEPSIZE - 1;
flash->timeout = val;
return lm3554_set_duration(flash);
}
static int lm3554_g_flash_timeout(struct v4l2_subdev *sd, s32 *val)
{
struct lm3554 *flash = to_lm3554(sd);
*val = (u32)(flash->timeout + 1) * LM3554_TIMEOUT_STEPSIZE;
return 0;
}
static int lm3554_s_flash_intensity(struct v4l2_subdev *sd, u32 intensity)
{
struct lm3554 *flash = to_lm3554(sd);
intensity = LM3554_CLAMP_PERCENTAGE(intensity);
intensity = LM3554_PERCENT_TO_VALUE(intensity, LM3554_FLASH_STEP);
flash->flash_current = intensity;
return lm3554_set_flash(flash);
}
static int lm3554_g_flash_intensity(struct v4l2_subdev *sd, s32 *val)
{
struct lm3554 *flash = to_lm3554(sd);
*val = LM3554_VALUE_TO_PERCENT((u32)flash->flash_current,
LM3554_FLASH_STEP);
return 0;
}
static int lm3554_s_torch_intensity(struct v4l2_subdev *sd, u32 intensity)
{
struct lm3554 *flash = to_lm3554(sd);
intensity = LM3554_CLAMP_PERCENTAGE(intensity);
intensity = LM3554_PERCENT_TO_VALUE(intensity, LM3554_TORCH_STEP);
flash->torch_current = intensity;
return lm3554_set_torch(flash);
}
static int lm3554_g_torch_intensity(struct v4l2_subdev *sd, s32 *val)
{
struct lm3554 *flash = to_lm3554(sd);
*val = LM3554_VALUE_TO_PERCENT((u32)flash->torch_current,
LM3554_TORCH_STEP);
return 0;
}
static int lm3554_s_indicator_intensity(struct v4l2_subdev *sd, u32 intensity)
{
struct lm3554 *flash = to_lm3554(sd);
intensity = LM3554_CLAMP_PERCENTAGE(intensity);
intensity = LM3554_PERCENT_TO_VALUE(intensity, LM3554_INDICATOR_STEP);
flash->indicator_current = intensity;
return lm3554_set_torch(flash);
}
static int lm3554_g_indicator_intensity(struct v4l2_subdev *sd, s32 *val)
{
struct lm3554 *flash = to_lm3554(sd);
*val = LM3554_VALUE_TO_PERCENT((u32)flash->indicator_current,
LM3554_INDICATOR_STEP);
return 0;
}
static int lm3554_s_flash_strobe(struct v4l2_subdev *sd, u32 val)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
return lm3554_hw_strobe(client, val);
}
static int lm3554_s_flash_mode(struct v4l2_subdev *sd, u32 new_mode)
{
struct lm3554 *flash = to_lm3554(sd);
unsigned int mode;
switch (new_mode) {
case ATOMISP_FLASH_MODE_OFF:
mode = LM3554_MODE_SHUTDOWN;
break;
case ATOMISP_FLASH_MODE_FLASH:
mode = LM3554_MODE_FLASH;
break;
case ATOMISP_FLASH_MODE_INDICATOR:
mode = LM3554_MODE_INDICATOR;
break;
case ATOMISP_FLASH_MODE_TORCH:
mode = LM3554_MODE_TORCH;
break;
default:
return -EINVAL;
}
return lm3554_set_mode(flash, mode);
}
static int lm3554_g_flash_mode(struct v4l2_subdev *sd, s32 *val)
{
struct lm3554 *flash = to_lm3554(sd);
*val = flash->mode;
return 0;
}
static int lm3554_g_flash_status(struct v4l2_subdev *sd, s32 *val)
{
struct lm3554 *flash = to_lm3554(sd);
int value;
value = lm3554_read_status(flash);
if (value < 0)
return value;
if (value & LM3554_FLAG_TIMEOUT)
*val = ATOMISP_FLASH_STATUS_TIMEOUT;
else if (value > 0)
*val = ATOMISP_FLASH_STATUS_HW_ERROR;
else
*val = ATOMISP_FLASH_STATUS_OK;
return 0;
}
#ifndef CSS15
static int lm3554_g_flash_status_register(struct v4l2_subdev *sd, s32 *val)
{
struct lm3554 *flash = to_lm3554(sd);
int ret;
ret = lm3554_read(flash, LM3554_FLAGS_REG);
if (ret < 0)
return ret;
*val = ret;
return 0;
}
#endif
static int lm3554_s_ctrl(struct v4l2_ctrl *ctrl)
{
struct lm3554 *dev =
container_of(ctrl->handler, struct lm3554, ctrl_handler);
int ret = 0;
switch (ctrl->id) {
case V4L2_CID_FLASH_TIMEOUT:
ret = lm3554_s_flash_timeout(&dev->sd, ctrl->val);
break;
case V4L2_CID_FLASH_INTENSITY:
ret = lm3554_s_flash_intensity(&dev->sd, ctrl->val);
break;
case V4L2_CID_FLASH_TORCH_INTENSITY:
ret = lm3554_s_torch_intensity(&dev->sd, ctrl->val);
break;
case V4L2_CID_FLASH_INDICATOR_INTENSITY:
ret = lm3554_s_indicator_intensity(&dev->sd, ctrl->val);
break;
case V4L2_CID_FLASH_STROBE:
ret = lm3554_s_flash_strobe(&dev->sd, ctrl->val);
break;
case V4L2_CID_FLASH_MODE:
ret = lm3554_s_flash_mode(&dev->sd, ctrl->val);
break;
default:
ret = -EINVAL;
}
return ret;
}
static int lm3554_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
{
struct lm3554 *dev =
container_of(ctrl->handler, struct lm3554, ctrl_handler);
int ret = 0;
switch (ctrl->id) {
case V4L2_CID_FLASH_TIMEOUT:
ret = lm3554_g_flash_timeout(&dev->sd, &ctrl->val);
break;
case V4L2_CID_FLASH_INTENSITY:
ret = lm3554_g_flash_intensity(&dev->sd, &ctrl->val);
break;
case V4L2_CID_FLASH_TORCH_INTENSITY:
ret = lm3554_g_torch_intensity(&dev->sd, &ctrl->val);
break;
case V4L2_CID_FLASH_INDICATOR_INTENSITY:
ret = lm3554_g_indicator_intensity(&dev->sd, &ctrl->val);
break;
case V4L2_CID_FLASH_MODE:
ret = lm3554_g_flash_mode(&dev->sd, &ctrl->val);
break;
case V4L2_CID_FLASH_STATUS:
ret = lm3554_g_flash_status(&dev->sd, &ctrl->val);
break;
#ifndef CSS15
case V4L2_CID_FLASH_STATUS_REGISTER:
ret = lm3554_g_flash_status_register(&dev->sd, &ctrl->val);
break;
#endif
default:
ret = -EINVAL;
}
return ret;
}
static const struct v4l2_ctrl_ops ctrl_ops = {
.s_ctrl = lm3554_s_ctrl,
.g_volatile_ctrl = lm3554_g_volatile_ctrl
};
static const struct v4l2_ctrl_config lm3554_controls[] = {
{
.ops = &ctrl_ops,
.id = V4L2_CID_FLASH_TIMEOUT,
.type = V4L2_CTRL_TYPE_INTEGER,
.name = "Flash Timeout",
.min = 0x0,
.max = LM3554_MAX_TIMEOUT,
.step = 0x01,
.def = LM3554_DEFAULT_TIMEOUT,
.flags = 0,
},
{
.ops = &ctrl_ops,
.id = V4L2_CID_FLASH_INTENSITY,
.type = V4L2_CTRL_TYPE_INTEGER,
.name = "Flash Intensity",
.min = LM3554_MIN_PERCENT,
.max = LM3554_MAX_PERCENT,
.step = 0x01,
.def = LM3554_FLASH_DEFAULT_BRIGHTNESS,
.flags = 0,
},
{
.ops = &ctrl_ops,
.id = V4L2_CID_FLASH_TORCH_INTENSITY,
.type = V4L2_CTRL_TYPE_INTEGER,
.name = "Torch Intensity",
.min = LM3554_MIN_PERCENT,
.max = LM3554_MAX_PERCENT,
.step = 0x01,
.def = LM3554_TORCH_DEFAULT_BRIGHTNESS,
.flags = 0,
},
{
.ops = &ctrl_ops,
.id = V4L2_CID_FLASH_INDICATOR_INTENSITY,
.type = V4L2_CTRL_TYPE_INTEGER,
.name = "Indicator Intensity",
.min = LM3554_MIN_PERCENT,
.max = LM3554_MAX_PERCENT,
.step = 0x01,
.def = LM3554_INDICATOR_DEFAULT_BRIGHTNESS,
.flags = 0,
},
{
.ops = &ctrl_ops,
.id = V4L2_CID_FLASH_STROBE,
.type = V4L2_CTRL_TYPE_BOOLEAN,
.name = "Flash Strobe",
.min = 0,
.max = 1,
.step = 1,
.def = 0,
.flags = 0,
},
{
.ops = &ctrl_ops,
.id = V4L2_CID_FLASH_MODE,
.type = V4L2_CTRL_TYPE_INTEGER,
.name = "Flash Mode",
.min = 0,
.max = 100,
.step = 1,
.def = ATOMISP_FLASH_MODE_OFF,
.flags = 0,
},
{
.ops = &ctrl_ops,
.id = V4L2_CID_FLASH_STATUS,
.type = V4L2_CTRL_TYPE_INTEGER,
.name = "Flash Status",
.min = ATOMISP_FLASH_STATUS_OK,
.max = ATOMISP_FLASH_STATUS_TIMEOUT,
.step = 1,
.def = ATOMISP_FLASH_STATUS_OK,
.flags = 0,
},
#ifndef CSS15
{
.ops = &ctrl_ops,
.id = V4L2_CID_FLASH_STATUS_REGISTER,
.type = V4L2_CTRL_TYPE_INTEGER,
.name = "Flash Status Register",
.min = 0,
.max = 255,
.step = 1,
.def = 0,
.flags = 0,
},
#endif
};
/* -----------------------------------------------------------------------------
* V4L2 subdev core operations
*/
/* Put device into known state. */
static int lm3554_setup(struct lm3554 *flash)
{
struct i2c_client *client = v4l2_get_subdevdata(&flash->sd);
int ret;
/* clear the flags register */
ret = lm3554_read(flash, LM3554_FLAGS_REG);
if (ret < 0)
return ret;
dev_dbg(&client->dev, "Fault info: %02x\n", ret);
ret = lm3554_set_config1(flash);
if (ret < 0)
return ret;
ret = lm3554_set_duration(flash);
if (ret < 0)
return ret;
ret = lm3554_set_torch(flash);
if (ret < 0)
return ret;
ret = lm3554_set_flash(flash);
if (ret < 0)
return ret;
/* read status */
ret = lm3554_read_status(flash);
if (ret < 0)
return ret;
return ret ? -EIO : 0;
}
static int __lm3554_s_power(struct lm3554 *flash, int power)
{
struct lm3554_platform_data *pdata = flash->pdata;
int ret;
/*initialize flash driver*/
gpio_set_value(pdata->gpio_reset, power);
usleep_range(100, 100 + 1);
if (power) {
/* Setup default values. This makes sure that the chip
* is in a known state.
*/
ret = lm3554_setup(flash);
if (ret < 0) {
__lm3554_s_power(flash, 0);
return ret;
}
}
return 0;
}
static int lm3554_s_power(struct v4l2_subdev *sd, int power)
{
struct lm3554 *flash = to_lm3554(sd);
int ret = 0;
mutex_lock(&flash->power_lock);
if (flash->power_count == !power) {
ret = __lm3554_s_power(flash, !!power);
if (ret < 0)
goto done;
}
flash->power_count += power ? 1 : -1;
WARN_ON(flash->power_count < 0);
done:
mutex_unlock(&flash->power_lock);
return ret;
}
static const struct v4l2_subdev_core_ops lm3554_core_ops = {
.s_power = lm3554_s_power,
};
static const struct v4l2_subdev_ops lm3554_ops = {
.core = &lm3554_core_ops,
};
static int lm3554_detect(struct v4l2_subdev *sd)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
struct i2c_adapter *adapter = client->adapter;
struct lm3554 *flash = to_lm3554(sd);
int ret;
if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
dev_err(&client->dev, "lm3554_detect i2c error\n");
return -ENODEV;
}
/* Power up the flash driver and reset it */
ret = lm3554_s_power(&flash->sd, 1);
if (ret < 0) {
dev_err(&client->dev, "Failed to power on lm3554 LED flash\n");
} else {
dev_dbg(&client->dev, "Successfully detected lm3554 LED flash\n");
lm3554_s_power(&flash->sd, 0);
}
return ret;
}
static int lm3554_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
{
return lm3554_s_power(sd, 1);
}
static int lm3554_close(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
{
return lm3554_s_power(sd, 0);
}
static const struct v4l2_subdev_internal_ops lm3554_internal_ops = {
.registered = lm3554_detect,
.open = lm3554_open,
.close = lm3554_close,
};
/* -----------------------------------------------------------------------------
* I2C driver
*/
#ifdef CONFIG_PM
static int lm3554_suspend(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
struct v4l2_subdev *subdev = i2c_get_clientdata(client);
struct lm3554 *flash = to_lm3554(subdev);
int rval;
if (flash->power_count == 0)
return 0;
rval = __lm3554_s_power(flash, 0);
dev_dbg(&client->dev, "Suspend %s\n", rval < 0 ? "failed" : "ok");
return rval;
}
static int lm3554_resume(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
struct v4l2_subdev *subdev = i2c_get_clientdata(client);
struct lm3554 *flash = to_lm3554(subdev);
int rval;
if (flash->power_count == 0)
return 0;
rval = __lm3554_s_power(flash, 1);
dev_dbg(&client->dev, "Resume %s\n", rval < 0 ? "fail" : "ok");
return rval;
}
#else
#define lm3554_suspend NULL
#define lm3554_resume NULL
#endif /* CONFIG_PM */
static int lm3554_gpio_init(struct i2c_client *client)
{
struct v4l2_subdev *sd = i2c_get_clientdata(client);
struct lm3554 *flash = to_lm3554(sd);
struct lm3554_platform_data *pdata = flash->pdata;
int ret;
if (!gpio_is_valid(pdata->gpio_reset))
return -EINVAL;
ret = gpio_direction_output(pdata->gpio_reset, 0);
if (ret < 0)
goto err_gpio_reset;
dev_info(&client->dev, "flash led reset successfully\n");
if (!gpio_is_valid(pdata->gpio_strobe)) {
ret = -EINVAL;
goto err_gpio_dir_reset;
}
ret = gpio_direction_output(pdata->gpio_strobe, 0);
if (ret < 0)
goto err_gpio_strobe;
return 0;
err_gpio_strobe:
gpio_free(pdata->gpio_strobe);
err_gpio_dir_reset:
gpio_direction_output(pdata->gpio_reset, 0);
err_gpio_reset:
gpio_free(pdata->gpio_reset);
return ret;
}
static int lm3554_gpio_uninit(struct i2c_client *client)
{
struct v4l2_subdev *sd = i2c_get_clientdata(client);
struct lm3554 *flash = to_lm3554(sd);
struct lm3554_platform_data *pdata = flash->pdata;
int ret;
ret = gpio_direction_output(pdata->gpio_strobe, 0);
if (ret < 0)
return ret;
ret = gpio_direction_output(pdata->gpio_reset, 0);
if (ret < 0)
return ret;
gpio_free(pdata->gpio_strobe);
gpio_free(pdata->gpio_reset);
return 0;
}
static void *lm3554_platform_data_func(struct i2c_client *client)
{
static struct lm3554_platform_data platform_data;
platform_data.gpio_reset =
desc_to_gpio(gpiod_get_index(&client->dev,
NULL, 2, GPIOD_OUT_LOW));
platform_data.gpio_strobe =
desc_to_gpio(gpiod_get_index(&client->dev,
NULL, 0, GPIOD_OUT_LOW));
platform_data.gpio_torch =
desc_to_gpio(gpiod_get_index(&client->dev,
NULL, 1, GPIOD_OUT_LOW));
dev_info(&client->dev, "camera pdata: lm3554: reset: %d strobe %d torch %d\n",
platform_data.gpio_reset, platform_data.gpio_strobe,
platform_data.gpio_torch);
/* Set to TX2 mode, then ENVM/TX2 pin is a power amplifier sync input:
* ENVM/TX pin asserted, flash forced into torch;
* ENVM/TX pin desserted, flash set back;
*/
platform_data.envm_tx2 = 1;
platform_data.tx2_polarity = 0;
/* set peak current limit to be 1000mA */
platform_data.current_limit = 0;
return &platform_data;
}
static int lm3554_probe(struct i2c_client *client)
{
int err = 0;
struct lm3554 *flash;
unsigned int i;
int ret;
flash = kzalloc(sizeof(*flash), GFP_KERNEL);
if (!flash)
return -ENOMEM;
flash->pdata = lm3554_platform_data_func(client);
v4l2_i2c_subdev_init(&flash->sd, client, &lm3554_ops);
flash->sd.internal_ops = &lm3554_internal_ops;
flash->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
flash->mode = ATOMISP_FLASH_MODE_OFF;
flash->timeout = LM3554_MAX_TIMEOUT / LM3554_TIMEOUT_STEPSIZE - 1;
ret =
v4l2_ctrl_handler_init(&flash->ctrl_handler,
ARRAY_SIZE(lm3554_controls));
if (ret) {
dev_err(&client->dev, "error initialize a ctrl_handler.\n");
goto fail2;
}
for (i = 0; i < ARRAY_SIZE(lm3554_controls); i++)
v4l2_ctrl_new_custom(&flash->ctrl_handler, &lm3554_controls[i],
NULL);
if (flash->ctrl_handler.error) {
dev_err(&client->dev, "ctrl_handler error.\n");
goto fail2;
}
flash->sd.ctrl_handler = &flash->ctrl_handler;
err = media_entity_pads_init(&flash->sd.entity, 0, NULL);
if (err) {
dev_err(&client->dev, "error initialize a media entity.\n");
goto fail1;
}
flash->sd.entity.function = MEDIA_ENT_F_FLASH;
mutex_init(&flash->power_lock);
timer_setup(&flash->flash_off_delay, lm3554_flash_off_delay, 0);
err = lm3554_gpio_init(client);
if (err) {
dev_err(&client->dev, "gpio request/direction_output fail");
goto fail2;
}
return atomisp_register_i2c_module(&flash->sd, NULL, LED_FLASH);
fail2:
media_entity_cleanup(&flash->sd.entity);
v4l2_ctrl_handler_free(&flash->ctrl_handler);
fail1:
v4l2_device_unregister_subdev(&flash->sd);
kfree(flash);
return err;
}
static int lm3554_remove(struct i2c_client *client)
{
struct v4l2_subdev *sd = i2c_get_clientdata(client);
struct lm3554 *flash = to_lm3554(sd);
int ret;
media_entity_cleanup(&flash->sd.entity);
v4l2_ctrl_handler_free(&flash->ctrl_handler);
v4l2_device_unregister_subdev(sd);
atomisp_gmin_remove_subdev(sd);
del_timer_sync(&flash->flash_off_delay);
ret = lm3554_gpio_uninit(client);
if (ret < 0)
goto fail;
kfree(flash);
return 0;
fail:
dev_err(&client->dev, "gpio request/direction_output fail");
return ret;
}
static const struct dev_pm_ops lm3554_pm_ops = {
.suspend = lm3554_suspend,
.resume = lm3554_resume,
};
static const struct acpi_device_id lm3554_acpi_match[] = {
{ "INTCF1C" },
{},
};
MODULE_DEVICE_TABLE(acpi, lm3554_acpi_match);
static struct i2c_driver lm3554_driver = {
.driver = {
.name = "lm3554",
.pm = &lm3554_pm_ops,
.acpi_match_table = lm3554_acpi_match,
},
.probe_new = lm3554_probe,
.remove = lm3554_remove,
};
module_i2c_driver(lm3554_driver);
MODULE_AUTHOR("Jing Tao <jing.tao@intel.com>");
MODULE_DESCRIPTION("LED flash driver for LM3554");
MODULE_LICENSE("GPL");

1908
drivers/staging/media/atomisp/i2c/atomisp-mt9m114.c
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1470
drivers/staging/media/atomisp/i2c/atomisp-ov2680.c
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1271
drivers/staging/media/atomisp/i2c/atomisp-ov2722.c
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404
drivers/staging/media/atomisp/i2c/gc0310.h
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@ -1,404 +0,0 @@
/*
* Support for GalaxyCore GC0310 VGA camera sensor.
*
* Copyright (c) 2013 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
*/
#ifndef __GC0310_H__
#define __GC0310_H__
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/i2c.h>
#include <linux/acpi.h>
#include <linux/delay.h>
#include <linux/videodev2.h>
#include <linux/spinlock.h>
#include <media/v4l2-subdev.h>
#include <media/v4l2-device.h>
#include <media/v4l2-ctrls.h>
#include <linux/v4l2-mediabus.h>
#include <media/media-entity.h>
#include "../include/linux/atomisp_platform.h"
/* Defines for register writes and register array processing */
#define I2C_MSG_LENGTH 1
#define I2C_RETRY_COUNT 5
#define GC0310_FOCAL_LENGTH_NUM 278 /*2.78mm*/
#define GC0310_FOCAL_LENGTH_DEM 100
#define GC0310_F_NUMBER_DEFAULT_NUM 26
#define GC0310_F_NUMBER_DEM 10
#define MAX_FMTS 1
/*
* focal length bits definition:
* bits 31-16: numerator, bits 15-0: denominator
*/
#define GC0310_FOCAL_LENGTH_DEFAULT 0x1160064
/*
* current f-number bits definition:
* bits 31-16: numerator, bits 15-0: denominator
*/
#define GC0310_F_NUMBER_DEFAULT 0x1a000a
/*
* f-number range bits definition:
* bits 31-24: max f-number numerator
* bits 23-16: max f-number denominator
* bits 15-8: min f-number numerator
* bits 7-0: min f-number denominator
*/
#define GC0310_F_NUMBER_RANGE 0x1a0a1a0a
#define GC0310_ID 0xa310
#define GC0310_RESET_RELATED 0xFE
#define GC0310_REGISTER_PAGE_0 0x0
#define GC0310_REGISTER_PAGE_3 0x3
#define GC0310_FINE_INTG_TIME_MIN 0
#define GC0310_FINE_INTG_TIME_MAX_MARGIN 0
#define GC0310_COARSE_INTG_TIME_MIN 1
#define GC0310_COARSE_INTG_TIME_MAX_MARGIN 6
/*
* GC0310 System control registers
*/
#define GC0310_SW_STREAM 0x10
#define GC0310_SC_CMMN_CHIP_ID_H 0xf0
#define GC0310_SC_CMMN_CHIP_ID_L 0xf1
#define GC0310_AEC_PK_EXPO_H 0x03
#define GC0310_AEC_PK_EXPO_L 0x04
#define GC0310_AGC_ADJ 0x48
#define GC0310_DGC_ADJ 0x71
#if 0
#define GC0310_GROUP_ACCESS 0x3208
#endif
#define GC0310_H_CROP_START_H 0x09
#define GC0310_H_CROP_START_L 0x0A
#define GC0310_V_CROP_START_H 0x0B
#define GC0310_V_CROP_START_L 0x0C
#define GC0310_H_OUTSIZE_H 0x0F
#define GC0310_H_OUTSIZE_L 0x10
#define GC0310_V_OUTSIZE_H 0x0D
#define GC0310_V_OUTSIZE_L 0x0E
#define GC0310_H_BLANKING_H 0x05
#define GC0310_H_BLANKING_L 0x06
#define GC0310_V_BLANKING_H 0x07
#define GC0310_V_BLANKING_L 0x08
#define GC0310_SH_DELAY 0x11
#define GC0310_START_STREAMING 0x94 /* 8-bit enable */
#define GC0310_STOP_STREAMING 0x0 /* 8-bit disable */
#define GC0310_BIN_FACTOR_MAX 3
struct regval_list {
u16 reg_num;
u8 value;
};
struct gc0310_resolution {
u8 *desc;
const struct gc0310_reg *regs;
int res;
int width;
int height;
int fps;
int pix_clk_freq;
u32 skip_frames;
u16 pixels_per_line;
u16 lines_per_frame;
u8 bin_factor_x;
u8 bin_factor_y;
u8 bin_mode;
bool used;
};
struct gc0310_format {
u8 *desc;
u32 pixelformat;
struct gc0310_reg *regs;
};
/*
* gc0310 device structure.
*/
struct gc0310_device {
struct v4l2_subdev sd;
struct media_pad pad;
struct v4l2_mbus_framefmt format;
struct mutex input_lock;
struct v4l2_ctrl_handler ctrl_handler;
struct camera_sensor_platform_data *platform_data;
int vt_pix_clk_freq_mhz;
int fmt_idx;
u8 res;
u8 type;
};
enum gc0310_tok_type {
GC0310_8BIT = 0x0001,
GC0310_TOK_TERM = 0xf000, /* terminating token for reg list */
GC0310_TOK_DELAY = 0xfe00, /* delay token for reg list */
GC0310_TOK_MASK = 0xfff0
};
/**
* struct gc0310_reg - MI sensor register format
* @type: type of the register
* @reg: 16-bit offset to register
* @val: 8/16/32-bit register value
*
* Define a structure for sensor register initialization values
*/
struct gc0310_reg {
enum gc0310_tok_type type;
u8 reg;
u8 val; /* @set value for read/mod/write, @mask */
};
#define to_gc0310_sensor(x) container_of(x, struct gc0310_device, sd)
#define GC0310_MAX_WRITE_BUF_SIZE 30
struct gc0310_write_buffer {
u8 addr;
u8 data[GC0310_MAX_WRITE_BUF_SIZE];
};
struct gc0310_write_ctrl {
int index;
struct gc0310_write_buffer buffer;
};
/*
* Register settings for various resolution
*/
static const struct gc0310_reg gc0310_reset_register[] = {
/////////////////////////////////////////////////
///////////////// system reg /////////////////
/////////////////////////////////////////////////
{GC0310_8BIT, 0xfe, 0xf0},
{GC0310_8BIT, 0xfe, 0xf0},
{GC0310_8BIT, 0xfe, 0x00},
{GC0310_8BIT, 0xfc, 0x0e}, //4e
{GC0310_8BIT, 0xfc, 0x0e}, //16//4e // [0]apwd [6]regf_clk_gate
{GC0310_8BIT, 0xf2, 0x80}, //sync output
{GC0310_8BIT, 0xf3, 0x00}, //1f//01 data output
{GC0310_8BIT, 0xf7, 0x33}, //f9
{GC0310_8BIT, 0xf8, 0x05}, //00
{GC0310_8BIT, 0xf9, 0x0e}, // 0x8e //0f
{GC0310_8BIT, 0xfa, 0x11},
/////////////////////////////////////////////////
/////////////////// MIPI ////////////////////
/////////////////////////////////////////////////
{GC0310_8BIT, 0xfe, 0x03},
{GC0310_8BIT, 0x01, 0x03}, ///mipi 1lane
{GC0310_8BIT, 0x02, 0x22}, // 0x33
{GC0310_8BIT, 0x03, 0x94},
{GC0310_8BIT, 0x04, 0x01}, // fifo_prog
{GC0310_8BIT, 0x05, 0x00}, //fifo_prog
{GC0310_8BIT, 0x06, 0x80}, //b0 //YUV ISP data
{GC0310_8BIT, 0x11, 0x2a},//1e //LDI set YUV422
{GC0310_8BIT, 0x12, 0x90},//00 //04 //00 //04//00 //LWC[7:0] //
{GC0310_8BIT, 0x13, 0x02},//05 //05 //LWC[15:8]
{GC0310_8BIT, 0x15, 0x12}, // 0x10 //DPHYY_MODE read_ready
{GC0310_8BIT, 0x17, 0x01},
{GC0310_8BIT, 0x40, 0x08},
{GC0310_8BIT, 0x41, 0x00},
{GC0310_8BIT, 0x42, 0x00},
{GC0310_8BIT, 0x43, 0x00},
{GC0310_8BIT, 0x21, 0x02}, // 0x01
{GC0310_8BIT, 0x22, 0x02}, // 0x01
{GC0310_8BIT, 0x23, 0x01}, // 0x05 //Nor:0x05 DOU:0x06
{GC0310_8BIT, 0x29, 0x00},
{GC0310_8BIT, 0x2A, 0x25}, // 0x05 //data zero 0x7a de
{GC0310_8BIT, 0x2B, 0x02},
{GC0310_8BIT, 0xfe, 0x00},
/////////////////////////////////////////////////
///////////////// CISCTL reg /////////////////
/////////////////////////////////////////////////
{GC0310_8BIT, 0x00, 0x2f}, //2f//0f//02//01
{GC0310_8BIT, 0x01, 0x0f}, //06
{GC0310_8BIT, 0x02, 0x04},
{GC0310_8BIT, 0x4f, 0x00}, //AEC 0FF
{GC0310_8BIT, 0x03, 0x01}, // 0x03 //04
{GC0310_8BIT, 0x04, 0xc0}, // 0xe8 //58
{GC0310_8BIT, 0x05, 0x00},
{GC0310_8BIT, 0x06, 0xb2}, // 0x0a //HB
{GC0310_8BIT, 0x07, 0x00},
{GC0310_8BIT, 0x08, 0x0c}, // 0x89 //VB
{GC0310_8BIT, 0x09, 0x00}, //row start
{GC0310_8BIT, 0x0a, 0x00}, //
{GC0310_8BIT, 0x0b, 0x00}, //col start
{GC0310_8BIT, 0x0c, 0x00},
{GC0310_8BIT, 0x0d, 0x01}, //height
{GC0310_8BIT, 0x0e, 0xf2}, // 0xf7 //height
{GC0310_8BIT, 0x0f, 0x02}, //width
{GC0310_8BIT, 0x10, 0x94}, // 0xa0 //height
{GC0310_8BIT, 0x17, 0x14},
{GC0310_8BIT, 0x18, 0x1a}, //0a//[4]double reset
{GC0310_8BIT, 0x19, 0x14}, //AD pipeline
{GC0310_8BIT, 0x1b, 0x48},
{GC0310_8BIT, 0x1e, 0x6b}, //3b//col bias
{GC0310_8BIT, 0x1f, 0x28}, //20//00//08//txlow
{GC0310_8BIT, 0x20, 0x89}, //88//0c//[3:2]DA15
{GC0310_8BIT, 0x21, 0x49}, //48//[3] txhigh
{GC0310_8BIT, 0x22, 0xb0},
{GC0310_8BIT, 0x23, 0x04}, //[1:0]vcm_r
{GC0310_8BIT, 0x24, 0x16}, //15
{GC0310_8BIT, 0x34, 0x20}, //[6:4] rsg high//range
/////////////////////////////////////////////////
//////////////////// BLK ////////////////////
/////////////////////////////////////////////////
{GC0310_8BIT, 0x26, 0x23}, //[1]dark_current_en [0]offset_en
{GC0310_8BIT, 0x28, 0xff}, //BLK_limie_value
{GC0310_8BIT, 0x29, 0x00}, //global offset
{GC0310_8BIT, 0x33, 0x18}, //offset_ratio
{GC0310_8BIT, 0x37, 0x20}, //dark_current_ratio
{GC0310_8BIT, 0x2a, 0x00},
{GC0310_8BIT, 0x2b, 0x00},
{GC0310_8BIT, 0x2c, 0x00},
{GC0310_8BIT, 0x2d, 0x00},
{GC0310_8BIT, 0x2e, 0x00},
{GC0310_8BIT, 0x2f, 0x00},
{GC0310_8BIT, 0x30, 0x00},
{GC0310_8BIT, 0x31, 0x00},
{GC0310_8BIT, 0x47, 0x80}, //a7
{GC0310_8BIT, 0x4e, 0x66}, //select_row
{GC0310_8BIT, 0xa8, 0x02}, //win_width_dark, same with crop_win_width
{GC0310_8BIT, 0xa9, 0x80},
/////////////////////////////////////////////////
////////////////// ISP reg ///////////////////
/////////////////////////////////////////////////
{GC0310_8BIT, 0x40, 0x06}, // 0xff //ff //48
{GC0310_8BIT, 0x41, 0x00}, // 0x21 //00//[0]curve_en
{GC0310_8BIT, 0x42, 0x04}, // 0xcf //0a//[1]awn_en
{GC0310_8BIT, 0x44, 0x18}, // 0x18 //02
{GC0310_8BIT, 0x46, 0x02}, // 0x03 //sync
{GC0310_8BIT, 0x49, 0x03},
{GC0310_8BIT, 0x4c, 0x20}, //00[5]pretect exp
{GC0310_8BIT, 0x50, 0x01}, //crop enable
{GC0310_8BIT, 0x51, 0x00},
{GC0310_8BIT, 0x52, 0x00},
{GC0310_8BIT, 0x53, 0x00},
{GC0310_8BIT, 0x54, 0x01},
{GC0310_8BIT, 0x55, 0x01}, //crop window height
{GC0310_8BIT, 0x56, 0xf0},
{GC0310_8BIT, 0x57, 0x02}, //crop window width
{GC0310_8BIT, 0x58, 0x90},
/////////////////////////////////////////////////
/////////////////// GAIN ////////////////////
/////////////////////////////////////////////////
{GC0310_8BIT, 0x70, 0x70}, //70 //80//global gain
{GC0310_8BIT, 0x71, 0x20}, // pregain gain
{GC0310_8BIT, 0x72, 0x40}, // post gain
{GC0310_8BIT, 0x5a, 0x84}, //84//analog gain 0
{GC0310_8BIT, 0x5b, 0xc9}, //c9
{GC0310_8BIT, 0x5c, 0xed}, //ed//not use pga gain highest level
{GC0310_8BIT, 0x77, 0x40}, // R gain 0x74 //awb gain
{GC0310_8BIT, 0x78, 0x40}, // G gain
{GC0310_8BIT, 0x79, 0x40}, // B gain 0x5f
{GC0310_8BIT, 0x48, 0x00},
{GC0310_8BIT, 0xfe, 0x01},
{GC0310_8BIT, 0x0a, 0x45}, //[7]col gain mode
{GC0310_8BIT, 0x3e, 0x40},
{GC0310_8BIT, 0x3f, 0x5c},
{GC0310_8BIT, 0x40, 0x7b},
{GC0310_8BIT, 0x41, 0xbd},
{GC0310_8BIT, 0x42, 0xf6},
{GC0310_8BIT, 0x43, 0x63},
{GC0310_8BIT, 0x03, 0x60},
{GC0310_8BIT, 0x44, 0x03},
/////////////////////////////////////////////////
///////////////// dark sun //////////////////
/////////////////////////////////////////////////
{GC0310_8BIT, 0xfe, 0x01},
{GC0310_8BIT, 0x45, 0xa4}, // 0xf7
{GC0310_8BIT, 0x46, 0xf0}, // 0xff //f0//sun vaule th
{GC0310_8BIT, 0x48, 0x03}, //sun mode
{GC0310_8BIT, 0x4f, 0x60}, //sun_clamp
{GC0310_8BIT, 0xfe, 0x00},
{GC0310_TOK_TERM, 0, 0},
};
static struct gc0310_reg const gc0310_VGA_30fps[] = {
{GC0310_8BIT, 0xfe, 0x00},
{GC0310_8BIT, 0x0d, 0x01}, //height
{GC0310_8BIT, 0x0e, 0xf2}, // 0xf7 //height
{GC0310_8BIT, 0x0f, 0x02}, //width
{GC0310_8BIT, 0x10, 0x94}, // 0xa0 //height
{GC0310_8BIT, 0x50, 0x01}, //crop enable
{GC0310_8BIT, 0x51, 0x00},
{GC0310_8BIT, 0x52, 0x00},
{GC0310_8BIT, 0x53, 0x00},
{GC0310_8BIT, 0x54, 0x01},
{GC0310_8BIT, 0x55, 0x01}, //crop window height
{GC0310_8BIT, 0x56, 0xf0},
{GC0310_8BIT, 0x57, 0x02}, //crop window width
{GC0310_8BIT, 0x58, 0x90},
{GC0310_8BIT, 0xfe, 0x03},
{GC0310_8BIT, 0x12, 0x90},//00 //04 //00 //04//00 //LWC[7:0] //
{GC0310_8BIT, 0x13, 0x02},//05 //05 //LWC[15:8]
{GC0310_8BIT, 0xfe, 0x00},
{GC0310_TOK_TERM, 0, 0},
};
static struct gc0310_resolution gc0310_res_preview[] = {
{
.desc = "gc0310_VGA_30fps",
.width = 656, // 648,
.height = 496, // 488,
.fps = 30,
//.pix_clk_freq = 73,
.used = 0,
#if 0
.pixels_per_line = 0x0314,
.lines_per_frame = 0x0213,
#endif
.bin_factor_x = 1,
.bin_factor_y = 1,
.bin_mode = 0,
.skip_frames = 2,
.regs = gc0310_VGA_30fps,
},
};
#define N_RES_PREVIEW (ARRAY_SIZE(gc0310_res_preview))
static struct gc0310_resolution *gc0310_res = gc0310_res_preview;
static unsigned long N_RES = N_RES_PREVIEW;
#endif

677
drivers/staging/media/atomisp/i2c/gc2235.h
View File

@ -1,677 +0,0 @@
/*
* Support for GalaxyCore GC2235 2M camera sensor.
*
* Copyright (c) 2014 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program.
*
*/
#ifndef __GC2235_H__
#define __GC2235_H__
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/i2c.h>
#include <linux/delay.h>
#include <linux/videodev2.h>
#include <linux/spinlock.h>
#include <media/v4l2-subdev.h>
#include <media/v4l2-device.h>
#include <media/v4l2-ctrls.h>
#include <linux/v4l2-mediabus.h>
#include <media/media-entity.h>
#include "../include/linux/atomisp_platform.h"
/*
* FIXME: non-preview resolutions are currently broken
*/
#define ENABLE_NON_PREVIEW 0
/* Defines for register writes and register array processing */
#define I2C_MSG_LENGTH 0x2
#define I2C_RETRY_COUNT 5
#define GC2235_FOCAL_LENGTH_NUM 278 /*2.78mm*/
#define GC2235_FOCAL_LENGTH_DEM 100
#define GC2235_F_NUMBER_DEFAULT_NUM 26
#define GC2235_F_NUMBER_DEM 10
#define MAX_FMTS 1
/*
* focal length bits definition:
* bits 31-16: numerator, bits 15-0: denominator
*/
#define GC2235_FOCAL_LENGTH_DEFAULT 0x1160064
/*
* current f-number bits definition:
* bits 31-16: numerator, bits 15-0: denominator
*/
#define GC2235_F_NUMBER_DEFAULT 0x1a000a
/*
* f-number range bits definition:
* bits 31-24: max f-number numerator
* bits 23-16: max f-number denominator
* bits 15-8: min f-number numerator
* bits 7-0: min f-number denominator
*/
#define GC2235_F_NUMBER_RANGE 0x1a0a1a0a
#define GC2235_ID 0x2235
#define GC2235_FINE_INTG_TIME_MIN 0
#define GC2235_FINE_INTG_TIME_MAX_MARGIN 0
#define GC2235_COARSE_INTG_TIME_MIN 1
#define GC2235_COARSE_INTG_TIME_MAX_MARGIN 6
/*
* GC2235 System control registers
*/
/*
* GC2235 System control registers
*/
#define GC2235_SENSOR_ID_H 0xF0
#define GC2235_SENSOR_ID_L 0xF1
#define GC2235_RESET_RELATED 0xFE
#define GC2235_SW_RESET 0x8
#define GC2235_MIPI_RESET 0x3
#define GC2235_RESET_BIT 0x4
#define GC2235_REGISTER_PAGE_0 0x0
#define GC2235_REGISTER_PAGE_3 0x3
#define GC2235_V_CROP_START_H 0x91
#define GC2235_V_CROP_START_L 0x92
#define GC2235_H_CROP_START_H 0x93
#define GC2235_H_CROP_START_L 0x94
#define GC2235_V_OUTSIZE_H 0x95
#define GC2235_V_OUTSIZE_L 0x96
#define GC2235_H_OUTSIZE_H 0x97
#define GC2235_H_OUTSIZE_L 0x98
#define GC2235_HB_H 0x5
#define GC2235_HB_L 0x6
#define GC2235_VB_H 0x7
#define GC2235_VB_L 0x8
#define GC2235_SH_DELAY_H 0x11
#define GC2235_SH_DELAY_L 0x12
#define GC2235_CSI2_MODE 0x10
#define GC2235_EXPOSURE_H 0x3
#define GC2235_EXPOSURE_L 0x4
#define GC2235_GLOBAL_GAIN 0xB0
#define GC2235_PRE_GAIN 0xB1
#define GC2235_AWB_R_GAIN 0xB3
#define GC2235_AWB_G_GAIN 0xB4
#define GC2235_AWB_B_GAIN 0xB5
#define GC2235_START_STREAMING 0x91
#define GC2235_STOP_STREAMING 0x0
struct regval_list {
u16 reg_num;
u8 value;
};
struct gc2235_resolution {
u8 *desc;
const struct gc2235_reg *regs;
int res;
int width;
int height;
int fps;
int pix_clk_freq;
u32 skip_frames;
u16 pixels_per_line;
u16 lines_per_frame;
u8 bin_factor_x;
u8 bin_factor_y;
u8 bin_mode;
bool used;
};
struct gc2235_format {
u8 *desc;
u32 pixelformat;
struct gc2235_reg *regs;
};
/*
* gc2235 device structure.
*/
struct gc2235_device {
struct v4l2_subdev sd;
struct media_pad pad;
struct v4l2_mbus_framefmt format;
struct mutex input_lock;
struct v4l2_ctrl_handler ctrl_handler;
struct camera_sensor_platform_data *platform_data;
int vt_pix_clk_freq_mhz;
int fmt_idx;
u8 res;
u8 type;
};
enum gc2235_tok_type {
GC2235_8BIT = 0x0001,
GC2235_16BIT = 0x0002,
GC2235_32BIT = 0x0004,
GC2235_TOK_TERM = 0xf000, /* terminating token for reg list */
GC2235_TOK_DELAY = 0xfe00, /* delay token for reg list */
GC2235_TOK_MASK = 0xfff0
};
/**
* struct gc2235_reg - MI sensor register format
* @type: type of the register
* @reg: 8-bit offset to register
* @val: 8/16/32-bit register value
*
* Define a structure for sensor register initialization values
*/
struct gc2235_reg {
enum gc2235_tok_type type;
u8 reg;
u32 val; /* @set value for read/mod/write, @mask */
};
#define to_gc2235_sensor(x) container_of(x, struct gc2235_device, sd)
#define GC2235_MAX_WRITE_BUF_SIZE 30
struct gc2235_write_buffer {
u8 addr;
u8 data[GC2235_MAX_WRITE_BUF_SIZE];
};
struct gc2235_write_ctrl {
int index;
struct gc2235_write_buffer buffer;
};
static struct gc2235_reg const gc2235_stream_on[] = {
{ GC2235_8BIT, 0xfe, 0x03}, /* switch to P3 */
{ GC2235_8BIT, 0x10, 0x91}, /* start mipi */
{ GC2235_8BIT, 0xfe, 0x00}, /* switch to P0 */
{ GC2235_TOK_TERM, 0, 0 }
};
static struct gc2235_reg const gc2235_stream_off[] = {
{ GC2235_8BIT, 0xfe, 0x03}, /* switch to P3 */
{ GC2235_8BIT, 0x10, 0x01}, /* stop mipi */
{ GC2235_8BIT, 0xfe, 0x00}, /* switch to P0 */
{ GC2235_TOK_TERM, 0, 0 }
};
static struct gc2235_reg const gc2235_init_settings[] = {
/* Sysytem */
{ GC2235_8BIT, 0xfe, 0x80 },
{ GC2235_8BIT, 0xfe, 0x80 },
{ GC2235_8BIT, 0xfe, 0x80 },
{ GC2235_8BIT, 0xf2, 0x00 },
{ GC2235_8BIT, 0xf6, 0x00 },
{ GC2235_8BIT, 0xfc, 0x06 },
{ GC2235_8BIT, 0xf7, 0x15 },
{ GC2235_8BIT, 0xf8, 0x84 },
{ GC2235_8BIT, 0xf9, 0xfe },
{ GC2235_8BIT, 0xfa, 0x00 },
{ GC2235_8BIT, 0xfe, 0x00 },
/* Analog & cisctl */
{ GC2235_8BIT, 0x03, 0x04 },
{ GC2235_8BIT, 0x04, 0x9E },
{ GC2235_8BIT, 0x05, 0x00 },
{ GC2235_8BIT, 0x06, 0xfd },
{ GC2235_8BIT, 0x07, 0x00 },
{ GC2235_8BIT, 0x08, 0x14 },
{ GC2235_8BIT, 0x0a, 0x02 }, /* row start */
{ GC2235_8BIT, 0x0c, 0x00 }, /* col start */
{ GC2235_8BIT, 0x0d, 0x04 }, /* win height 1232 */
{ GC2235_8BIT, 0x0e, 0xd0 },
{ GC2235_8BIT, 0x0f, 0x06 }, /* win width: 1616 */
{ GC2235_8BIT, 0x10, 0x60 },
{ GC2235_8BIT, 0x17, 0x15 }, /* mirror flip */
{ GC2235_8BIT, 0x18, 0x1a },
{ GC2235_8BIT, 0x19, 0x06 },
{ GC2235_8BIT, 0x1a, 0x01 },
{ GC2235_8BIT, 0x1b, 0x4d },
{ GC2235_8BIT, 0x1e, 0x88 },
{ GC2235_8BIT, 0x1f, 0x48 },
{ GC2235_8BIT, 0x20, 0x03 },
{ GC2235_8BIT, 0x21, 0x7f },
{ GC2235_8BIT, 0x22, 0x83 },
{ GC2235_8BIT, 0x23, 0x42 },
{ GC2235_8BIT, 0x24, 0x16 },
{ GC2235_8BIT, 0x26, 0x01 }, /*analog gain*/
{ GC2235_8BIT, 0x27, 0x30 },
{ GC2235_8BIT, 0x3f, 0x00 }, /* PRC */
/* blk */
{ GC2235_8BIT, 0x40, 0xa3 },
{ GC2235_8BIT, 0x41, 0x82 },
{ GC2235_8BIT, 0x43, 0x20 },
{ GC2235_8BIT, 0x5e, 0x18 },
{ GC2235_8BIT, 0x5f, 0x18 },
{ GC2235_8BIT, 0x60, 0x18 },
{ GC2235_8BIT, 0x61, 0x18 },
{ GC2235_8BIT, 0x62, 0x18 },
{ GC2235_8BIT, 0x63, 0x18 },
{ GC2235_8BIT, 0x64, 0x18 },
{ GC2235_8BIT, 0x65, 0x18 },
{ GC2235_8BIT, 0x66, 0x20 },
{ GC2235_8BIT, 0x67, 0x20 },
{ GC2235_8BIT, 0x68, 0x20 },
{ GC2235_8BIT, 0x69, 0x20 },
/* Gain */
{ GC2235_8BIT, 0xb2, 0x00 },
{ GC2235_8BIT, 0xb3, 0x40 },
{ GC2235_8BIT, 0xb4, 0x40 },
{ GC2235_8BIT, 0xb5, 0x40 },
/* Dark sun */
{ GC2235_8BIT, 0xbc, 0x00 },
{ GC2235_8BIT, 0xfe, 0x03 },
{ GC2235_8BIT, 0x10, 0x01 }, /* disable mipi */
{ GC2235_8BIT, 0xfe, 0x00 }, /* switch to P0 */
{ GC2235_TOK_TERM, 0, 0 }
};
/*
* Register settings for various resolution
*/
#if ENABLE_NON_PREVIEW
static struct gc2235_reg const gc2235_1296_736_30fps[] = {
{ GC2235_8BIT, 0x8b, 0xa0 },
{ GC2235_8BIT, 0x8c, 0x02 },
{ GC2235_8BIT, 0x07, 0x01 }, /* VBI */
{ GC2235_8BIT, 0x08, 0x44 },
{ GC2235_8BIT, 0x09, 0x00 }, /* row start */
{ GC2235_8BIT, 0x0a, 0xf0 },
{ GC2235_8BIT, 0x0b, 0x00 }, /* col start */
{ GC2235_8BIT, 0x0c, 0xa0 },
{ GC2235_8BIT, 0x0d, 0x02 }, /* win height 736 */
{ GC2235_8BIT, 0x0e, 0xf0 },
{ GC2235_8BIT, 0x0f, 0x05 }, /* win width: 1296 */
{ GC2235_8BIT, 0x10, 0x20 },
{ GC2235_8BIT, 0x90, 0x01 },
{ GC2235_8BIT, 0x92, 0x08 },
{ GC2235_8BIT, 0x94, 0x08 },
{ GC2235_8BIT, 0x95, 0x02 }, /* crop win height 736 */
{ GC2235_8BIT, 0x96, 0xe0 },
{ GC2235_8BIT, 0x97, 0x05 }, /* crop win width 1296 */
{ GC2235_8BIT, 0x98, 0x10 },
/* mimi init */
{ GC2235_8BIT, 0xfe, 0x03 }, /* switch to P3 */
{ GC2235_8BIT, 0x01, 0x07 },
{ GC2235_8BIT, 0x02, 0x11 },
{ GC2235_8BIT, 0x03, 0x11 },
{ GC2235_8BIT, 0x06, 0x80 },
{ GC2235_8BIT, 0x11, 0x2b },
/* set mipi buffer */
{ GC2235_8BIT, 0x12, 0x54 }, /* val_low = (width * 10 / 8) & 0xFF */
{ GC2235_8BIT, 0x13, 0x06 }, /* val_high = (width * 10 / 8) >> 8 */
{ GC2235_8BIT, 0x15, 0x12 }, /* DPHY mode*/
{ GC2235_8BIT, 0x04, 0x10 },
{ GC2235_8BIT, 0x05, 0x00 },
{ GC2235_8BIT, 0x17, 0x01 },
{ GC2235_8BIT, 0x22, 0x01 },
{ GC2235_8BIT, 0x23, 0x05 },
{ GC2235_8BIT, 0x24, 0x10 },
{ GC2235_8BIT, 0x25, 0x10 },
{ GC2235_8BIT, 0x26, 0x02 },
{ GC2235_8BIT, 0x21, 0x10 },
{ GC2235_8BIT, 0x29, 0x01 },
{ GC2235_8BIT, 0x2a, 0x02 },
{ GC2235_8BIT, 0x2b, 0x02 },
{ GC2235_8BIT, 0x10, 0x01 }, /* disable mipi */
{ GC2235_8BIT, 0xfe, 0x00 }, /* switch to P0 */
{ GC2235_TOK_TERM, 0, 0 }
};
static struct gc2235_reg const gc2235_960_640_30fps[] = {
{ GC2235_8BIT, 0x8b, 0xa0 },
{ GC2235_8BIT, 0x8c, 0x02 },
{ GC2235_8BIT, 0x07, 0x02 }, /* VBI */
{ GC2235_8BIT, 0x08, 0xA4 },
{ GC2235_8BIT, 0x09, 0x01 }, /* row start */
{ GC2235_8BIT, 0x0a, 0x18 },
{ GC2235_8BIT, 0x0b, 0x01 }, /* col start */
{ GC2235_8BIT, 0x0c, 0x40 },
{ GC2235_8BIT, 0x0d, 0x02 }, /* win height 656 */
{ GC2235_8BIT, 0x0e, 0x90 },
{ GC2235_8BIT, 0x0f, 0x03 }, /* win width: 976 */
{ GC2235_8BIT, 0x10, 0xd0 },
{ GC2235_8BIT, 0x90, 0x01 },
{ GC2235_8BIT, 0x92, 0x02 },
{ GC2235_8BIT, 0x94, 0x06 },
{ GC2235_8BIT, 0x95, 0x02 }, /* crop win height 640 */
{ GC2235_8BIT, 0x96, 0x80 },
{ GC2235_8BIT, 0x97, 0x03 }, /* crop win width 960 */
{ GC2235_8BIT, 0x98, 0xc0 },
/* mimp init */
{ GC2235_8BIT, 0xfe, 0x03 }, /* switch to P3 */
{ GC2235_8BIT, 0x01, 0x07 },
{ GC2235_8BIT, 0x02, 0x11 },
{ GC2235_8BIT, 0x03, 0x11 },
{ GC2235_8BIT, 0x06, 0x80 },
{ GC2235_8BIT, 0x11, 0x2b },
/* set mipi buffer */
{ GC2235_8BIT, 0x12, 0xb0 }, /* val_low = (width * 10 / 8) & 0xFF */
{ GC2235_8BIT, 0x13, 0x04 }, /* val_high = (width * 10 / 8) >> 8 */
{ GC2235_8BIT, 0x15, 0x12 }, /* DPHY mode*/
{ GC2235_8BIT, 0x04, 0x10 },
{ GC2235_8BIT, 0x05, 0x00 },
{ GC2235_8BIT, 0x17, 0x01 },
{ GC2235_8BIT, 0x22, 0x01 },
{ GC2235_8BIT, 0x23, 0x05 },
{ GC2235_8BIT, 0x24, 0x10 },
{ GC2235_8BIT, 0x25, 0x10 },
{ GC2235_8BIT, 0x26, 0x02 },
{ GC2235_8BIT, 0x21, 0x10 },
{ GC2235_8BIT, 0x29, 0x01 },
{ GC2235_8BIT, 0x2a, 0x02 },
{ GC2235_8BIT, 0x2b, 0x02 },
{ GC2235_8BIT, 0x10, 0x01 }, /* disable mipi */
{ GC2235_8BIT, 0xfe, 0x00 }, /* switch to P0 */
{ GC2235_TOK_TERM, 0, 0 }
};
#endif
static struct gc2235_reg const gc2235_1600_900_30fps[] = {
{ GC2235_8BIT, 0x8b, 0xa0 },
{ GC2235_8BIT, 0x8c, 0x02 },
{ GC2235_8BIT, 0x0d, 0x03 }, /* win height 932 */
{ GC2235_8BIT, 0x0e, 0xa4 },
{ GC2235_8BIT, 0x0f, 0x06 }, /* win width: 1632 */
{ GC2235_8BIT, 0x10, 0x50 },
{ GC2235_8BIT, 0x90, 0x01 },
{ GC2235_8BIT, 0x92, 0x02 },
{ GC2235_8BIT, 0x94, 0x06 },
{ GC2235_8BIT, 0x95, 0x03 }, /* crop win height 900 */
{ GC2235_8BIT, 0x96, 0x84 },
{ GC2235_8BIT, 0x97, 0x06 }, /* crop win width 1600 */
{ GC2235_8BIT, 0x98, 0x40 },
/* mimi init */
{ GC2235_8BIT, 0xfe, 0x03 }, /* switch to P3 */
{ GC2235_8BIT, 0x01, 0x07 },
{ GC2235_8BIT, 0x02, 0x11 },
{ GC2235_8BIT, 0x03, 0x11 },
{ GC2235_8BIT, 0x06, 0x80 },
{ GC2235_8BIT, 0x11, 0x2b },
/* set mipi buffer */
{ GC2235_8BIT, 0x12, 0xd0 }, /* val_low = (width * 10 / 8) & 0xFF */
{ GC2235_8BIT, 0x13, 0x07 }, /* val_high = (width * 10 / 8) >> 8 */
{ GC2235_8BIT, 0x15, 0x12 }, /* DPHY mode*/
{ GC2235_8BIT, 0x04, 0x10 },
{ GC2235_8BIT, 0x05, 0x00 },
{ GC2235_8BIT, 0x17, 0x01 },
{ GC2235_8BIT, 0x22, 0x01 },
{ GC2235_8BIT, 0x23, 0x05 },
{ GC2235_8BIT, 0x24, 0x10 },
{ GC2235_8BIT, 0x25, 0x10 },
{ GC2235_8BIT, 0x26, 0x02 },
{ GC2235_8BIT, 0x21, 0x10 },
{ GC2235_8BIT, 0x29, 0x01 },
{ GC2235_8BIT, 0x2a, 0x02 },
{ GC2235_8BIT, 0x2b, 0x02 },
{ GC2235_8BIT, 0x10, 0x01 }, /* disable mipi */
{ GC2235_8BIT, 0xfe, 0x00 }, /* switch to P0 */
{ GC2235_TOK_TERM, 0, 0 }
};
static struct gc2235_reg const gc2235_1616_1082_30fps[] = {
{ GC2235_8BIT, 0x8b, 0xa0 },
{ GC2235_8BIT, 0x8c, 0x02 },
{ GC2235_8BIT, 0x0d, 0x04 }, /* win height 1232 */
{ GC2235_8BIT, 0x0e, 0xd0 },
{ GC2235_8BIT, 0x0f, 0x06 }, /* win width: 1616 */
{ GC2235_8BIT, 0x10, 0x50 },
{ GC2235_8BIT, 0x90, 0x01 },
{ GC2235_8BIT, 0x92, 0x4a },
{ GC2235_8BIT, 0x94, 0x00 },
{ GC2235_8BIT, 0x95, 0x04 }, /* crop win height 1082 */
{ GC2235_8BIT, 0x96, 0x3a },
{ GC2235_8BIT, 0x97, 0x06 }, /* crop win width 1616 */
{ GC2235_8BIT, 0x98, 0x50 },
/* mimp init */
{ GC2235_8BIT, 0xfe, 0x03 }, /* switch to P3 */
{ GC2235_8BIT, 0x01, 0x07 },
{ GC2235_8BIT, 0x02, 0x11 },
{ GC2235_8BIT, 0x03, 0x11 },
{ GC2235_8BIT, 0x06, 0x80 },
{ GC2235_8BIT, 0x11, 0x2b },
/* set mipi buffer */
{ GC2235_8BIT, 0x12, 0xe4 }, /* val_low = (width * 10 / 8) & 0xFF */
{ GC2235_8BIT, 0x13, 0x07 }, /* val_high = (width * 10 / 8) >> 8 */
{ GC2235_8BIT, 0x15, 0x12 }, /* DPHY mode*/
{ GC2235_8BIT, 0x04, 0x10 },
{ GC2235_8BIT, 0x05, 0x00 },
{ GC2235_8BIT, 0x17, 0x01 },
{ GC2235_8BIT, 0x22, 0x01 },
{ GC2235_8BIT, 0x23, 0x05 },
{ GC2235_8BIT, 0x24, 0x10 },
{ GC2235_8BIT, 0x25, 0x10 },
{ GC2235_8BIT, 0x26, 0x02 },
{ GC2235_8BIT, 0x21, 0x10 },
{ GC2235_8BIT, 0x29, 0x01 },
{ GC2235_8BIT, 0x2a, 0x02 },
{ GC2235_8BIT, 0x2b, 0x02 },
{ GC2235_8BIT, 0x10, 0x01 }, /* disable mipi */
{ GC2235_8BIT, 0xfe, 0x00 }, /* switch to P0 */
{ GC2235_TOK_TERM, 0, 0 }
};
static struct gc2235_reg const gc2235_1616_1216_30fps[] = {
{ GC2235_8BIT, 0x8b, 0xa0 },
{ GC2235_8BIT, 0x8c, 0x02 },
{ GC2235_8BIT, 0x0d, 0x04 }, /* win height 1232 */
{ GC2235_8BIT, 0x0e, 0xd0 },
{ GC2235_8BIT, 0x0f, 0x06 }, /* win width: 1616 */
{ GC2235_8BIT, 0x10, 0x50 },
{ GC2235_8BIT, 0x90, 0x01 },
{ GC2235_8BIT, 0x92, 0x02 },
{ GC2235_8BIT, 0x94, 0x00 },
{ GC2235_8BIT, 0x95, 0x04 }, /* crop win height 1216 */
{ GC2235_8BIT, 0x96, 0xc0 },
{ GC2235_8BIT, 0x97, 0x06 }, /* crop win width 1616 */
{ GC2235_8BIT, 0x98, 0x50 },
/* mimi init */
{ GC2235_8BIT, 0xfe, 0x03 }, /* switch to P3 */
{ GC2235_8BIT, 0x01, 0x07 },
{ GC2235_8BIT, 0x02, 0x11 },
{ GC2235_8BIT, 0x03, 0x11 },
{ GC2235_8BIT, 0x06, 0x80 },
{ GC2235_8BIT, 0x11, 0x2b },
/* set mipi buffer */
{ GC2235_8BIT, 0x12, 0xe4 }, /* val_low = (width * 10 / 8) & 0xFF */
{ GC2235_8BIT, 0x13, 0x07 }, /* val_high = (width * 10 / 8) >> 8 */
{ GC2235_8BIT, 0x15, 0x12 }, /* DPHY mode*/
{ GC2235_8BIT, 0x04, 0x10 },
{ GC2235_8BIT, 0x05, 0x00 },
{ GC2235_8BIT, 0x17, 0x01 },
{ GC2235_8BIT, 0x22, 0x01 },
{ GC2235_8BIT, 0x23, 0x05 },
{ GC2235_8BIT, 0x24, 0x10 },
{ GC2235_8BIT, 0x25, 0x10 },
{ GC2235_8BIT, 0x26, 0x02 },
{ GC2235_8BIT, 0x21, 0x10 },
{ GC2235_8BIT, 0x29, 0x01 },
{ GC2235_8BIT, 0x2a, 0x02 },
{ GC2235_8BIT, 0x2b, 0x02 },
{ GC2235_8BIT, 0x10, 0x01 }, /* disable mipi */
{ GC2235_8BIT, 0xfe, 0x00 }, /* switch to P0 */
{ GC2235_TOK_TERM, 0, 0 }
};
static struct gc2235_resolution gc2235_res_preview[] = {
{
.desc = "gc2235_1600_900_30fps",
.width = 1600,
.height = 900,
.pix_clk_freq = 30,
.fps = 30,
.used = 0,
.pixels_per_line = 2132,
.lines_per_frame = 1068,
.bin_factor_x = 0,
.bin_factor_y = 0,
.bin_mode = 0,
.skip_frames = 3,
.regs = gc2235_1600_900_30fps,
},
{
.desc = "gc2235_1600_1066_30fps",
.width = 1616,
.height = 1082,
.pix_clk_freq = 30,
.fps = 30,
.used = 0,
.pixels_per_line = 2132,
.lines_per_frame = 1368,
.bin_factor_x = 0,
.bin_factor_y = 0,
.bin_mode = 0,
.skip_frames = 3,
.regs = gc2235_1616_1082_30fps,
},
{
.desc = "gc2235_1600_1200_30fps",
.width = 1616,
.height = 1216,
.pix_clk_freq = 30,
.fps = 30,
.used = 0,
.pixels_per_line = 2132,
.lines_per_frame = 1368,
.bin_factor_x = 0,
.bin_factor_y = 0,
.bin_mode = 0,
.skip_frames = 3,
.regs = gc2235_1616_1216_30fps,
},
};
#define N_RES_PREVIEW (ARRAY_SIZE(gc2235_res_preview))
/*
* Disable non-preview configurations until the configuration selection is
* improved.
*/
#if ENABLE_NON_PREVIEW
static struct gc2235_resolution gc2235_res_still[] = {
{
.desc = "gc2235_1600_900_30fps",
.width = 1600,
.height = 900,
.pix_clk_freq = 30,
.fps = 30,
.used = 0,
.pixels_per_line = 2132,
.lines_per_frame = 1068,
.bin_factor_x = 0,
.bin_factor_y = 0,
.bin_mode = 0,
.skip_frames = 3,
.regs = gc2235_1600_900_30fps,
},
{
.desc = "gc2235_1600_1066_30fps",
.width = 1616,
.height = 1082,
.pix_clk_freq = 30,
.fps = 30,
.used = 0,
.pixels_per_line = 2132,
.lines_per_frame = 1368,
.bin_factor_x = 0,
.bin_factor_y = 0,
.bin_mode = 0,
.skip_frames = 3,
.regs = gc2235_1616_1082_30fps,
},
{
.desc = "gc2235_1600_1200_30fps",
.width = 1616,
.height = 1216,
.pix_clk_freq = 30,
.fps = 30,
.used = 0,
.pixels_per_line = 2132,
.lines_per_frame = 1368,
.bin_factor_x = 0,
.bin_factor_y = 0,
.bin_mode = 0,
.skip_frames = 3,
.regs = gc2235_1616_1216_30fps,
},
};
#define N_RES_STILL (ARRAY_SIZE(gc2235_res_still))
static struct gc2235_resolution gc2235_res_video[] = {
{
.desc = "gc2235_1296_736_30fps",
.width = 1296,
.height = 736,
.pix_clk_freq = 30,
.fps = 30,
.used = 0,
.pixels_per_line = 1828,
.lines_per_frame = 888,
.bin_factor_x = 0,
.bin_factor_y = 0,
.bin_mode = 0,
.skip_frames = 3,
.regs = gc2235_1296_736_30fps,
},
{
.desc = "gc2235_960_640_30fps",
.width = 960,
.height = 640,
.pix_clk_freq = 30,
.fps = 30,
.used = 0,
.pixels_per_line = 1492,
.lines_per_frame = 792,
.bin_factor_x = 0,
.bin_factor_y = 0,
.bin_mode = 0,
.skip_frames = 3,
.regs = gc2235_960_640_30fps,
},
};
#define N_RES_VIDEO (ARRAY_SIZE(gc2235_res_video))
#endif
static struct gc2235_resolution *gc2235_res = gc2235_res_preview;
static unsigned long N_RES = N_RES_PREVIEW;
#endif

1788
drivers/staging/media/atomisp/i2c/mt9m114.h
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858
drivers/staging/media/atomisp/i2c/ov2680.h
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@ -1,858 +0,0 @@
/*
* Support for OmniVision OV2680 5M camera sensor.
*
* Copyright (c) 2013 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
*/
#ifndef __OV2680_H__
#define __OV2680_H__
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/i2c.h>
#include <linux/delay.h>
#include <linux/videodev2.h>
#include <linux/spinlock.h>
#include <media/v4l2-subdev.h>
#include <media/v4l2-device.h>
#include <media/v4l2-ctrls.h>
#include <linux/v4l2-mediabus.h>
#include <media/media-entity.h>
#include "../include/linux/atomisp_platform.h"
/* Defines for register writes and register array processing */
#define I2C_MSG_LENGTH 0x2
#define I2C_RETRY_COUNT 5
#define OV2680_FOCAL_LENGTH_NUM 334 /*3.34mm*/
#define OV2680_FOCAL_LENGTH_DEM 100
#define OV2680_F_NUMBER_DEFAULT_NUM 24
#define OV2680_F_NUMBER_DEM 10
#define OV2680_BIN_FACTOR_MAX 4
#define MAX_FMTS 1
/* sensor_mode_data read_mode adaptation */
#define OV2680_READ_MODE_BINNING_ON 0x0400
#define OV2680_READ_MODE_BINNING_OFF 0x00
#define OV2680_INTEGRATION_TIME_MARGIN 8
#define OV2680_MAX_EXPOSURE_VALUE 0xFFF1
#define OV2680_MAX_GAIN_VALUE 0xFF
/*
* focal length bits definition:
* bits 31-16: numerator, bits 15-0: denominator
*/
#define OV2680_FOCAL_LENGTH_DEFAULT 0x1B70064
/*
* current f-number bits definition:
* bits 31-16: numerator, bits 15-0: denominator
*/
#define OV2680_F_NUMBER_DEFAULT 0x18000a
/*
* f-number range bits definition:
* bits 31-24: max f-number numerator
* bits 23-16: max f-number denominator
* bits 15-8: min f-number numerator
* bits 7-0: min f-number denominator
*/
#define OV2680_F_NUMBER_RANGE 0x180a180a
#define OV2680_ID 0x2680
#define OV2680_FINE_INTG_TIME_MIN 0
#define OV2680_FINE_INTG_TIME_MAX_MARGIN 0
#define OV2680_COARSE_INTG_TIME_MIN 1
#define OV2680_COARSE_INTG_TIME_MAX_MARGIN 6
/*
* OV2680 System control registers
*/
#define OV2680_SW_SLEEP 0x0100
#define OV2680_SW_RESET 0x0103
#define OV2680_SW_STREAM 0x0100
#define OV2680_SC_CMMN_CHIP_ID_H 0x300A
#define OV2680_SC_CMMN_CHIP_ID_L 0x300B
#define OV2680_SC_CMMN_SCCB_ID 0x302B /* 0x300C*/
#define OV2680_SC_CMMN_SUB_ID 0x302A /* process, version*/
#define OV2680_GROUP_ACCESS 0x3208 /*Bit[7:4] Group control, Bit[3:0] Group ID*/
#define OV2680_EXPOSURE_H 0x3500 /*Bit[3:0] Bit[19:16] of exposure, remaining 16 bits lies in Reg0x3501&Reg0x3502*/
#define OV2680_EXPOSURE_M 0x3501
#define OV2680_EXPOSURE_L 0x3502
#define OV2680_AGC_H 0x350A /*Bit[1:0] means Bit[9:8] of gain*/
#define OV2680_AGC_L 0x350B /*Bit[7:0] of gain*/
#define OV2680_HORIZONTAL_START_H 0x3800 /*Bit[11:8]*/
#define OV2680_HORIZONTAL_START_L 0x3801 /*Bit[7:0]*/
#define OV2680_VERTICAL_START_H 0x3802 /*Bit[11:8]*/
#define OV2680_VERTICAL_START_L 0x3803 /*Bit[7:0]*/
#define OV2680_HORIZONTAL_END_H 0x3804 /*Bit[11:8]*/
#define OV2680_HORIZONTAL_END_L 0x3805 /*Bit[7:0]*/
#define OV2680_VERTICAL_END_H 0x3806 /*Bit[11:8]*/
#define OV2680_VERTICAL_END_L 0x3807 /*Bit[7:0]*/
#define OV2680_HORIZONTAL_OUTPUT_SIZE_H 0x3808 /*Bit[3:0]*/
#define OV2680_HORIZONTAL_OUTPUT_SIZE_L 0x3809 /*Bit[7:0]*/
#define OV2680_VERTICAL_OUTPUT_SIZE_H 0x380a /*Bit[3:0]*/
#define OV2680_VERTICAL_OUTPUT_SIZE_L 0x380b /*Bit[7:0]*/
#define OV2680_TIMING_HTS_H 0x380C /*High 8-bit, and low 8-bit HTS address is 0x380d*/
#define OV2680_TIMING_HTS_L 0x380D /*High 8-bit, and low 8-bit HTS address is 0x380d*/
#define OV2680_TIMING_VTS_H 0x380e /*High 8-bit, and low 8-bit HTS address is 0x380f*/
#define OV2680_TIMING_VTS_L 0x380f /*High 8-bit, and low 8-bit HTS address is 0x380f*/
#define OV2680_FRAME_OFF_NUM 0x4202
/*Flip/Mirror*/
#define OV2680_FLIP_REG 0x3820
#define OV2680_MIRROR_REG 0x3821
#define OV2680_FLIP_BIT 1
#define OV2680_MIRROR_BIT 2
#define OV2680_FLIP_MIRROR_BIT_ENABLE 4
#define OV2680_MWB_RED_GAIN_H 0x5004/*0x3400*/
#define OV2680_MWB_GREEN_GAIN_H 0x5006/*0x3402*/
#define OV2680_MWB_BLUE_GAIN_H 0x5008/*0x3404*/
#define OV2680_MWB_GAIN_MAX 0x0fff
#define OV2680_START_STREAMING 0x01
#define OV2680_STOP_STREAMING 0x00
#define OV2680_INVALID_CONFIG 0xffffffff
struct regval_list {
u16 reg_num;
u8 value;
};
struct ov2680_resolution {
u8 *desc;
const struct ov2680_reg *regs;
int res;
int width;
int height;
int fps;
int pix_clk_freq;
u32 skip_frames;
u16 pixels_per_line;
u16 lines_per_frame;
u8 bin_factor_x;
u8 bin_factor_y;
u8 bin_mode;
bool used;
};
struct ov2680_format {
u8 *desc;
u32 pixelformat;
struct ov2680_reg *regs;
};
/*
* ov2680 device structure.
*/
struct ov2680_device {
struct v4l2_subdev sd;
struct media_pad pad;
struct v4l2_mbus_framefmt format;
struct mutex input_lock;
struct v4l2_ctrl_handler ctrl_handler;
struct camera_sensor_platform_data *platform_data;
int vt_pix_clk_freq_mhz;
int fmt_idx;
int run_mode;
u8 res;
u8 type;
};
enum ov2680_tok_type {
OV2680_8BIT = 0x0001,
OV2680_16BIT = 0x0002,
OV2680_32BIT = 0x0004,
OV2680_TOK_TERM = 0xf000, /* terminating token for reg list */
OV2680_TOK_DELAY = 0xfe00, /* delay token for reg list */
OV2680_TOK_MASK = 0xfff0
};
/**
* struct ov2680_reg - MI sensor register format
* @type: type of the register
* @reg: 16-bit offset to register
* @val: 8/16/32-bit register value
*
* Define a structure for sensor register initialization values
*/
struct ov2680_reg {
enum ov2680_tok_type type;
u16 reg;
u32 val; /* @set value for read/mod/write, @mask */
};
#define to_ov2680_sensor(x) container_of(x, struct ov2680_device, sd)
#define OV2680_MAX_WRITE_BUF_SIZE 30
struct ov2680_write_buffer {
u16 addr;
u8 data[OV2680_MAX_WRITE_BUF_SIZE];
};
struct ov2680_write_ctrl {
int index;
struct ov2680_write_buffer buffer;
};
static struct ov2680_reg const ov2680_global_setting[] = {
{OV2680_8BIT, 0x0103, 0x01},
{OV2680_8BIT, 0x3002, 0x00},
{OV2680_8BIT, 0x3016, 0x1c},
{OV2680_8BIT, 0x3018, 0x44},
{OV2680_8BIT, 0x3020, 0x00},
{OV2680_8BIT, 0x3080, 0x02},
{OV2680_8BIT, 0x3082, 0x45},
{OV2680_8BIT, 0x3084, 0x09},
{OV2680_8BIT, 0x3085, 0x04},
{OV2680_8BIT, 0x3503, 0x03},
{OV2680_8BIT, 0x350b, 0x36},
{OV2680_8BIT, 0x3600, 0xb4},
{OV2680_8BIT, 0x3603, 0x39},
{OV2680_8BIT, 0x3604, 0x24},
{OV2680_8BIT, 0x3605, 0x00},
{OV2680_8BIT, 0x3620, 0x26},
{OV2680_8BIT, 0x3621, 0x37},
{OV2680_8BIT, 0x3622, 0x04},
{OV2680_8BIT, 0x3628, 0x00},
{OV2680_8BIT, 0x3705, 0x3c},
{OV2680_8BIT, 0x370c, 0x50},
{OV2680_8BIT, 0x370d, 0xc0},
{OV2680_8BIT, 0x3718, 0x88},
{OV2680_8BIT, 0x3720, 0x00},
{OV2680_8BIT, 0x3721, 0x00},
{OV2680_8BIT, 0x3722, 0x00},
{OV2680_8BIT, 0x3723, 0x00},
{OV2680_8BIT, 0x3738, 0x00},
{OV2680_8BIT, 0x3717, 0x58},
{OV2680_8BIT, 0x3781, 0x80},
{OV2680_8BIT, 0x3789, 0x60},
{OV2680_8BIT, 0x3800, 0x00},
{OV2680_8BIT, 0x3819, 0x04},
{OV2680_8BIT, 0x4000, 0x81},
{OV2680_8BIT, 0x4001, 0x40},
{OV2680_8BIT, 0x4602, 0x02},
{OV2680_8BIT, 0x481f, 0x36},
{OV2680_8BIT, 0x4825, 0x36},
{OV2680_8BIT, 0x4837, 0x18},
{OV2680_8BIT, 0x5002, 0x30},
{OV2680_8BIT, 0x5004, 0x04},//manual awb 1x
{OV2680_8BIT, 0x5005, 0x00},
{OV2680_8BIT, 0x5006, 0x04},
{OV2680_8BIT, 0x5007, 0x00},
{OV2680_8BIT, 0x5008, 0x04},
{OV2680_8BIT, 0x5009, 0x00},
{OV2680_8BIT, 0x5080, 0x00},
{OV2680_8BIT, 0x3701, 0x64}, //add on 14/05/13
{OV2680_8BIT, 0x3784, 0x0c}, //based OV2680_R1A_AM10.ovt add on 14/06/13
{OV2680_8BIT, 0x5780, 0x3e}, //based OV2680_R1A_AM10.ovt,Adjust DPC setting (57xx) on 14/06/13
{OV2680_8BIT, 0x5781, 0x0f},
{OV2680_8BIT, 0x5782, 0x04},
{OV2680_8BIT, 0x5783, 0x02},
{OV2680_8BIT, 0x5784, 0x01},
{OV2680_8BIT, 0x5785, 0x01},
{OV2680_8BIT, 0x5786, 0x00},
{OV2680_8BIT, 0x5787, 0x04},
{OV2680_8BIT, 0x5788, 0x02},
{OV2680_8BIT, 0x5789, 0x00},
{OV2680_8BIT, 0x578a, 0x01},
{OV2680_8BIT, 0x578b, 0x02},
{OV2680_8BIT, 0x578c, 0x03},
{OV2680_8BIT, 0x578d, 0x03},
{OV2680_8BIT, 0x578e, 0x08},
{OV2680_8BIT, 0x578f, 0x0c},
{OV2680_8BIT, 0x5790, 0x08},
{OV2680_8BIT, 0x5791, 0x04},
{OV2680_8BIT, 0x5792, 0x00},
{OV2680_8BIT, 0x5793, 0x00},
{OV2680_8BIT, 0x5794, 0x03}, //based OV2680_R1A_AM10.ovt,Adjust DPC setting (57xx) on 14/06/13
{OV2680_8BIT, 0x0100, 0x00}, //stream off
{OV2680_TOK_TERM, 0, 0}
};
#if 0 /* None of the definitions below are used currently */
/*
* 176x144 30fps VBlanking 1lane 10Bit (binning)
*/
static struct ov2680_reg const ov2680_QCIF_30fps[] = {
{OV2680_8BIT, 0x3086, 0x01},
{OV2680_8BIT, 0x3501, 0x24},
{OV2680_8BIT, 0x3502, 0x40},
{OV2680_8BIT, 0x370a, 0x23},
{OV2680_8BIT, 0x3801, 0xa0},
{OV2680_8BIT, 0x3802, 0x00},
{OV2680_8BIT, 0x3803, 0x78},
{OV2680_8BIT, 0x3804, 0x05},
{OV2680_8BIT, 0x3805, 0xaf},
{OV2680_8BIT, 0x3806, 0x04},
{OV2680_8BIT, 0x3807, 0x47},
{OV2680_8BIT, 0x3808, 0x00},
{OV2680_8BIT, 0x3809, 0xC0},
{OV2680_8BIT, 0x380a, 0x00},
{OV2680_8BIT, 0x380b, 0xa0},
{OV2680_8BIT, 0x380c, 0x06},
{OV2680_8BIT, 0x380d, 0xb0},
{OV2680_8BIT, 0x380e, 0x02},
{OV2680_8BIT, 0x380f, 0x84},
{OV2680_8BIT, 0x3810, 0x00},
{OV2680_8BIT, 0x3811, 0x04},
{OV2680_8BIT, 0x3812, 0x00},
{OV2680_8BIT, 0x3813, 0x04},
{OV2680_8BIT, 0x3814, 0x31},
{OV2680_8BIT, 0x3815, 0x31},
{OV2680_8BIT, 0x4000, 0x81},
{OV2680_8BIT, 0x4001, 0x40},
{OV2680_8BIT, 0x4008, 0x00},
{OV2680_8BIT, 0x4009, 0x03},
{OV2680_8BIT, 0x5081, 0x41},
{OV2680_8BIT, 0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11
{OV2680_8BIT, 0x5704, 0x10},
{OV2680_8BIT, 0x5705, 0xa0},
{OV2680_8BIT, 0x5706, 0x0c},
{OV2680_8BIT, 0x5707, 0x78},
{OV2680_8BIT, 0x3820, 0xc2},
{OV2680_8BIT, 0x3821, 0x01},
// {OV2680_8BIT, 0x5090, 0x0c},
{OV2680_TOK_TERM, 0, 0}
};
/*
* 352x288 30fps VBlanking 1lane 10Bit (binning)
*/
static struct ov2680_reg const ov2680_CIF_30fps[] = {
{OV2680_8BIT, 0x3086, 0x01},
{OV2680_8BIT, 0x3501, 0x24},
{OV2680_8BIT, 0x3502, 0x40},
{OV2680_8BIT, 0x370a, 0x23},
{OV2680_8BIT, 0x3801, 0xa0},
{OV2680_8BIT, 0x3802, 0x00},
{OV2680_8BIT, 0x3803, 0x78},
{OV2680_8BIT, 0x3804, 0x03},
{OV2680_8BIT, 0x3805, 0x8f},
{OV2680_8BIT, 0x3806, 0x02},
{OV2680_8BIT, 0x3807, 0xe7},
{OV2680_8BIT, 0x3808, 0x01},
{OV2680_8BIT, 0x3809, 0x70},
{OV2680_8BIT, 0x380a, 0x01},
{OV2680_8BIT, 0x380b, 0x30},
{OV2680_8BIT, 0x380c, 0x06},
{OV2680_8BIT, 0x380d, 0xb0},
{OV2680_8BIT, 0x380e, 0x02},
{OV2680_8BIT, 0x380f, 0x84},
{OV2680_8BIT, 0x3810, 0x00},
{OV2680_8BIT, 0x3811, 0x04},
{OV2680_8BIT, 0x3812, 0x00},
{OV2680_8BIT, 0x3813, 0x04},
{OV2680_8BIT, 0x3814, 0x31},
{OV2680_8BIT, 0x3815, 0x31},
{OV2680_8BIT, 0x4008, 0x00},
{OV2680_8BIT, 0x4009, 0x03},
{OV2680_8BIT, 0x5081, 0x41},
{OV2680_8BIT, 0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11
{OV2680_8BIT, 0x5704, 0x10},
{OV2680_8BIT, 0x5705, 0xa0},
{OV2680_8BIT, 0x5706, 0x0c},
{OV2680_8BIT, 0x5707, 0x78},
{OV2680_8BIT, 0x3820, 0xc2},
{OV2680_8BIT, 0x3821, 0x01},
// {OV2680_8BIT, 0x5090, 0x0c},
{OV2680_TOK_TERM, 0, 0}
};
/*
* 336x256 30fps VBlanking 1lane 10Bit (binning)
*/
static struct ov2680_reg const ov2680_QVGA_30fps[] = {
{OV2680_8BIT, 0x3086, 0x01},
{OV2680_8BIT, 0x3501, 0x24},
{OV2680_8BIT, 0x3502, 0x40},
{OV2680_8BIT, 0x370a, 0x23},
{OV2680_8BIT, 0x3801, 0xa0},
{OV2680_8BIT, 0x3802, 0x00},
{OV2680_8BIT, 0x3803, 0x78},
{OV2680_8BIT, 0x3804, 0x03},
{OV2680_8BIT, 0x3805, 0x4f},
{OV2680_8BIT, 0x3806, 0x02},
{OV2680_8BIT, 0x3807, 0x87},
{OV2680_8BIT, 0x3808, 0x01},
{OV2680_8BIT, 0x3809, 0x50},
{OV2680_8BIT, 0x380a, 0x01},
{OV2680_8BIT, 0x380b, 0x00},
{OV2680_8BIT, 0x380c, 0x06},
{OV2680_8BIT, 0x380d, 0xb0},
{OV2680_8BIT, 0x380e, 0x02},
{OV2680_8BIT, 0x380f, 0x84},
{OV2680_8BIT, 0x3810, 0x00},
{OV2680_8BIT, 0x3811, 0x04},
{OV2680_8BIT, 0x3812, 0x00},
{OV2680_8BIT, 0x3813, 0x04},
{OV2680_8BIT, 0x3814, 0x31},
{OV2680_8BIT, 0x3815, 0x31},
{OV2680_8BIT, 0x4008, 0x00},
{OV2680_8BIT, 0x4009, 0x03},
{OV2680_8BIT, 0x5081, 0x41},
{OV2680_8BIT, 0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11
{OV2680_8BIT, 0x5704, 0x10},
{OV2680_8BIT, 0x5705, 0xa0},
{OV2680_8BIT, 0x5706, 0x0c},
{OV2680_8BIT, 0x5707, 0x78},
{OV2680_8BIT, 0x3820, 0xc2},
{OV2680_8BIT, 0x3821, 0x01},
// {OV2680_8BIT, 0x5090, 0x0c},
{OV2680_TOK_TERM, 0, 0}
};
/*
* 656x496 30fps VBlanking 1lane 10Bit (binning)
*/
static struct ov2680_reg const ov2680_656x496_30fps[] = {
{OV2680_8BIT, 0x3086, 0x01},
{OV2680_8BIT, 0x3501, 0x24},
{OV2680_8BIT, 0x3502, 0x40},
{OV2680_8BIT, 0x370a, 0x23},
{OV2680_8BIT, 0x3801, 0xa0},
{OV2680_8BIT, 0x3802, 0x00},
{OV2680_8BIT, 0x3803, 0x78},
{OV2680_8BIT, 0x3804, 0x05},
{OV2680_8BIT, 0x3805, 0xcf},
{OV2680_8BIT, 0x3806, 0x04},
{OV2680_8BIT, 0x3807, 0x67},
{OV2680_8BIT, 0x3808, 0x02},
{OV2680_8BIT, 0x3809, 0x90},
{OV2680_8BIT, 0x380a, 0x01},
{OV2680_8BIT, 0x380b, 0xf0},
{OV2680_8BIT, 0x380c, 0x06},
{OV2680_8BIT, 0x380d, 0xb0},
{OV2680_8BIT, 0x380e, 0x02},
{OV2680_8BIT, 0x380f, 0x84},
{OV2680_8BIT, 0x3810, 0x00},
{OV2680_8BIT, 0x3811, 0x04},
{OV2680_8BIT, 0x3812, 0x00},
{OV2680_8BIT, 0x3813, 0x04},
{OV2680_8BIT, 0x3814, 0x31},
{OV2680_8BIT, 0x3815, 0x31},
{OV2680_8BIT, 0x4008, 0x00},
{OV2680_8BIT, 0x4009, 0x03},
{OV2680_8BIT, 0x5081, 0x41},
{OV2680_8BIT, 0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11
{OV2680_8BIT, 0x5704, 0x10},
{OV2680_8BIT, 0x5705, 0xa0},
{OV2680_8BIT, 0x5706, 0x0c},
{OV2680_8BIT, 0x5707, 0x78},
{OV2680_8BIT, 0x3820, 0xc2},
{OV2680_8BIT, 0x3821, 0x01},
// {OV2680_8BIT, 0x5090, 0x0c},
{OV2680_TOK_TERM, 0, 0}
};
/*
* 800x600 30fps VBlanking 1lane 10Bit (binning)
*/
static struct ov2680_reg const ov2680_720x592_30fps[] = {
{OV2680_8BIT, 0x3086, 0x01},
{OV2680_8BIT, 0x3501, 0x26},
{OV2680_8BIT, 0x3502, 0x40},
{OV2680_8BIT, 0x370a, 0x23},
{OV2680_8BIT, 0x3801, 0x00}, // X_ADDR_START;
{OV2680_8BIT, 0x3802, 0x00},
{OV2680_8BIT, 0x3803, 0x00}, // Y_ADDR_START;
{OV2680_8BIT, 0x3804, 0x05},
{OV2680_8BIT, 0x3805, 0xaf}, // X_ADDR_END;
{OV2680_8BIT, 0x3806, 0x04},
{OV2680_8BIT, 0x3807, 0xaf}, // Y_ADDR_END;
{OV2680_8BIT, 0x3808, 0x02},
{OV2680_8BIT, 0x3809, 0xd0}, // X_OUTPUT_SIZE;
{OV2680_8BIT, 0x380a, 0x02},
{OV2680_8BIT, 0x380b, 0x50}, // Y_OUTPUT_SIZE;
{OV2680_8BIT, 0x380c, 0x06},
{OV2680_8BIT, 0x380d, 0xac}, // HTS;
{OV2680_8BIT, 0x380e, 0x02},
{OV2680_8BIT, 0x380f, 0x84}, // VTS;
{OV2680_8BIT, 0x3810, 0x00},
{OV2680_8BIT, 0x3811, 0x00},
{OV2680_8BIT, 0x3812, 0x00},
{OV2680_8BIT, 0x3813, 0x00},
{OV2680_8BIT, 0x3814, 0x31},
{OV2680_8BIT, 0x3815, 0x31},
{OV2680_8BIT, 0x4008, 0x00},
{OV2680_8BIT, 0x4009, 0x03},
{OV2680_8BIT, 0x5708, 0x00},
{OV2680_8BIT, 0x5704, 0x02},
{OV2680_8BIT, 0x5705, 0xd0}, // X_WIN;
{OV2680_8BIT, 0x5706, 0x02},
{OV2680_8BIT, 0x5707, 0x50}, // Y_WIN;
{OV2680_8BIT, 0x3820, 0xc2}, // FLIP_FORMAT;
{OV2680_8BIT, 0x3821, 0x01}, // MIRROR_FORMAT;
{OV2680_8BIT, 0x5090, 0x00}, // PRE ISP CTRL16, default value is 0x0C;
// BIT[3]: Mirror order, BG or GB;
// BIT[2]: Flip order, BR or RB;
{OV2680_8BIT, 0x5081, 0x41},
{OV2680_TOK_TERM, 0, 0}
};
/*
* 800x600 30fps VBlanking 1lane 10Bit (binning)
*/
static struct ov2680_reg const ov2680_800x600_30fps[] = {
{OV2680_8BIT, 0x3086, 0x01},
{OV2680_8BIT, 0x3501, 0x26},
{OV2680_8BIT, 0x3502, 0x40},
{OV2680_8BIT, 0x370a, 0x23},
{OV2680_8BIT, 0x3801, 0x00},
{OV2680_8BIT, 0x3802, 0x00},
{OV2680_8BIT, 0x3803, 0x00},
{OV2680_8BIT, 0x3804, 0x06},
{OV2680_8BIT, 0x3805, 0x4f},
{OV2680_8BIT, 0x3806, 0x04},
{OV2680_8BIT, 0x3807, 0xbf},
{OV2680_8BIT, 0x3808, 0x03},
{OV2680_8BIT, 0x3809, 0x20},
{OV2680_8BIT, 0x380a, 0x02},
{OV2680_8BIT, 0x380b, 0x58},
{OV2680_8BIT, 0x380c, 0x06},
{OV2680_8BIT, 0x380d, 0xac},
{OV2680_8BIT, 0x380e, 0x02},
{OV2680_8BIT, 0x380f, 0x84},
{OV2680_8BIT, 0x3810, 0x00},
{OV2680_8BIT, 0x3811, 0x00},
{OV2680_8BIT, 0x3812, 0x00},
{OV2680_8BIT, 0x3813, 0x00},
{OV2680_8BIT, 0x3814, 0x31},
{OV2680_8BIT, 0x3815, 0x31},
{OV2680_8BIT, 0x5708, 0x00},
{OV2680_8BIT, 0x5704, 0x03},
{OV2680_8BIT, 0x5705, 0x20},
{OV2680_8BIT, 0x5706, 0x02},
{OV2680_8BIT, 0x5707, 0x58},
{OV2680_8BIT, 0x3820, 0xc2},
{OV2680_8BIT, 0x3821, 0x01},
{OV2680_8BIT, 0x5090, 0x00},
{OV2680_8BIT, 0x4008, 0x00},
{OV2680_8BIT, 0x4009, 0x03},
{OV2680_8BIT, 0x5081, 0x41},
{OV2680_TOK_TERM, 0, 0}
};
/*
* 720p=1280*720 30fps VBlanking 1lane 10Bit (no-Scaling)
*/
static struct ov2680_reg const ov2680_720p_30fps[] = {
{OV2680_8BIT, 0x3086, 0x00},
{OV2680_8BIT, 0x3501, 0x48},
{OV2680_8BIT, 0x3502, 0xe0},
{OV2680_8BIT, 0x370a, 0x21},
{OV2680_8BIT, 0x3801, 0xa0},
{OV2680_8BIT, 0x3802, 0x00},
{OV2680_8BIT, 0x3803, 0xf2},
{OV2680_8BIT, 0x3804, 0x05},
{OV2680_8BIT, 0x3805, 0xbf},
{OV2680_8BIT, 0x3806, 0x03},
{OV2680_8BIT, 0x3807, 0xdd},
{OV2680_8BIT, 0x3808, 0x05},
{OV2680_8BIT, 0x3809, 0x10},
{OV2680_8BIT, 0x380a, 0x02},
{OV2680_8BIT, 0x380b, 0xe0},
{OV2680_8BIT, 0x380c, 0x06},
{OV2680_8BIT, 0x380d, 0xa8},
{OV2680_8BIT, 0x380e, 0x05},
{OV2680_8BIT, 0x380f, 0x0e},
{OV2680_8BIT, 0x3810, 0x00},
{OV2680_8BIT, 0x3811, 0x08},
{OV2680_8BIT, 0x3812, 0x00},
{OV2680_8BIT, 0x3813, 0x06},
{OV2680_8BIT, 0x3814, 0x11},
{OV2680_8BIT, 0x3815, 0x11},
{OV2680_8BIT, 0x4008, 0x02},
{OV2680_8BIT, 0x4009, 0x09},
{OV2680_8BIT, 0x5081, 0x41},
{OV2680_8BIT, 0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11
{OV2680_8BIT, 0x5704, 0x10},
{OV2680_8BIT, 0x5705, 0xa0},
{OV2680_8BIT, 0x5706, 0x0c},
{OV2680_8BIT, 0x5707, 0x78},
{OV2680_8BIT, 0x3820, 0xc0},
{OV2680_8BIT, 0x3821, 0x00},
// {OV2680_8BIT, 0x5090, 0x0c},
{OV2680_TOK_TERM, 0, 0}
};
/*
* 1296x976 30fps VBlanking 1lane 10Bit(no-scaling)
*/
static struct ov2680_reg const ov2680_1296x976_30fps[] = {
{OV2680_8BIT, 0x3086, 0x00},
{OV2680_8BIT, 0x3501, 0x48},
{OV2680_8BIT, 0x3502, 0xe0},
{OV2680_8BIT, 0x370a, 0x21},
{OV2680_8BIT, 0x3801, 0xa0},
{OV2680_8BIT, 0x3802, 0x00},
{OV2680_8BIT, 0x3803, 0x78},
{OV2680_8BIT, 0x3804, 0x05},
{OV2680_8BIT, 0x3805, 0xbf},
{OV2680_8BIT, 0x3806, 0x04},
{OV2680_8BIT, 0x3807, 0x57},
{OV2680_8BIT, 0x3808, 0x05},
{OV2680_8BIT, 0x3809, 0x10},
{OV2680_8BIT, 0x380a, 0x03},
{OV2680_8BIT, 0x380b, 0xd0},
{OV2680_8BIT, 0x380c, 0x06},
{OV2680_8BIT, 0x380d, 0xa8},
{OV2680_8BIT, 0x380e, 0x05},
{OV2680_8BIT, 0x380f, 0x0e},
{OV2680_8BIT, 0x3810, 0x00},
{OV2680_8BIT, 0x3811, 0x08},
{OV2680_8BIT, 0x3812, 0x00},
{OV2680_8BIT, 0x3813, 0x08},
{OV2680_8BIT, 0x3814, 0x11},
{OV2680_8BIT, 0x3815, 0x11},
{OV2680_8BIT, 0x4008, 0x02},
{OV2680_8BIT, 0x4009, 0x09},
{OV2680_8BIT, 0x5081, 0x41},
{OV2680_8BIT, 0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11
{OV2680_8BIT, 0x5704, 0x10},
{OV2680_8BIT, 0x5705, 0xa0},
{OV2680_8BIT, 0x5706, 0x0c},
{OV2680_8BIT, 0x5707, 0x78},
{OV2680_8BIT, 0x3820, 0xc0},
{OV2680_8BIT, 0x3821, 0x00}, //miror/flip
// {OV2680_8BIT, 0x5090, 0x0c},
{OV2680_TOK_TERM, 0, 0}
};
/*
* 1456*1096 30fps VBlanking 1lane 10bit(no-scaling)
*/
static struct ov2680_reg const ov2680_1456x1096_30fps[]= {
{OV2680_8BIT, 0x3086, 0x00},
{OV2680_8BIT, 0x3501, 0x48},
{OV2680_8BIT, 0x3502, 0xe0},
{OV2680_8BIT, 0x370a, 0x21},
{OV2680_8BIT, 0x3801, 0x90},
{OV2680_8BIT, 0x3802, 0x00},
{OV2680_8BIT, 0x3803, 0x78},
{OV2680_8BIT, 0x3804, 0x06},
{OV2680_8BIT, 0x3805, 0x4f},
{OV2680_8BIT, 0x3806, 0x04},
{OV2680_8BIT, 0x3807, 0xC0},
{OV2680_8BIT, 0x3808, 0x05},
{OV2680_8BIT, 0x3809, 0xb0},
{OV2680_8BIT, 0x380a, 0x04},
{OV2680_8BIT, 0x380b, 0x48},
{OV2680_8BIT, 0x380c, 0x06},
{OV2680_8BIT, 0x380d, 0xa8},
{OV2680_8BIT, 0x380e, 0x05},
{OV2680_8BIT, 0x380f, 0x0e},
{OV2680_8BIT, 0x3810, 0x00},
{OV2680_8BIT, 0x3811, 0x08},
{OV2680_8BIT, 0x3812, 0x00},
{OV2680_8BIT, 0x3813, 0x00},
{OV2680_8BIT, 0x3814, 0x11},
{OV2680_8BIT, 0x3815, 0x11},
{OV2680_8BIT, 0x4008, 0x02},
{OV2680_8BIT, 0x4009, 0x09},
{OV2680_8BIT, 0x5081, 0x41},
{OV2680_8BIT, 0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11
{OV2680_8BIT, 0x5704, 0x10},
{OV2680_8BIT, 0x5705, 0xa0},
{OV2680_8BIT, 0x5706, 0x0c},
{OV2680_8BIT, 0x5707, 0x78},
{OV2680_8BIT, 0x3820, 0xc0},
{OV2680_8BIT, 0x3821, 0x00},
// {OV2680_8BIT, 0x5090, 0x0c},
{OV2680_TOK_TERM, 0, 0}
};
#endif
/*
*1616x916 30fps VBlanking 1lane 10bit
*/
static struct ov2680_reg const ov2680_1616x916_30fps[] = {
{OV2680_8BIT, 0x3086, 0x00},
{OV2680_8BIT, 0x3501, 0x48},
{OV2680_8BIT, 0x3502, 0xe0},
{OV2680_8BIT, 0x370a, 0x21},
{OV2680_8BIT, 0x3801, 0x00},
{OV2680_8BIT, 0x3802, 0x00},
{OV2680_8BIT, 0x3803, 0x96},
{OV2680_8BIT, 0x3804, 0x06},
{OV2680_8BIT, 0x3805, 0x4f},
{OV2680_8BIT, 0x3806, 0x04},
{OV2680_8BIT, 0x3807, 0x39},
{OV2680_8BIT, 0x3808, 0x06},
{OV2680_8BIT, 0x3809, 0x50},
{OV2680_8BIT, 0x380a, 0x03},
{OV2680_8BIT, 0x380b, 0x94},
{OV2680_8BIT, 0x380c, 0x06},
{OV2680_8BIT, 0x380d, 0xa8},
{OV2680_8BIT, 0x380e, 0x05},
{OV2680_8BIT, 0x380f, 0x0e},
{OV2680_8BIT, 0x3810, 0x00},
{OV2680_8BIT, 0x3811, 0x00},
{OV2680_8BIT, 0x3812, 0x00},
{OV2680_8BIT, 0x3813, 0x08},
{OV2680_8BIT, 0x3814, 0x11},
{OV2680_8BIT, 0x3815, 0x11},
{OV2680_8BIT, 0x4008, 0x02},
{OV2680_8BIT, 0x4009, 0x09},
{OV2680_8BIT, 0x5081, 0x41},
{OV2680_8BIT, 0x5708, 0x01}, //add for full size flip off and mirror off 2014/09/11
{OV2680_8BIT, 0x5704, 0x06},
{OV2680_8BIT, 0x5705, 0x50},
{OV2680_8BIT, 0x5706, 0x03},
{OV2680_8BIT, 0x5707, 0x94},
{OV2680_8BIT, 0x3820, 0xc0},
{OV2680_8BIT, 0x3821, 0x00},
// {OV2680_8BIT, 0x5090, 0x0C},
{OV2680_TOK_TERM, 0, 0}
};
/*
* 1612x1212 30fps VBlanking 1lane 10Bit
*/
#if 0
static struct ov2680_reg const ov2680_1616x1082_30fps[] = {
{OV2680_8BIT, 0x3086, 0x00},
{OV2680_8BIT, 0x3501, 0x48},
{OV2680_8BIT, 0x3502, 0xe0},
{OV2680_8BIT, 0x370a, 0x21},
{OV2680_8BIT, 0x3801, 0x00},
{OV2680_8BIT, 0x3802, 0x00},
{OV2680_8BIT, 0x3803, 0x86},
{OV2680_8BIT, 0x3804, 0x06},
{OV2680_8BIT, 0x3805, 0x4f},
{OV2680_8BIT, 0x3806, 0x04},
{OV2680_8BIT, 0x3807, 0xbf},
{OV2680_8BIT, 0x3808, 0x06},
{OV2680_8BIT, 0x3809, 0x50},
{OV2680_8BIT, 0x380a, 0x04},
{OV2680_8BIT, 0x380b, 0x3a},
{OV2680_8BIT, 0x380c, 0x06},
{OV2680_8BIT, 0x380d, 0xa8},
{OV2680_8BIT, 0x380e, 0x05},
{OV2680_8BIT, 0x380f, 0x0e},
{OV2680_8BIT, 0x3810, 0x00},
{OV2680_8BIT, 0x3811, 0x00},
{OV2680_8BIT, 0x3812, 0x00},
{OV2680_8BIT, 0x3813, 0x00},
{OV2680_8BIT, 0x3814, 0x11},
{OV2680_8BIT, 0x3815, 0x11},
{OV2680_8BIT, 0x5708, 0x01}, //add for full size flip off and mirror off 2014/09/11
{OV2680_8BIT, 0x5704, 0x06},
{OV2680_8BIT, 0x5705, 0x50},
{OV2680_8BIT, 0x5706, 0x04},
{OV2680_8BIT, 0x5707, 0x3a},
{OV2680_8BIT, 0x3820, 0xc0},
{OV2680_8BIT, 0x3821, 0x00},
// {OV2680_8BIT, 0x5090, 0x0C},
{OV2680_8BIT, 0x4008, 0x02},
{OV2680_8BIT, 0x4009, 0x09},
{OV2680_8BIT, 0x5081, 0x41},
{OV2680_TOK_TERM, 0, 0}
};
#endif
/*
* 1616x1216 30fps VBlanking 1lane 10Bit
*/
static struct ov2680_reg const ov2680_1616x1216_30fps[] = {
{OV2680_8BIT, 0x3086, 0x00},
{OV2680_8BIT, 0x3501, 0x48},
{OV2680_8BIT, 0x3502, 0xe0},
{OV2680_8BIT, 0x370a, 0x21},
{OV2680_8BIT, 0x3801, 0x00},
{OV2680_8BIT, 0x3802, 0x00},
{OV2680_8BIT, 0x3803, 0x00},
{OV2680_8BIT, 0x3804, 0x06},
{OV2680_8BIT, 0x3805, 0x4f},
{OV2680_8BIT, 0x3806, 0x04},
{OV2680_8BIT, 0x3807, 0xbf},
{OV2680_8BIT, 0x3808, 0x06},
{OV2680_8BIT, 0x3809, 0x50},//50},//4line for mirror and flip
{OV2680_8BIT, 0x380a, 0x04},
{OV2680_8BIT, 0x380b, 0xc0},//c0},
{OV2680_8BIT, 0x380c, 0x06},
{OV2680_8BIT, 0x380d, 0xa8},
{OV2680_8BIT, 0x380e, 0x05},
{OV2680_8BIT, 0x380f, 0x0e},
{OV2680_8BIT, 0x3810, 0x00},
{OV2680_8BIT, 0x3811, 0x00},
{OV2680_8BIT, 0x3812, 0x00},
{OV2680_8BIT, 0x3813, 0x00},
{OV2680_8BIT, 0x3814, 0x11},
{OV2680_8BIT, 0x3815, 0x11},
{OV2680_8BIT, 0x4008, 0x00},
{OV2680_8BIT, 0x4009, 0x0b},
{OV2680_8BIT, 0x5081, 0x01},
{OV2680_8BIT, 0x5708, 0x01}, //add for full size flip off and mirror off 2014/09/11
{OV2680_8BIT, 0x5704, 0x06},
{OV2680_8BIT, 0x5705, 0x50},
{OV2680_8BIT, 0x5706, 0x04},
{OV2680_8BIT, 0x5707, 0xcc},
{OV2680_8BIT, 0x3820, 0xc0},
{OV2680_8BIT, 0x3821, 0x00},
// {OV2680_8BIT, 0x5090, 0x0C},
{OV2680_TOK_TERM, 0, 0}
};
static struct ov2680_resolution ov2680_res_preview[] = {
{
.desc = "ov2680_1616x1216_30fps",
.width = 1616,
.height = 1216,
.pix_clk_freq = 66,
.fps = 30,
.used = 0,
.pixels_per_line = 1698,//1704,
.lines_per_frame = 1294,
.bin_factor_x = 0,
.bin_factor_y = 0,
.bin_mode = 0,
.skip_frames = 3,
.regs = ov2680_1616x1216_30fps,
},
{
.desc = "ov2680_1616x916_30fps",
.width = 1616,
.height = 916,
.fps = 30,
.pix_clk_freq = 66,
.used = 0,
.pixels_per_line = 1698,//1704,
.lines_per_frame = 1294,
.bin_factor_x = 0,
.bin_factor_y = 0,
.bin_mode = 0,
.skip_frames = 3,
.regs = ov2680_1616x916_30fps,
},
};
#define N_RES_PREVIEW (ARRAY_SIZE(ov2680_res_preview))
static struct ov2680_resolution *ov2680_res = ov2680_res_preview;
static unsigned long N_RES = N_RES_PREVIEW;
#endif

1268
drivers/staging/media/atomisp/i2c/ov2722.h
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11
drivers/staging/media/atomisp/i2c/ov5693/Kconfig
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@ -1,11 +0,0 @@
config VIDEO_ATOMISP_OV5693
tristate "Omnivision ov5693 sensor support"
depends on ACPI
depends on I2C && VIDEO_V4L2
---help---
This is a Video4Linux2 sensor-level driver for the Micron
ov5693 5 Mpixel camera.
ov5693 is video camera sensor.
It currently only works with the atomisp driver.

2
drivers/staging/media/atomisp/i2c/ov5693/Makefile
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# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_VIDEO_ATOMISP_OV5693) += atomisp-ov5693.o

63
drivers/staging/media/atomisp/i2c/ov5693/ad5823.h
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/*
* Support for AD5823 VCM.
*
* Copyright (c) 2013 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
*/
#ifndef __AD5823_H__
#define __AD5823_H__
#include <linux/types.h>
#define AD5823_VCM_ADDR 0x0c
#define AD5823_REG_RESET 0x01
#define AD5823_REG_MODE 0x02
#define AD5823_REG_VCM_MOVE_TIME 0x03
#define AD5823_REG_VCM_CODE_MSB 0x04
#define AD5823_REG_VCM_CODE_LSB 0x05
#define AD5823_REG_VCM_THRESHOLD_MSB 0x06
#define AD5823_REG_VCM_THRESHOLD_LSB 0x07
#define AD5823_REG_LENGTH 0x1
#define AD5823_RING_CTRL_ENABLE 0x04
#define AD5823_RING_CTRL_DISABLE 0x00
#define AD5823_RESONANCE_PERIOD 100000
#define AD5823_RESONANCE_COEF 512
#define AD5823_HIGH_FREQ_RANGE 0x80
#define VCM_CODE_MSB_MASK 0xfc
#define AD5823_INIT_FOCUS_POS 350
enum ad5823_tok_type {
AD5823_8BIT = 0x1,
AD5823_16BIT = 0x2,
};
enum ad5823_vcm_mode {
AD5823_ARC_RES0 = 0x0, /* Actuator response control RES1 */
AD5823_ARC_RES1 = 0x1, /* Actuator response control RES0.5 */
AD5823_ARC_RES2 = 0x2, /* Actuator response control RES2 */
AD5823_ESRC = 0x3, /* Enhanced slew rate control */
AD5823_DIRECT = 0x4, /* Direct control */
};
#define AD5823_INVALID_CONFIG 0xffffffff
#define AD5823_MAX_FOCUS_POS 1023
#define DELAY_PER_STEP_NS 1000000
#define DELAY_MAX_PER_STEP_NS (1000000 * 1023)
#endif

1993
drivers/staging/media/atomisp/i2c/ov5693/atomisp-ov5693.c
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1392
drivers/staging/media/atomisp/i2c/ov5693/ov5693.h
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1359
drivers/staging/media/atomisp/include/linux/atomisp.h
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36
drivers/staging/media/atomisp/include/linux/atomisp_gmin_platform.h
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/*
* Support for Intel MID SoC Camera Imaging ISP subsystem.
*
* Copyright (c) 2014 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef ATOMISP_GMIN_PLATFORM_H_
#define ATOMISP_GMIN_PLATFORM_H_
#include "atomisp_platform.h"
int atomisp_register_i2c_module(struct v4l2_subdev *subdev,
struct camera_sensor_platform_data *plat_data,
enum intel_v4l2_subdev_type type);
struct v4l2_subdev *atomisp_gmin_find_subdev(struct i2c_adapter *adapter,
struct i2c_board_info *board_info);
int atomisp_gmin_remove_subdev(struct v4l2_subdev *sd);
int gmin_get_var_int(struct device *dev, const char *var, int def);
int camera_sensor_csi(struct v4l2_subdev *sd, u32 port,
u32 lanes, u32 format, u32 bayer_order, int flag);
struct camera_sensor_platform_data *gmin_camera_platform_data(
struct v4l2_subdev *subdev,
enum atomisp_input_format csi_format,
enum atomisp_bayer_order csi_bayer);
int atomisp_gmin_register_vcm_control(struct camera_vcm_control *);
#endif

249
drivers/staging/media/atomisp/include/linux/atomisp_platform.h
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@ -1,249 +0,0 @@
/*
* Support for Medifield PNW Camera Imaging ISP subsystem.
*
* Copyright (c) 2010 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
*/
#ifndef ATOMISP_PLATFORM_H_
#define ATOMISP_PLATFORM_H_
#include <linux/i2c.h>
#include <linux/sfi.h>
#include <media/v4l2-subdev.h>
#include "atomisp.h"
#define MAX_SENSORS_PER_PORT 4
#define MAX_STREAMS_PER_CHANNEL 2
#define CAMERA_MODULE_ID_LEN 64
enum atomisp_bayer_order {
atomisp_bayer_order_grbg,
atomisp_bayer_order_rggb,
atomisp_bayer_order_bggr,
atomisp_bayer_order_gbrg
};
enum atomisp_input_stream_id {
ATOMISP_INPUT_STREAM_GENERAL = 0,
ATOMISP_INPUT_STREAM_CAPTURE = 0,
ATOMISP_INPUT_STREAM_POSTVIEW,
ATOMISP_INPUT_STREAM_PREVIEW,
ATOMISP_INPUT_STREAM_VIDEO,
ATOMISP_INPUT_STREAM_NUM
};
enum atomisp_input_format {
ATOMISP_INPUT_FORMAT_YUV420_8_LEGACY,/* 8 bits per subpixel (legacy) */
ATOMISP_INPUT_FORMAT_YUV420_8, /* 8 bits per subpixel */
ATOMISP_INPUT_FORMAT_YUV420_10,/* 10 bits per subpixel */
ATOMISP_INPUT_FORMAT_YUV420_16,/* 16 bits per subpixel */
ATOMISP_INPUT_FORMAT_YUV422_8, /* UYVY..UVYV, 8 bits per subpixel */
ATOMISP_INPUT_FORMAT_YUV422_10,/* UYVY..UVYV, 10 bits per subpixel */
ATOMISP_INPUT_FORMAT_YUV422_16,/* UYVY..UVYV, 16 bits per subpixel */
ATOMISP_INPUT_FORMAT_RGB_444, /* BGR..BGR, 4 bits per subpixel */
ATOMISP_INPUT_FORMAT_RGB_555, /* BGR..BGR, 5 bits per subpixel */
ATOMISP_INPUT_FORMAT_RGB_565, /* BGR..BGR, 5 bits B and R, 6 bits G */
ATOMISP_INPUT_FORMAT_RGB_666, /* BGR..BGR, 6 bits per subpixel */
ATOMISP_INPUT_FORMAT_RGB_888, /* BGR..BGR, 8 bits per subpixel */
ATOMISP_INPUT_FORMAT_RAW_6, /* RAW data, 6 bits per pixel */
ATOMISP_INPUT_FORMAT_RAW_7, /* RAW data, 7 bits per pixel */
ATOMISP_INPUT_FORMAT_RAW_8, /* RAW data, 8 bits per pixel */
ATOMISP_INPUT_FORMAT_RAW_10, /* RAW data, 10 bits per pixel */
ATOMISP_INPUT_FORMAT_RAW_12, /* RAW data, 12 bits per pixel */
ATOMISP_INPUT_FORMAT_RAW_14, /* RAW data, 14 bits per pixel */
ATOMISP_INPUT_FORMAT_RAW_16, /* RAW data, 16 bits per pixel */
ATOMISP_INPUT_FORMAT_BINARY_8, /* Binary byte stream. */
/* CSI2-MIPI specific format: Generic short packet data. It is used to
* keep the timing information for the opening/closing of shutters,
* triggering of flashes and etc.
*/
ATOMISP_INPUT_FORMAT_GENERIC_SHORT1, /* Generic Short Packet Code 1 */
ATOMISP_INPUT_FORMAT_GENERIC_SHORT2, /* Generic Short Packet Code 2 */
ATOMISP_INPUT_FORMAT_GENERIC_SHORT3, /* Generic Short Packet Code 3 */
ATOMISP_INPUT_FORMAT_GENERIC_SHORT4, /* Generic Short Packet Code 4 */
ATOMISP_INPUT_FORMAT_GENERIC_SHORT5, /* Generic Short Packet Code 5 */
ATOMISP_INPUT_FORMAT_GENERIC_SHORT6, /* Generic Short Packet Code 6 */
ATOMISP_INPUT_FORMAT_GENERIC_SHORT7, /* Generic Short Packet Code 7 */
ATOMISP_INPUT_FORMAT_GENERIC_SHORT8, /* Generic Short Packet Code 8 */
/* CSI2-MIPI specific format: YUV data.
*/
ATOMISP_INPUT_FORMAT_YUV420_8_SHIFT, /* YUV420 8-bit (Chroma Shifted
Pixel Sampling) */
ATOMISP_INPUT_FORMAT_YUV420_10_SHIFT, /* YUV420 8-bit (Chroma Shifted
Pixel Sampling) */
/* CSI2-MIPI specific format: Generic long packet data
*/
ATOMISP_INPUT_FORMAT_EMBEDDED, /* Embedded 8-bit non Image Data */
/* CSI2-MIPI specific format: User defined byte-based data. For example,
* the data transmitter (e.g. the SoC sensor) can keep the JPEG data as
* the User Defined Data Type 4 and the MPEG data as the
* User Defined Data Type 7.
*/
ATOMISP_INPUT_FORMAT_USER_DEF1, /* User defined 8-bit data type 1 */
ATOMISP_INPUT_FORMAT_USER_DEF2, /* User defined 8-bit data type 2 */
ATOMISP_INPUT_FORMAT_USER_DEF3, /* User defined 8-bit data type 3 */
ATOMISP_INPUT_FORMAT_USER_DEF4, /* User defined 8-bit data type 4 */
ATOMISP_INPUT_FORMAT_USER_DEF5, /* User defined 8-bit data type 5 */
ATOMISP_INPUT_FORMAT_USER_DEF6, /* User defined 8-bit data type 6 */
ATOMISP_INPUT_FORMAT_USER_DEF7, /* User defined 8-bit data type 7 */
ATOMISP_INPUT_FORMAT_USER_DEF8, /* User defined 8-bit data type 8 */
};
#define N_ATOMISP_INPUT_FORMAT (ATOMISP_INPUT_FORMAT_USER_DEF8 + 1)
enum intel_v4l2_subdev_type {
RAW_CAMERA = 1,
SOC_CAMERA = 2,
CAMERA_MOTOR = 3,
LED_FLASH = 4,
XENON_FLASH = 5,
FILE_INPUT = 6,
TEST_PATTERN = 7,
};
struct intel_v4l2_subdev_id {
char name[17];
enum intel_v4l2_subdev_type type;
enum atomisp_camera_port port;
};
struct intel_v4l2_subdev_i2c_board_info {
struct i2c_board_info board_info;
int i2c_adapter_id;
};
struct intel_v4l2_subdev_table {
struct intel_v4l2_subdev_i2c_board_info v4l2_subdev;
enum intel_v4l2_subdev_type type;
enum atomisp_camera_port port;
struct v4l2_subdev *subdev;
};
struct atomisp_platform_data {
struct intel_v4l2_subdev_table *subdevs;
};
/* Describe the capacities of one single sensor. */
struct atomisp_sensor_caps {
/* The number of streams this sensor can output. */
int stream_num;
bool is_slave;
};
/* Describe the capacities of sensors connected to one camera port. */
struct atomisp_camera_caps {
/* The number of sensors connected to this camera port. */
int sensor_num;
/* The capacities of each sensor. */
struct atomisp_sensor_caps sensor[MAX_SENSORS_PER_PORT];
/* Define whether stream control is required for multiple streams. */
bool multi_stream_ctrl;
};
/*
* Sensor of external ISP can send multiple steams with different mipi data
* type in the same virtual channel. This information needs to come from the
* sensor or external ISP
*/
struct atomisp_isys_config_info {
u8 input_format;
u16 width;
u16 height;
};
struct atomisp_input_stream_info {
enum atomisp_input_stream_id stream;
u8 enable;
/* Sensor driver fills ch_id with the id
of the virtual channel. */
u8 ch_id;
/* Tells how many streams in this virtual channel. If 0 ignore rest
* and the input format will be from mipi_info */
u8 isys_configs;
/*
* if more isys_configs is more than 0, sensor needs to configure the
* input format differently. width and height can be 0. If width and
* height is not zero, then the corresponsing data needs to be set
*/
struct atomisp_isys_config_info isys_info[MAX_STREAMS_PER_CHANNEL];
};
struct camera_vcm_control;
struct camera_vcm_ops {
int (*power_up)(struct v4l2_subdev *sd, struct camera_vcm_control *vcm);
int (*power_down)(struct v4l2_subdev *sd,
struct camera_vcm_control *vcm);
int (*queryctrl)(struct v4l2_subdev *sd, struct v4l2_queryctrl *qc,
struct camera_vcm_control *vcm);
int (*g_ctrl)(struct v4l2_subdev *sd, struct v4l2_control *ctrl,
struct camera_vcm_control *vcm);
int (*s_ctrl)(struct v4l2_subdev *sd, struct v4l2_control *ctrl,
struct camera_vcm_control *vcm);
};
struct camera_vcm_control {
char camera_module[CAMERA_MODULE_ID_LEN];
struct camera_vcm_ops *ops;
struct list_head list;
};
struct camera_sensor_platform_data {
int (*flisclk_ctrl)(struct v4l2_subdev *subdev, int flag);
int (*csi_cfg)(struct v4l2_subdev *subdev, int flag);
/*
* New G-Min power and GPIO interface to control individual
* lines as implemented on all known camera modules.
*/
int (*gpio0_ctrl)(struct v4l2_subdev *subdev, int on);
int (*gpio1_ctrl)(struct v4l2_subdev *subdev, int on);
int (*v1p8_ctrl)(struct v4l2_subdev *subdev, int on);
int (*v2p8_ctrl)(struct v4l2_subdev *subdev, int on);
int (*v1p2_ctrl)(struct v4l2_subdev *subdev, int on);
struct camera_vcm_control * (*get_vcm_ctrl)(struct v4l2_subdev *subdev,
char *module_id);
};
struct camera_mipi_info {
enum atomisp_camera_port port;
unsigned int num_lanes;
enum atomisp_input_format input_format;
enum atomisp_bayer_order raw_bayer_order;
struct atomisp_sensor_mode_data data;
enum atomisp_input_format metadata_format;
uint32_t metadata_width;
uint32_t metadata_height;
const uint32_t *metadata_effective_width;
};
extern const struct atomisp_platform_data *atomisp_get_platform_data(void);
extern const struct atomisp_camera_caps *atomisp_get_default_camera_caps(void);
/* API from old platform_camera.h, new CPUID implementation */
#define __IS_SOC(x) (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && \
boot_cpu_data.x86 == 6 && \
boot_cpu_data.x86_model == x)
#define IS_MFLD __IS_SOC(0x27)
#define IS_BYT __IS_SOC(0x37)
#define IS_CHT __IS_SOC(0x4C)
#define IS_MOFD __IS_SOC(0x5A)
#endif /* ATOMISP_PLATFORM_H_ */

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drivers/staging/media/atomisp/include/linux/libmsrlisthelper.h
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/*
* Copyright (c) 2013 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
*/
#ifndef __LIBMSRLISTHELPER_H__
#define __LIBMSRLISTHELPER_H__
struct i2c_client;
struct firmware;
extern int load_msr_list(struct i2c_client *client, char *path,
const struct firmware **fw);
extern int apply_msr_data(struct i2c_client *client, const struct firmware *fw);
extern void release_msr_list(struct i2c_client *client,
const struct firmware *fw);
#endif /* ifndef __LIBMSRLISTHELPER_H__ */

131
drivers/staging/media/atomisp/include/media/lm3554.h
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@ -1,131 +0,0 @@
/*
* include/media/lm3554.h
*
* Copyright (c) 2010-2012 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
*/
#ifndef _LM3554_H_
#define _LM3554_H_
#include <linux/videodev2.h>
#include <media/v4l2-subdev.h>
#define LM3554_ID 3554
#define v4l2_queryctrl_entry_integer(_id, _name,\
_minimum, _maximum, _step, \
_default_value, _flags) \
{\
.id = (_id), \
.type = V4L2_CTRL_TYPE_INTEGER, \
.name = _name, \
.minimum = (_minimum), \
.maximum = (_maximum), \
.step = (_step), \
.default_value = (_default_value),\
.flags = (_flags),\
}
#define v4l2_queryctrl_entry_boolean(_id, _name,\
_default_value, _flags) \
{\
.id = (_id), \
.type = V4L2_CTRL_TYPE_BOOLEAN, \
.name = _name, \
.minimum = 0, \
.maximum = 1, \
.step = 1, \
.default_value = (_default_value),\
.flags = (_flags),\
}
#define s_ctrl_id_entry_integer(_id, _name, \
_minimum, _maximum, _step, \
_default_value, _flags, \
_s_ctrl, _g_ctrl) \
{\
.qc = v4l2_queryctrl_entry_integer(_id, _name,\
_minimum, _maximum, _step,\
_default_value, _flags), \
.s_ctrl = _s_ctrl, \
.g_ctrl = _g_ctrl, \
}
#define s_ctrl_id_entry_boolean(_id, _name, \
_default_value, _flags, \
_s_ctrl, _g_ctrl) \
{\
.qc = v4l2_queryctrl_entry_boolean(_id, _name,\
_default_value, _flags), \
.s_ctrl = _s_ctrl, \
.g_ctrl = _g_ctrl, \
}
/* Value settings for Flash Time-out Duration*/
#define LM3554_DEFAULT_TIMEOUT 512U
#define LM3554_MIN_TIMEOUT 32U
#define LM3554_MAX_TIMEOUT 1024U
#define LM3554_TIMEOUT_STEPSIZE 32U
/* Flash modes */
#define LM3554_MODE_SHUTDOWN 0
#define LM3554_MODE_INDICATOR 1
#define LM3554_MODE_TORCH 2
#define LM3554_MODE_FLASH 3
/* timer delay time */
#define LM3554_TIMER_DELAY 5
/* Percentage <-> value macros */
#define LM3554_MIN_PERCENT 0U
#define LM3554_MAX_PERCENT 100U
#define LM3554_CLAMP_PERCENTAGE(val) \
clamp(val, LM3554_MIN_PERCENT, LM3554_MAX_PERCENT)
#define LM3554_VALUE_TO_PERCENT(v, step) (((((unsigned long)(v))*(step))+50)/100)
#define LM3554_PERCENT_TO_VALUE(p, step) (((((unsigned long)(p))*100)+(step>>1))/(step))
/* Product specific limits
* TODO: get these from platform data */
#define LM3554_FLASH_MAX_LVL 0x0F /* 1191mA */
/* Flash brightness, input is percentage, output is [0..15] */
#define LM3554_FLASH_STEP \
((100ul*(LM3554_MAX_PERCENT)+((LM3554_FLASH_MAX_LVL)>>1))/((LM3554_FLASH_MAX_LVL)))
#define LM3554_FLASH_DEFAULT_BRIGHTNESS \
LM3554_VALUE_TO_PERCENT(13, LM3554_FLASH_STEP)
/* Torch brightness, input is percentage, output is [0..7] */
#define LM3554_TORCH_STEP 1250
#define LM3554_TORCH_DEFAULT_BRIGHTNESS \
LM3554_VALUE_TO_PERCENT(2, LM3554_TORCH_STEP)
/* Indicator brightness, input is percentage, output is [0..3] */
#define LM3554_INDICATOR_STEP 2500
#define LM3554_INDICATOR_DEFAULT_BRIGHTNESS \
LM3554_VALUE_TO_PERCENT(1, LM3554_INDICATOR_STEP)
/*
* lm3554_platform_data - Flash controller platform data
*/
struct lm3554_platform_data {
int gpio_torch;
int gpio_strobe;
int gpio_reset;
unsigned int current_limit;
unsigned int envm_tx2;
unsigned int tx2_polarity;
};
#endif /* _LM3554_H_ */

14
drivers/staging/media/atomisp/pci/Kconfig
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@ -1,14 +0,0 @@
#
# Kconfig for ISP driver
#
config VIDEO_ATOMISP
tristate "Intel Atom Image Signal Processor Driver"
depends on VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API
select IOSF_MBI
select VIDEOBUF_VMALLOC
---help---
Say Y here if your platform supports Intel Atom SoC
camera imaging subsystem.
To compile this driver as a module, choose M here: the
module will be called atomisp

5
drivers/staging/media/atomisp/pci/Makefile
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@ -1,5 +0,0 @@
#
# Makefile for ISP driver
#
obj-$(CONFIG_VIDEO_ATOMISP) += atomisp2/

349
drivers/staging/media/atomisp/pci/atomisp2/Makefile
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@ -1,349 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
atomisp-objs += \
atomisp_drvfs.o \
atomisp_file.o \
css2400/sh_css_mipi.o \
css2400/runtime/pipeline/src/pipeline.o \
css2400/runtime/spctrl/src/spctrl.o \
css2400/runtime/rmgr/src/rmgr.o \
css2400/runtime/rmgr/src/rmgr_vbuf.o \
css2400/runtime/isp_param/src/isp_param.o \
css2400/runtime/inputfifo/src/inputfifo.o \
css2400/runtime/queue/src/queue_access.o \
css2400/runtime/queue/src/queue.o \
css2400/runtime/frame/src/frame.o \
css2400/runtime/eventq/src/eventq.o \
css2400/runtime/binary/src/binary.o \
css2400/runtime/timer/src/timer.o \
css2400/runtime/isys/src/csi_rx_rmgr.o \
css2400/runtime/isys/src/isys_stream2mmio_rmgr.o \
css2400/runtime/isys/src/virtual_isys.o \
css2400/runtime/isys/src/rx.o \
css2400/runtime/isys/src/isys_dma_rmgr.o \
css2400/runtime/isys/src/ibuf_ctrl_rmgr.o \
css2400/runtime/isys/src/isys_init.o \
css2400/runtime/bufq/src/bufq.o \
css2400/runtime/ifmtr/src/ifmtr.o \
css2400/runtime/debug/src/ia_css_debug.o \
css2400/runtime/event/src/event.o \
css2400/sh_css_sp.o \
css2400/css_2400_system/spmem_dump.o \
css2400/css_2400_system/hive_isp_css_2400_system_generated/ia_css_isp_states.o \
css2400/css_2400_system/hive_isp_css_2400_system_generated/ia_css_isp_configs.o \
css2400/css_2400_system/hive_isp_css_2400_system_generated/ia_css_isp_params.o \
css2400/sh_css_stream_format.o \
css2400/sh_css_hrt.o \
css2400/sh_css_properties.o \
css2400/memory_realloc.o \
css2400/hive_isp_css_shared/host/tag.o \
css2400/sh_css_params.o \
css2400/sh_css.o \
css2400/isp/kernels/hdr/ia_css_hdr.host.o \
css2400/isp/kernels/ynr/ynr_2/ia_css_ynr2.host.o \
css2400/isp/kernels/ynr/ynr_1.0/ia_css_ynr.host.o \
css2400/isp/kernels/conversion/conversion_1.0/ia_css_conversion.host.o \
css2400/isp/kernels/fpn/fpn_1.0/ia_css_fpn.host.o \
css2400/isp/kernels/tnr/tnr_1.0/ia_css_tnr.host.o \
css2400/isp/kernels/vf/vf_1.0/ia_css_vf.host.o \
css2400/isp/kernels/raw/raw_1.0/ia_css_raw.host.o \
css2400/isp/kernels/ref/ref_1.0/ia_css_ref.host.o \
css2400/isp/kernels/qplane/qplane_2/ia_css_qplane.host.o \
css2400/isp/kernels/norm/norm_1.0/ia_css_norm.host.o \
css2400/isp/kernels/output/output_1.0/ia_css_output.host.o \
css2400/isp/kernels/raw_aa_binning/raw_aa_binning_1.0/ia_css_raa.host.o \
css2400/isp/kernels/macc/macc1_5/ia_css_macc1_5_table.host.o \
css2400/isp/kernels/macc/macc1_5/ia_css_macc1_5.host.o \
css2400/isp/kernels/macc/macc_1.0/ia_css_macc.host.o \
css2400/isp/kernels/macc/macc_1.0/ia_css_macc_table.host.o \
css2400/isp/kernels/csc/csc_1.0/ia_css_csc.host.o \
css2400/isp/kernels/bnr/bnr_1.0/ia_css_bnr.host.o \
css2400/isp/kernels/bnr/bnr2_2/ia_css_bnr2_2.host.o \
css2400/isp/kernels/dpc2/ia_css_dpc2.host.o \
css2400/isp/kernels/fc/fc_1.0/ia_css_formats.host.o \
css2400/isp/kernels/ctc/ctc_1.0/ia_css_ctc.host.o \
css2400/isp/kernels/ctc/ctc_1.0/ia_css_ctc_table.host.o \
css2400/isp/kernels/ctc/ctc2/ia_css_ctc2.host.o \
css2400/isp/kernels/ctc/ctc1_5/ia_css_ctc1_5.host.o \
css2400/isp/kernels/bh/bh_2/ia_css_bh.host.o \
css2400/isp/kernels/bnlm/ia_css_bnlm.host.o \
css2400/isp/kernels/tdf/tdf_1.0/ia_css_tdf.host.o \
css2400/isp/kernels/dvs/dvs_1.0/ia_css_dvs.host.o \
css2400/isp/kernels/anr/anr_1.0/ia_css_anr.host.o \
css2400/isp/kernels/anr/anr_2/ia_css_anr2_table.host.o \
css2400/isp/kernels/anr/anr_2/ia_css_anr2.host.o \
css2400/isp/kernels/dp/dp_1.0/ia_css_dp.host.o \
css2400/isp/kernels/sdis/sdis_1.0/ia_css_sdis.host.o \
css2400/isp/kernels/sdis/sdis_2/ia_css_sdis2.host.o \
css2400/isp/kernels/cnr/cnr_2/ia_css_cnr2.host.o \
css2400/isp/kernels/cnr/cnr_1.0/ia_css_cnr.host.o \
css2400/isp/kernels/xnr/xnr_1.0/ia_css_xnr.host.o \
css2400/isp/kernels/xnr/xnr_1.0/ia_css_xnr_table.host.o \
css2400/isp/kernels/xnr/xnr_3.0/ia_css_xnr3.host.o \
css2400/isp/kernels/de/de_1.0/ia_css_de.host.o \
css2400/isp/kernels/de/de_2/ia_css_de2.host.o \
css2400/isp/kernels/gc/gc_2/ia_css_gc2.host.o \
css2400/isp/kernels/gc/gc_2/ia_css_gc2_table.host.o \
css2400/isp/kernels/gc/gc_1.0/ia_css_gc.host.o \
css2400/isp/kernels/gc/gc_1.0/ia_css_gc_table.host.o \
css2400/isp/kernels/crop/crop_1.0/ia_css_crop.host.o \
css2400/isp/kernels/io_ls/bayer_io_ls/ia_css_bayer_io.host.o \
css2400/isp/kernels/aa/aa_2/ia_css_aa2.host.o \
css2400/isp/kernels/copy_output/copy_output_1.0/ia_css_copy_output.host.o \
css2400/isp/kernels/ob/ob_1.0/ia_css_ob.host.o \
css2400/isp/kernels/ob/ob2/ia_css_ob2.host.o \
css2400/isp/kernels/iterator/iterator_1.0/ia_css_iterator.host.o \
css2400/isp/kernels/wb/wb_1.0/ia_css_wb.host.o \
css2400/isp/kernels/eed1_8/ia_css_eed1_8.host.o \
css2400/isp/kernels/sc/sc_1.0/ia_css_sc.host.o \
css2400/isp/kernels/ipu2_io_ls/bayer_io_ls/ia_css_bayer_io.host.o \
css2400/isp/kernels/ipu2_io_ls/yuv444_io_ls/ia_css_yuv444_io.host.o \
css2400/isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.o \
css2400/sh_css_pipe.o \
css2400/ia_css_device_access.o \
css2400/sh_css_host_data.o \
css2400/sh_css_mmu.o \
css2400/sh_css_metadata.o \
css2400/base/refcount/src/refcount.o \
css2400/base/circbuf/src/circbuf.o \
css2400/camera/pipe/src/pipe_binarydesc.o \
css2400/camera/pipe/src/pipe_util.o \
css2400/camera/pipe/src/pipe_stagedesc.o \
css2400/camera/util/src/util.o \
css2400/sh_css_metrics.o \
css2400/sh_css_version.o \
css2400/ia_css_memory_access.o \
css2400/sh_css_param_shading.o \
css2400/sh_css_morph.o \
css2400/sh_css_firmware.o \
css2400/hive_isp_css_common/host/isp.o \
css2400/hive_isp_css_common/host/gdc.o \
css2400/hive_isp_css_common/host/sp.o \
css2400/hive_isp_css_common/host/vmem.o \
css2400/hive_isp_css_common/host/dma.o \
css2400/hive_isp_css_common/host/input_formatter.o \
css2400/hive_isp_css_common/host/debug.o \
css2400/hive_isp_css_common/host/hmem.o \
css2400/hive_isp_css_common/host/gp_device.o \
css2400/hive_isp_css_common/host/fifo_monitor.o \
css2400/hive_isp_css_common/host/gp_timer.o \
css2400/hive_isp_css_common/host/irq.o \
css2400/hive_isp_css_common/host/input_system.o \
css2400/hive_isp_css_common/host/timed_ctrl.o \
css2400/hive_isp_css_common/host/mmu.o \
css2400/hive_isp_css_common/host/event_fifo.o \
css2400/sh_css_param_dvs.o \
css2400/sh_css_shading.o \
css2400/sh_css_stream.o \
mmu/sh_mmu_mrfld.o \
mmu/isp_mmu.o \
atomisp_acc.o \
atomisp_compat_css20.o \
atomisp_fops.o \
atomisp_subdev.o \
atomisp_ioctl.o \
atomisp_compat_ioctl32.o \
atomisp_csi2.o \
atomisp_cmd.o \
atomisp_tpg.o \
hmm/hmm_vm.o \
hmm/hmm.o \
hmm/hmm_bo.o \
hmm/hmm_reserved_pool.o \
hmm/hmm_dynamic_pool.o \
hrt/hive_isp_css_mm_hrt.o \
atomisp_v4l2.o
# These will be needed when clean merge CHT support nicely into the driver
# Keep them here handy for when we get to that point
#
obj-cht= \
css2400/css_2401_system/spmem_dump.o \
css2400/css_2401_system/hive_isp_css_2401_system_generated/ia_css_isp_states.o \
css2400/css_2401_system/hive_isp_css_2401_system_generated/ia_css_isp_configs.o \
css2400/css_2401_system/hive_isp_css_2401_system_generated/ia_css_isp_params.o \
css2400/css_2401_csi2p_system/spmem_dump.o \
css2400/css_2401_csi2p_system/host/isys_stream2mmio.o \
css2400/css_2401_csi2p_system/host/ibuf_ctrl.o \
css2400/css_2401_csi2p_system/host/isys_irq.o \
css2400/css_2401_csi2p_system/host/isys_dma.o \
css2400/css_2401_csi2p_system/host/csi_rx.o \
css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_states.o \
css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_configs.o \
css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_params.o \
# -I$(atomisp)/css2400/css_2401_csi2p_system/ \
# -I$(atomisp)/css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ \
# -I$(atomisp)/css2400/css_2401_csi2p_system/host/ \
# -I$(atomisp)/css2400/css_2401_csi2p_system/hrt/ \
# -I$(atomisp)/css2400/css_2401_system/hive_isp_css_2401_system_generated/ \
# -I$(atomisp)/css2400/css_2401_system/hrt/ \
obj-$(CONFIG_VIDEO_ATOMISP) += atomisp.o
atomisp = $(srctree)/drivers/staging/media/atomisp/pci/atomisp2
INCLUDES += \
-I$(atomisp)/ \
-I$(atomisp)/css2400/ \
-I$(atomisp)/hrt/ \
-I$(atomisp)/include/ \
-I$(atomisp)/include/hmm/ \
-I$(atomisp)/include/mmu/ \
-I$(atomisp)/css2400/base/circbuf/interface/ \
-I$(atomisp)/css2400/base/refcount/interface/ \
-I$(atomisp)/css2400/camera/pipe/interface/ \
-I$(atomisp)/css2400/camera/util/interface/ \
-I$(atomisp)/css2400/css_2400_system/ \
-I$(atomisp)/css2400/css_2400_system/hive_isp_css_2400_system_generated/ \
-I$(atomisp)/css2400/css_2400_system/hrt/ \
-I$(atomisp)/css2400/hive_isp_css_common/ \
-I$(atomisp)/css2400/hive_isp_css_common/host/ \
-I$(atomisp)/css2400/hive_isp_css_include/ \
-I$(atomisp)/css2400/hive_isp_css_include/device_access/ \
-I$(atomisp)/css2400/hive_isp_css_include/host/ \
-I$(atomisp)/css2400/hive_isp_css_include/memory_access/ \
-I$(atomisp)/css2400/hive_isp_css_shared/ \
-I$(atomisp)/css2400/hive_isp_css_shared/host/ \
-I$(atomisp)/css2400/isp/kernels/ \
-I$(atomisp)/css2400/isp/kernels/aa/aa_2/ \
-I$(atomisp)/css2400/isp/kernels/anr/anr_1.0/ \
-I$(atomisp)/css2400/isp/kernels/anr/anr_2/ \
-I$(atomisp)/css2400/isp/kernels/bh/bh_2/ \
-I$(atomisp)/css2400/isp/kernels/bnlm/ \
-I$(atomisp)/css2400/isp/kernels/bnr/ \
-I$(atomisp)/css2400/isp/kernels/bnr/bnr_1.0/ \
-I$(atomisp)/css2400/isp/kernels/bnr/bnr2_2/ \
-I$(atomisp)/css2400/isp/kernels/cnr/ \
-I$(atomisp)/css2400/isp/kernels/cnr/cnr_1.0/ \
-I$(atomisp)/css2400/isp/kernels/cnr/cnr_2/ \
-I$(atomisp)/css2400/isp/kernels/conversion/ \
-I$(atomisp)/css2400/isp/kernels/conversion/conversion_1.0/ \
-I$(atomisp)/css2400/isp/kernels/copy_output/ \
-I$(atomisp)/css2400/isp/kernels/copy_output/copy_output_1.0/ \
-I$(atomisp)/css2400/isp/kernels/crop/ \
-I$(atomisp)/css2400/isp/kernels/crop/crop_1.0/ \
-I$(atomisp)/css2400/isp/kernels/csc/ \
-I$(atomisp)/css2400/isp/kernels/csc/csc_1.0/ \
-I$(atomisp)/css2400/isp/kernels/ctc/ \
-I$(atomisp)/css2400/isp/kernels/ctc/ctc_1.0/ \
-I$(atomisp)/css2400/isp/kernels/ctc/ctc1_5/ \
-I$(atomisp)/css2400/isp/kernels/ctc/ctc2/ \
-I$(atomisp)/css2400/isp/kernels/de/ \
-I$(atomisp)/css2400/isp/kernels/de/de_1.0/ \
-I$(atomisp)/css2400/isp/kernels/de/de_2/ \
-I$(atomisp)/css2400/isp/kernels/dpc2/ \
-I$(atomisp)/css2400/isp/kernels/dp/ \
-I$(atomisp)/css2400/isp/kernels/dp/dp_1.0/ \
-I$(atomisp)/css2400/isp/kernels/dvs/ \
-I$(atomisp)/css2400/isp/kernels/dvs/dvs_1.0/ \
-I$(atomisp)/css2400/isp/kernels/eed1_8/ \
-I$(atomisp)/css2400/isp/kernels/fc/ \
-I$(atomisp)/css2400/isp/kernels/fc/fc_1.0/ \
-I$(atomisp)/css2400/isp/kernels/fixedbds/ \
-I$(atomisp)/css2400/isp/kernels/fixedbds/fixedbds_1.0/ \
-I$(atomisp)/css2400/isp/kernels/fpn/ \
-I$(atomisp)/css2400/isp/kernels/fpn/fpn_1.0/ \
-I$(atomisp)/css2400/isp/kernels/gc/ \
-I$(atomisp)/css2400/isp/kernels/gc/gc_1.0/ \
-I$(atomisp)/css2400/isp/kernels/gc/gc_2/ \
-I$(atomisp)/css2400/isp/kernels/hdr/ \
-I$(atomisp)/css2400/isp/kernels/io_ls/ \
-I$(atomisp)/css2400/isp/kernels/io_ls/bayer_io_ls/ \
-I$(atomisp)/css2400/isp/kernels/io_ls/common/ \
-I$(atomisp)/css2400/isp/kernels/io_ls/yuv444_io_ls/ \
-I$(atomisp)/css2400/isp/kernels/ipu2_io_ls/ \
-I$(atomisp)/css2400/isp/kernels/ipu2_io_ls/bayer_io_ls/ \
-I$(atomisp)/css2400/isp/kernels/ipu2_io_ls/common/ \
-I$(atomisp)/css2400/isp/kernels/ipu2_io_ls/yuv444_io_ls/ \
-I$(atomisp)/css2400/isp/kernels/iterator/ \
-I$(atomisp)/css2400/isp/kernels/iterator/iterator_1.0/ \
-I$(atomisp)/css2400/isp/kernels/macc/ \
-I$(atomisp)/css2400/isp/kernels/macc/macc_1.0/ \
-I$(atomisp)/css2400/isp/kernels/macc/macc1_5/ \
-I$(atomisp)/css2400/isp/kernels/norm/ \
-I$(atomisp)/css2400/isp/kernels/norm/norm_1.0/ \
-I$(atomisp)/css2400/isp/kernels/ob/ \
-I$(atomisp)/css2400/isp/kernels/ob/ob_1.0/ \
-I$(atomisp)/css2400/isp/kernels/ob/ob2/ \
-I$(atomisp)/css2400/isp/kernels/output/ \
-I$(atomisp)/css2400/isp/kernels/output/output_1.0/ \
-I$(atomisp)/css2400/isp/kernels/qplane/ \
-I$(atomisp)/css2400/isp/kernels/qplane/qplane_2/ \
-I$(atomisp)/css2400/isp/kernels/raw_aa_binning/ \
-I$(atomisp)/css2400/isp/kernels/raw_aa_binning/raw_aa_binning_1.0/ \
-I$(atomisp)/css2400/isp/kernels/raw/ \
-I$(atomisp)/css2400/isp/kernels/raw/raw_1.0/ \
-I$(atomisp)/css2400/isp/kernels/ref/ \
-I$(atomisp)/css2400/isp/kernels/ref/ref_1.0/ \
-I$(atomisp)/css2400/isp/kernels/s3a/ \
-I$(atomisp)/css2400/isp/kernels/s3a/s3a_1.0/ \
-I$(atomisp)/css2400/isp/kernels/sc/ \
-I$(atomisp)/css2400/isp/kernels/sc/sc_1.0/ \
-I$(atomisp)/css2400/isp/kernels/sdis/ \
-I$(atomisp)/css2400/isp/kernels/sdis/common/ \
-I$(atomisp)/css2400/isp/kernels/sdis/sdis_1.0/ \
-I$(atomisp)/css2400/isp/kernels/sdis/sdis_2/ \
-I$(atomisp)/css2400/isp/kernels/tdf/ \
-I$(atomisp)/css2400/isp/kernels/tdf/tdf_1.0/ \
-I$(atomisp)/css2400/isp/kernels/tnr/ \
-I$(atomisp)/css2400/isp/kernels/tnr/tnr_1.0/ \
-I$(atomisp)/css2400/isp/kernels/tnr/tnr3/ \
-I$(atomisp)/css2400/isp/kernels/uds/ \
-I$(atomisp)/css2400/isp/kernels/uds/uds_1.0/ \
-I$(atomisp)/css2400/isp/kernels/vf/ \
-I$(atomisp)/css2400/isp/kernels/vf/vf_1.0/ \
-I$(atomisp)/css2400/isp/kernels/wb/ \
-I$(atomisp)/css2400/isp/kernels/wb/wb_1.0/ \
-I$(atomisp)/css2400/isp/kernels/xnr/ \
-I$(atomisp)/css2400/isp/kernels/xnr/xnr_1.0/ \
-I$(atomisp)/css2400/isp/kernels/xnr/xnr_3.0/ \
-I$(atomisp)/css2400/isp/kernels/ynr/ \
-I$(atomisp)/css2400/isp/kernels/ynr/ynr_1.0/ \
-I$(atomisp)/css2400/isp/kernels/ynr/ynr_2/ \
-I$(atomisp)/css2400/isp/modes/interface/ \
-I$(atomisp)/css2400/runtime/binary/interface/ \
-I$(atomisp)/css2400/runtime/bufq/interface/ \
-I$(atomisp)/css2400/runtime/debug/interface/ \
-I$(atomisp)/css2400/runtime/event/interface/ \
-I$(atomisp)/css2400/runtime/eventq/interface/ \
-I$(atomisp)/css2400/runtime/frame/interface/ \
-I$(atomisp)/css2400/runtime/ifmtr/interface/ \
-I$(atomisp)/css2400/runtime/inputfifo/interface/ \
-I$(atomisp)/css2400/runtime/isp_param/interface/ \
-I$(atomisp)/css2400/runtime/isys/interface/ \
-I$(atomisp)/css2400/runtime/isys/src/ \
-I$(atomisp)/css2400/runtime/pipeline/interface/ \
-I$(atomisp)/css2400/runtime/queue/interface/ \
-I$(atomisp)/css2400/runtime/queue/src/ \
-I$(atomisp)/css2400/runtime/rmgr/interface/ \
-I$(atomisp)/css2400/runtime/spctrl/interface/ \
-I$(atomisp)/css2400/runtime/tagger/interface/
ifeq ($(CONFIG_ION),y)
INCLUDES += -I$(srctree)/drivers/staging/android/ion
endif
DEFINES := -DHRT_HW -DHRT_ISP_CSS_CUSTOM_HOST -DHRT_USE_VIR_ADDRS -D__HOST__
#DEFINES += -DUSE_DYNAMIC_BIN
#DEFINES += -DISP_POWER_GATING
#DEFINES += -DUSE_INTERRUPTS
#DEFINES += -DUSE_SSSE3
#DEFINES += -DPUNIT_CAMERA_BUSY
#DEFINES += -DUSE_KMEM_CACHE
DEFINES += -DATOMISP_POSTFIX=\"css2400b0_v21\" -DISP2400B0
DEFINES += -DSYSTEM_hive_isp_css_2400_system -DISP2400
ccflags-y += $(INCLUDES) $(DEFINES) -fno-common
# HACK! While this driver is in bad shape, don't enable several warnings
# that would be otherwise enabled with W=1
ccflags-y += $(call cc-disable-warning, implicit-fallthrough)
ccflags-y += $(call cc-disable-warning, missing-prototypes)
ccflags-y += $(call cc-disable-warning, missing-declarations)
ccflags-y += $(call cc-disable-warning, suggest-attribute=format)
ccflags-y += $(call cc-disable-warning, unused-const-variable)
ccflags-y += $(call cc-disable-warning, unused-but-set-variable)

205
drivers/staging/media/atomisp/pci/atomisp2/atomisp-regs.h
View File

@ -1,205 +0,0 @@
/*
* Support for Medifield PNW Camera Imaging ISP subsystem.
*
* Copyright (c) 2012 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
*/
#ifndef ATOMISP_REGS_H
#define ATOMISP_REGS_H
/* common register definitions */
#define PUNIT_PORT 0x04
#define CCK_PORT 0x14
#define PCICMDSTS 0x01
#define INTR 0x0f
#define MSI_CAPID 0x24
#define MSI_ADDRESS 0x25
#define MSI_DATA 0x26
#define INTR_CTL 0x27
#define PCI_MSI_CAPID 0x90
#define PCI_MSI_ADDR 0x94
#define PCI_MSI_DATA 0x98
#define PCI_INTERRUPT_CTRL 0x9C
#define PCI_I_CONTROL 0xfc
/* MRFLD specific register definitions */
#define MRFLD_CSI_AFE 0x39
#define MRFLD_CSI_CONTROL 0x3a
#define MRFLD_CSI_RCOMP 0x3d
#define MRFLD_PCI_PMCS 0x84
#define MRFLD_PCI_CSI_ACCESS_CTRL_VIOL 0xd4
#define MRFLD_PCI_CSI_AFE_HS_CONTROL 0xdc
#define MRFLD_PCI_CSI_AFE_RCOMP_CONTROL 0xe0
#define MRFLD_PCI_CSI_CONTROL 0xe8
#define MRFLD_PCI_CSI_AFE_TRIM_CONTROL 0xe4
#define MRFLD_PCI_CSI_DEADLINE_CONTROL 0xec
#define MRFLD_PCI_CSI_RCOMP_CONTROL 0xf4
/* Select Arasan (legacy)/Intel input system */
#define MRFLD_PCI_CSI_CONTROL_PARPATHEN BIT(24)
/* Enable CSI interface (ANN B0/K0) */
#define MRFLD_PCI_CSI_CONTROL_CSI_READY BIT(25)
/*
* Enables the combining of adjacent 32-byte read requests to the same
* cache line. When cleared, each 32-byte read request is sent as a
* separate request on the IB interface.
*/
#define MRFLD_PCI_I_CONTROL_ENABLE_READ_COMBINING 0x1
/*
* Register: MRFLD_PCI_CSI_RCOMP_CONTROL
* If cleared, the high speed clock going to the digital logic is gated when
* RCOMP update is happening. The clock is gated for a minimum of 100 nsec.
* If this bit is set, then the high speed clock is not gated during the
* update cycle.
*/
#define MRFLD_PCI_CSI_HS_OVR_CLK_GATE_ON_UPDATE 0x800000
/*
* Enables the combining of adjacent 32-byte write requests to the same
* cache line. When cleared, each 32-byte write request is sent as a
* separate request on the IB interface.
*/
#define MRFLD_PCI_I_CONTROL_ENABLE_WRITE_COMBINING 0x2
#define MRFLD_PCI_I_CONTROL_SRSE_RESET_MASK 0xc
#define MRFLD_PCI_CSI1_HSRXCLKTRIM 0x2
#define MRFLD_PCI_CSI1_HSRXCLKTRIM_SHIFT 16
#define MRFLD_PCI_CSI2_HSRXCLKTRIM 0x3
#define MRFLD_PCI_CSI2_HSRXCLKTRIM_SHIFT 24
#define MRFLD_PCI_CSI3_HSRXCLKTRIM 0x2
#define MRFLD_PCI_CSI3_HSRXCLKTRIM_SHIFT 28
#define MRFLD_PCI_CSI_HSRXCLKTRIM_MASK 0xf
/*
* This register is IUINT MMIO register, it is used to select the CSI
* receiver backend.
* 1: SH CSI backend
* 0: Arasan CSI backend
*/
#define MRFLD_CSI_RECEIVER_SELECTION_REG 0x8081c
#define MRFLD_INTR_CLEAR_REG 0x50c
#define MRFLD_INTR_STATUS_REG 0x508
#define MRFLD_INTR_ENABLE_REG 0x510
#define MRFLD_MAX_ZOOM_FACTOR 1024
/* MRFLD ISP POWER related */
#define MRFLD_ISPSSPM0 0x39
#define MRFLD_ISPSSPM0_ISPSSC_OFFSET 0
#define MRFLD_ISPSSPM0_ISPSSS_OFFSET 24
#define MRFLD_ISPSSPM0_ISPSSC_MASK 0x3
#define MRFLD_ISPSSPM0_IUNIT_POWER_ON 0
#define MRFLD_ISPSSPM0_IUNIT_POWER_OFF 0x3
#define MRFLD_ISPSSDVFS 0x13F
#define MRFLD_BIT0 0x0001
#define MRFLD_BIT1 0x0002
/* MRFLD CSI lane configuration related */
#define MRFLD_PORT_CONFIG_NUM 8
#define MRFLD_PORT_NUM 3
#define MRFLD_PORT1_ENABLE_SHIFT 0
#define MRFLD_PORT2_ENABLE_SHIFT 1
#define MRFLD_PORT3_ENABLE_SHIFT 2
#define MRFLD_PORT1_LANES_SHIFT 3
#define MRFLD_PORT2_LANES_SHIFT 7
#define MRFLD_PORT3_LANES_SHIFT 8
#define MRFLD_PORT_CONFIG_MASK 0x000f03ff
#define MRFLD_PORT_CONFIGCODE_SHIFT 16
#define MRFLD_ALL_CSI_PORTS_OFF_MASK 0x7
#define CHV_PORT3_LANES_SHIFT 9
#define CHV_PORT_CONFIG_MASK 0x1f07ff
#define ISPSSPM1 0x3a
#define ISP_FREQ_STAT_MASK (0x1f << ISP_FREQ_STAT_OFFSET)
#define ISP_REQ_FREQ_MASK 0x1f
#define ISP_FREQ_VALID_MASK (0x1 << ISP_FREQ_VALID_OFFSET)
#define ISP_FREQ_STAT_OFFSET 0x18
#define ISP_REQ_GUAR_FREQ_OFFSET 0x8
#define ISP_REQ_FREQ_OFFSET 0x0
#define ISP_FREQ_VALID_OFFSET 0x7
#define ISP_FREQ_RULE_ANY 0x0
#define ISP_FREQ_457MHZ 0x1C9
#define ISP_FREQ_400MHZ 0x190
#define ISP_FREQ_356MHZ 0x164
#define ISP_FREQ_320MHZ 0x140
#define ISP_FREQ_266MHZ 0x10a
#define ISP_FREQ_200MHZ 0xc8
#define ISP_FREQ_100MHZ 0x64
#define HPLL_FREQ_800MHZ 0x320
#define HPLL_FREQ_1600MHZ 0x640
#define HPLL_FREQ_2000MHZ 0x7D0
#define CCK_FUSE_REG_0 0x08
#define CCK_FUSE_HPLL_FREQ_MASK 0x03
#if defined(ISP2401)
#define ISP_FREQ_MAX ISP_FREQ_320MHZ
#else
#define ISP_FREQ_MAX ISP_FREQ_400MHZ
#endif
/* ISP2401 CSI2+ receiver delay settings */
#define CSI2_PORT_A_BASE 0xC0000
#define CSI2_PORT_B_BASE 0xC2000
#define CSI2_PORT_C_BASE 0xC4000
#define CSI2_LANE_CL_BASE 0x418
#define CSI2_LANE_D0_BASE 0x420
#define CSI2_LANE_D1_BASE 0x428
#define CSI2_LANE_D2_BASE 0x430
#define CSI2_LANE_D3_BASE 0x438
#define CSI2_REG_RX_CSI_DLY_CNT_TERMEN 0
#define CSI2_REG_RX_CSI_DLY_CNT_SETTLE 0x4
#define CSI2_PORT_A_RX_CSI_DLY_CNT_TERMEN_CLANE 0xC0418
#define CSI2_PORT_A_RX_CSI_DLY_CNT_SETTLE_CLANE 0xC041C
#define CSI2_PORT_A_RX_CSI_DLY_CNT_TERMEN_DLANE0 0xC0420
#define CSI2_PORT_A_RX_CSI_DLY_CNT_SETTLE_DLANE0 0xC0424
#define CSI2_PORT_A_RX_CSI_DLY_CNT_TERMEN_DLANE1 0xC0428
#define CSI2_PORT_A_RX_CSI_DLY_CNT_SETTLE_DLANE1 0xC042C
#define CSI2_PORT_A_RX_CSI_DLY_CNT_TERMEN_DLANE2 0xC0430
#define CSI2_PORT_A_RX_CSI_DLY_CNT_SETTLE_DLANE2 0xC0434
#define CSI2_PORT_A_RX_CSI_DLY_CNT_TERMEN_DLANE3 0xC0438
#define CSI2_PORT_A_RX_CSI_DLY_CNT_SETTLE_DLANE3 0xC043C
#define CSI2_PORT_B_RX_CSI_DLY_CNT_TERMEN_CLANE 0xC2418
#define CSI2_PORT_B_RX_CSI_DLY_CNT_SETTLE_CLANE 0xC241C
#define CSI2_PORT_B_RX_CSI_DLY_CNT_TERMEN_DLANE0 0xC2420
#define CSI2_PORT_B_RX_CSI_DLY_CNT_SETTLE_DLANE0 0xC2424
#define CSI2_PORT_B_RX_CSI_DLY_CNT_TERMEN_DLANE1 0xC2428
#define CSI2_PORT_B_RX_CSI_DLY_CNT_SETTLE_DLANE1 0xC242C
#define CSI2_PORT_C_RX_CSI_DLY_CNT_TERMEN_CLANE 0xC4418
#define CSI2_PORT_C_RX_CSI_DLY_CNT_SETTLE_CLANE 0xC441C
#define CSI2_PORT_C_RX_CSI_DLY_CNT_TERMEN_DLANE0 0xC4420
#define CSI2_PORT_C_RX_CSI_DLY_CNT_SETTLE_DLANE0 0xC4424
#define CSI2_PORT_C_RX_CSI_DLY_CNT_TERMEN_DLANE1 0xC4428
#define CSI2_PORT_C_RX_CSI_DLY_CNT_SETTLE_DLANE1 0xC442C
#define DMA_BURST_SIZE_REG 0xCD408
#define ISP_DFS_TRY_TIMES 2
#endif /* ATOMISP_REGS_H */

604
drivers/staging/media/atomisp/pci/atomisp2/atomisp_acc.c
View File

@ -1,604 +0,0 @@
/*
* Support for Clovertrail PNW Camera Imaging ISP subsystem.
*
* Copyright (c) 2012 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
*/
/*
* This file implements loadable acceleration firmware API,
* including ioctls to map and unmap acceleration parameters and buffers.
*/
#include <linux/init.h>
#include <media/v4l2-event.h>
#include "atomisp_acc.h"
#include "atomisp_internal.h"
#include "atomisp_compat.h"
#include "atomisp_cmd.h"
#include "hrt/hive_isp_css_mm_hrt.h"
#include "memory_access/memory_access.h"
#include "ia_css.h"
static const struct {
unsigned int flag;
enum atomisp_css_pipe_id pipe_id;
} acc_flag_to_pipe[] = {
{ ATOMISP_ACC_FW_LOAD_FL_PREVIEW, CSS_PIPE_ID_PREVIEW },
{ ATOMISP_ACC_FW_LOAD_FL_COPY, CSS_PIPE_ID_COPY },
{ ATOMISP_ACC_FW_LOAD_FL_VIDEO, CSS_PIPE_ID_VIDEO },
{ ATOMISP_ACC_FW_LOAD_FL_CAPTURE, CSS_PIPE_ID_CAPTURE },
{ ATOMISP_ACC_FW_LOAD_FL_ACC, CSS_PIPE_ID_ACC }
};
/*
* Allocate struct atomisp_acc_fw along with space for firmware.
* The returned struct atomisp_acc_fw is cleared (firmware region is not).
*/
static struct atomisp_acc_fw *acc_alloc_fw(unsigned int fw_size)
{
struct atomisp_acc_fw *acc_fw;
acc_fw = kzalloc(sizeof(*acc_fw), GFP_KERNEL);
if (!acc_fw)
return NULL;
acc_fw->fw = vmalloc(fw_size);
if (!acc_fw->fw) {
kfree(acc_fw);
return NULL;
}
return acc_fw;
}
static void acc_free_fw(struct atomisp_acc_fw *acc_fw)
{
vfree(acc_fw->fw);
kfree(acc_fw);
}
static struct atomisp_acc_fw *
acc_get_fw(struct atomisp_sub_device *asd, unsigned int handle)
{
struct atomisp_acc_fw *acc_fw;
list_for_each_entry(acc_fw, &asd->acc.fw, list)
if (acc_fw->handle == handle)
return acc_fw;
return NULL;
}
static struct atomisp_map *acc_get_map(struct atomisp_sub_device *asd,
unsigned long css_ptr, size_t length)
{
struct atomisp_map *atomisp_map;
list_for_each_entry(atomisp_map, &asd->acc.memory_maps, list) {
if (atomisp_map->ptr == css_ptr &&
atomisp_map->length == length)
return atomisp_map;
}
return NULL;
}
static int acc_stop_acceleration(struct atomisp_sub_device *asd)
{
int ret;
ret = atomisp_css_stop_acc_pipe(asd);
atomisp_css_destroy_acc_pipe(asd);
return ret;
}
void atomisp_acc_cleanup(struct atomisp_device *isp)
{
int i;
for (i = 0; i < isp->num_of_streams; i++)
ida_destroy(&isp->asd[i].acc.ida);
}
void atomisp_acc_release(struct atomisp_sub_device *asd)
{
struct atomisp_acc_fw *acc_fw, *ta;
struct atomisp_map *atomisp_map, *tm;
/* Stop acceleration if already running */
if (asd->acc.pipeline)
acc_stop_acceleration(asd);
/* Unload all loaded acceleration binaries */
list_for_each_entry_safe(acc_fw, ta, &asd->acc.fw, list) {
list_del(&acc_fw->list);
ida_remove(&asd->acc.ida, acc_fw->handle);
acc_free_fw(acc_fw);
}
/* Free all mapped memory blocks */
list_for_each_entry_safe(atomisp_map, tm, &asd->acc.memory_maps, list) {
list_del(&atomisp_map->list);
hmm_free(atomisp_map->ptr);
kfree(atomisp_map);
}
}
int atomisp_acc_load_to_pipe(struct atomisp_sub_device *asd,
struct atomisp_acc_fw_load_to_pipe *user_fw)
{
static const unsigned int pipeline_flags =
ATOMISP_ACC_FW_LOAD_FL_PREVIEW | ATOMISP_ACC_FW_LOAD_FL_COPY |
ATOMISP_ACC_FW_LOAD_FL_VIDEO |
ATOMISP_ACC_FW_LOAD_FL_CAPTURE | ATOMISP_ACC_FW_LOAD_FL_ACC;
struct atomisp_acc_fw *acc_fw;
int handle;
if (!user_fw->data || user_fw->size < sizeof(*acc_fw->fw))
return -EINVAL;
/* Binary has to be enabled at least for one pipeline */
if (!(user_fw->flags & pipeline_flags))
return -EINVAL;
/* We do not support other flags yet */
if (user_fw->flags & ~pipeline_flags)
return -EINVAL;
if (user_fw->type < ATOMISP_ACC_FW_LOAD_TYPE_OUTPUT ||
user_fw->type > ATOMISP_ACC_FW_LOAD_TYPE_STANDALONE)
return -EINVAL;
if (asd->acc.pipeline || asd->acc.extension_mode)
return -EBUSY;
acc_fw = acc_alloc_fw(user_fw->size);
if (!acc_fw)
return -ENOMEM;
if (copy_from_user(acc_fw->fw, user_fw->data, user_fw->size)) {
acc_free_fw(acc_fw);
return -EFAULT;
}
if (!ida_pre_get(&asd->acc.ida, GFP_KERNEL) ||
ida_get_new_above(&asd->acc.ida, 1, &handle)) {
acc_free_fw(acc_fw);
return -ENOSPC;
}
user_fw->fw_handle = handle;
acc_fw->handle = handle;
acc_fw->flags = user_fw->flags;
acc_fw->type = user_fw->type;
acc_fw->fw->handle = handle;
/*
* correct isp firmware type in order ISP firmware can be appended
* to correct pipe properly
*/
if (acc_fw->fw->type == ia_css_isp_firmware) {
static const int type_to_css[] = {
[ATOMISP_ACC_FW_LOAD_TYPE_OUTPUT] =
IA_CSS_ACC_OUTPUT,
[ATOMISP_ACC_FW_LOAD_TYPE_VIEWFINDER] =
IA_CSS_ACC_VIEWFINDER,
[ATOMISP_ACC_FW_LOAD_TYPE_STANDALONE] =
IA_CSS_ACC_STANDALONE,
};
acc_fw->fw->info.isp.type = type_to_css[acc_fw->type];
}
list_add_tail(&acc_fw->list, &asd->acc.fw);
return 0;
}
int atomisp_acc_load(struct atomisp_sub_device *asd,
struct atomisp_acc_fw_load *user_fw)
{
struct atomisp_acc_fw_load_to_pipe ltp = {0};
int r;
ltp.flags = ATOMISP_ACC_FW_LOAD_FL_ACC;
ltp.type = ATOMISP_ACC_FW_LOAD_TYPE_STANDALONE;
ltp.size = user_fw->size;
ltp.data = user_fw->data;
r = atomisp_acc_load_to_pipe(asd, &ltp);
user_fw->fw_handle = ltp.fw_handle;
return r;
}
int atomisp_acc_unload(struct atomisp_sub_device *asd, unsigned int *handle)
{
struct atomisp_acc_fw *acc_fw;
if (asd->acc.pipeline || asd->acc.extension_mode)
return -EBUSY;
acc_fw = acc_get_fw(asd, *handle);
if (!acc_fw)
return -EINVAL;
list_del(&acc_fw->list);
ida_remove(&asd->acc.ida, acc_fw->handle);
acc_free_fw(acc_fw);
return 0;
}
int atomisp_acc_start(struct atomisp_sub_device *asd, unsigned int *handle)
{
struct atomisp_device *isp = asd->isp;
struct atomisp_acc_fw *acc_fw;
int ret;
unsigned int nbin;
if (asd->acc.pipeline || asd->acc.extension_mode)
return -EBUSY;
/* Invalidate caches. FIXME: should flush only necessary buffers */
wbinvd();
ret = atomisp_css_create_acc_pipe(asd);
if (ret)
return ret;
nbin = 0;
list_for_each_entry(acc_fw, &asd->acc.fw, list) {
if (*handle != 0 && *handle != acc_fw->handle)
continue;
if (acc_fw->type != ATOMISP_ACC_FW_LOAD_TYPE_STANDALONE)
continue;
/* Add the binary into the pipeline */
ret = atomisp_css_load_acc_binary(asd, acc_fw->fw, nbin);
if (ret < 0) {
dev_err(isp->dev, "acc_load_binary failed\n");
goto err_stage;
}
ret = atomisp_css_set_acc_parameters(acc_fw);
if (ret < 0) {
dev_err(isp->dev, "acc_set_parameters failed\n");
goto err_stage;
}
nbin++;
}
if (nbin < 1) {
/* Refuse creating pipelines with no binaries */
dev_err(isp->dev, "%s: no acc binary available\n", __func__);
ret = -EINVAL;
goto err_stage;
}
ret = atomisp_css_start_acc_pipe(asd);
if (ret) {
dev_err(isp->dev, "%s: atomisp_acc_start_acc_pipe failed\n",
__func__);
goto err_stage;
}
return 0;
err_stage:
atomisp_css_destroy_acc_pipe(asd);
return ret;
}
int atomisp_acc_wait(struct atomisp_sub_device *asd, unsigned int *handle)
{
struct atomisp_device *isp = asd->isp;
int ret;
if (!asd->acc.pipeline)
return -ENOENT;
if (*handle && !acc_get_fw(asd, *handle))
return -EINVAL;
ret = atomisp_css_wait_acc_finish(asd);
if (acc_stop_acceleration(asd) == -EIO) {
atomisp_reset(isp);
return -EINVAL;
}
return ret;
}
void atomisp_acc_done(struct atomisp_sub_device *asd, unsigned int handle)
{
struct v4l2_event event = { 0 };
event.type = V4L2_EVENT_ATOMISP_ACC_COMPLETE;
event.u.frame_sync.frame_sequence = atomic_read(&asd->sequence);
event.id = handle;
v4l2_event_queue(asd->subdev.devnode, &event);
}
int atomisp_acc_map(struct atomisp_sub_device *asd, struct atomisp_acc_map *map)
{
struct atomisp_map *atomisp_map;
ia_css_ptr cssptr;
int pgnr;
if (map->css_ptr)
return -EINVAL;
if (asd->acc.pipeline)
return -EBUSY;
if (map->user_ptr) {
/* Buffer to map must be page-aligned */
if ((unsigned long)map->user_ptr & ~PAGE_MASK) {
dev_err(asd->isp->dev,
"%s: mapped buffer address %p is not page aligned\n",
__func__, map->user_ptr);
return -EINVAL;
}
pgnr = DIV_ROUND_UP(map->length, PAGE_SIZE);
cssptr = hrt_isp_css_mm_alloc_user_ptr(map->length,
map->user_ptr,
pgnr, HRT_USR_PTR,
(map->flags & ATOMISP_MAP_FLAG_CACHED));
} else {
/* Allocate private buffer. */
if (map->flags & ATOMISP_MAP_FLAG_CACHED)
cssptr = hrt_isp_css_mm_calloc_cached(map->length);
else
cssptr = hrt_isp_css_mm_calloc(map->length);
}
if (!cssptr)
return -ENOMEM;
atomisp_map = kmalloc(sizeof(*atomisp_map), GFP_KERNEL);
if (!atomisp_map) {
hmm_free(cssptr);
return -ENOMEM;
}
atomisp_map->ptr = cssptr;
atomisp_map->length = map->length;
list_add(&atomisp_map->list, &asd->acc.memory_maps);
dev_dbg(asd->isp->dev, "%s: userptr %p, css_address 0x%x, size %d\n",
__func__, map->user_ptr, cssptr, map->length);
map->css_ptr = cssptr;
return 0;
}
int atomisp_acc_unmap(struct atomisp_sub_device *asd, struct atomisp_acc_map *map)
{
struct atomisp_map *atomisp_map;
if (asd->acc.pipeline)
return -EBUSY;
atomisp_map = acc_get_map(asd, map->css_ptr, map->length);
if (!atomisp_map)
return -EINVAL;
list_del(&atomisp_map->list);
hmm_free(atomisp_map->ptr);
kfree(atomisp_map);
return 0;
}
int atomisp_acc_s_mapped_arg(struct atomisp_sub_device *asd,
struct atomisp_acc_s_mapped_arg *arg)
{
struct atomisp_acc_fw *acc_fw;
if (arg->memory >= ATOMISP_ACC_NR_MEMORY)
return -EINVAL;
if (asd->acc.pipeline)
return -EBUSY;
acc_fw = acc_get_fw(asd, arg->fw_handle);
if (!acc_fw)
return -EINVAL;
if (arg->css_ptr != 0 || arg->length != 0) {
/* Unless the parameter is cleared, check that it exists */
if (!acc_get_map(asd, arg->css_ptr, arg->length))
return -EINVAL;
}
acc_fw->args[arg->memory].length = arg->length;
acc_fw->args[arg->memory].css_ptr = arg->css_ptr;
dev_dbg(asd->isp->dev, "%s: mem %d, address %p, size %ld\n",
__func__, arg->memory, (void *)arg->css_ptr,
(unsigned long)arg->length);
return 0;
}
/*
* Appends the loaded acceleration binary extensions to the
* current ISP mode. Must be called just before sh_css_start().
*/
int atomisp_acc_load_extensions(struct atomisp_sub_device *asd)
{
struct atomisp_acc_fw *acc_fw;
bool ext_loaded = false;
bool continuous = asd->continuous_mode->val &&
asd->run_mode->val == ATOMISP_RUN_MODE_PREVIEW;
int ret = 0, i = -1;
struct atomisp_device *isp = asd->isp;
if (asd->acc.pipeline || asd->acc.extension_mode)
return -EBUSY;
/* Invalidate caches. FIXME: should flush only necessary buffers */
wbinvd();
list_for_each_entry(acc_fw, &asd->acc.fw, list) {
if (acc_fw->type != ATOMISP_ACC_FW_LOAD_TYPE_OUTPUT &&
acc_fw->type != ATOMISP_ACC_FW_LOAD_TYPE_VIEWFINDER)
continue;
for (i = 0; i < ARRAY_SIZE(acc_flag_to_pipe); i++) {
/* QoS (ACC pipe) acceleration stages are currently
* allowed only in continuous mode. Skip them for
* all other modes. */
if (!continuous &&
acc_flag_to_pipe[i].flag ==
ATOMISP_ACC_FW_LOAD_FL_ACC)
continue;
if (acc_fw->flags & acc_flag_to_pipe[i].flag) {
ret = atomisp_css_load_acc_extension(asd,
acc_fw->fw,
acc_flag_to_pipe[i].pipe_id,
acc_fw->type);
if (ret)
goto error;
ext_loaded = true;
}
}
ret = atomisp_css_set_acc_parameters(acc_fw);
if (ret < 0)
goto error;
}
if (!ext_loaded)
return ret;
ret = atomisp_css_update_stream(asd);
if (ret) {
dev_err(isp->dev, "%s: update stream failed.\n", __func__);
goto error;
}
asd->acc.extension_mode = true;
return 0;
error:
while (--i >= 0) {
if (acc_fw->flags & acc_flag_to_pipe[i].flag) {
atomisp_css_unload_acc_extension(asd, acc_fw->fw,
acc_flag_to_pipe[i].pipe_id);
}
}
list_for_each_entry_continue_reverse(acc_fw, &asd->acc.fw, list) {
if (acc_fw->type != ATOMISP_ACC_FW_LOAD_TYPE_OUTPUT &&
acc_fw->type != ATOMISP_ACC_FW_LOAD_TYPE_VIEWFINDER)
continue;
for (i = ARRAY_SIZE(acc_flag_to_pipe) - 1; i >= 0; i--) {
if (!continuous &&
acc_flag_to_pipe[i].flag ==
ATOMISP_ACC_FW_LOAD_FL_ACC)
continue;
if (acc_fw->flags & acc_flag_to_pipe[i].flag) {
atomisp_css_unload_acc_extension(asd,
acc_fw->fw,
acc_flag_to_pipe[i].pipe_id);
}
}
}
return ret;
}
void atomisp_acc_unload_extensions(struct atomisp_sub_device *asd)
{
struct atomisp_acc_fw *acc_fw;
int i;
if (!asd->acc.extension_mode)
return;
list_for_each_entry_reverse(acc_fw, &asd->acc.fw, list) {
if (acc_fw->type != ATOMISP_ACC_FW_LOAD_TYPE_OUTPUT &&
acc_fw->type != ATOMISP_ACC_FW_LOAD_TYPE_VIEWFINDER)
continue;
for (i = ARRAY_SIZE(acc_flag_to_pipe) - 1; i >= 0; i--) {
if (acc_fw->flags & acc_flag_to_pipe[i].flag) {
atomisp_css_unload_acc_extension(asd,
acc_fw->fw,
acc_flag_to_pipe[i].pipe_id);
}
}
}
asd->acc.extension_mode = false;
}
int atomisp_acc_set_state(struct atomisp_sub_device *asd,
struct atomisp_acc_state *arg)
{
struct atomisp_acc_fw *acc_fw;
bool enable = (arg->flags & ATOMISP_STATE_FLAG_ENABLE) != 0;
struct ia_css_pipe *pipe;
enum ia_css_err r;
int i;
if (!asd->acc.extension_mode)
return -EBUSY;
if (arg->flags & ~ATOMISP_STATE_FLAG_ENABLE)
return -EINVAL;
acc_fw = acc_get_fw(asd, arg->fw_handle);
if (!acc_fw)
return -EINVAL;
if (enable)
wbinvd();
for (i = 0; i < ARRAY_SIZE(acc_flag_to_pipe); i++) {
if (acc_fw->flags & acc_flag_to_pipe[i].flag) {
pipe = asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].
pipes[acc_flag_to_pipe[i].pipe_id];
r = ia_css_pipe_set_qos_ext_state(pipe, acc_fw->handle,
enable);
if (r != IA_CSS_SUCCESS)
return -EBADRQC;
}
}
if (enable)
acc_fw->flags |= ATOMISP_ACC_FW_LOAD_FL_ENABLE;
else
acc_fw->flags &= ~ATOMISP_ACC_FW_LOAD_FL_ENABLE;
return 0;
}
int atomisp_acc_get_state(struct atomisp_sub_device *asd,
struct atomisp_acc_state *arg)
{
struct atomisp_acc_fw *acc_fw;
if (!asd->acc.extension_mode)
return -EBUSY;
acc_fw = acc_get_fw(asd, arg->fw_handle);
if (!acc_fw)
return -EINVAL;
arg->flags = acc_fw->flags;
return 0;
}

120
drivers/staging/media/atomisp/pci/atomisp2/atomisp_acc.h
View File

@ -1,120 +0,0 @@
/*
* Support for Clovertrail PNW Camera Imaging ISP subsystem.
*
* Copyright (c) 2012 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
*/
#ifndef __ATOMISP_ACC_H__
#define __ATOMISP_ACC_H__
#include "../../include/linux/atomisp.h"
#include "atomisp_internal.h"
#include "ia_css_types.h"
/*
* Interface functions for AtomISP driver acceleration API implementation.
*/
struct atomisp_sub_device;
void atomisp_acc_cleanup(struct atomisp_device *isp);
/*
* Free up any allocated resources.
* Must be called each time when the device is closed.
* Note that there isn't corresponding open() call;
* this function may be called sequentially multiple times.
* Must be called to free up resources before driver is unloaded.
*/
void atomisp_acc_release(struct atomisp_sub_device *asd);
/* Load acceleration binary. DEPRECATED. */
int atomisp_acc_load(struct atomisp_sub_device *asd,
struct atomisp_acc_fw_load *fw);
/* Load acceleration binary with specified properties */
int atomisp_acc_load_to_pipe(struct atomisp_sub_device *asd,
struct atomisp_acc_fw_load_to_pipe *fw);
/* Unload specified acceleration binary */
int atomisp_acc_unload(struct atomisp_sub_device *asd,
unsigned int *handle);
/*
* Map a memory region into ISP memory space.
*/
int atomisp_acc_map(struct atomisp_sub_device *asd,
struct atomisp_acc_map *map);
/*
* Unmap a mapped memory region.
*/
int atomisp_acc_unmap(struct atomisp_sub_device *asd,
struct atomisp_acc_map *map);
/*
* Set acceleration binary argument to a previously mapped memory region.
*/
int atomisp_acc_s_mapped_arg(struct atomisp_sub_device *asd,
struct atomisp_acc_s_mapped_arg *arg);
/*
* Start acceleration.
* Return immediately, acceleration is left running in background.
* Specify either acceleration binary or pipeline which to start.
*/
int atomisp_acc_start(struct atomisp_sub_device *asd,
unsigned int *handle);
/*
* Wait until acceleration finishes.
* This MUST be called after each acceleration has been started.
* Specify either acceleration binary or pipeline handle.
*/
int atomisp_acc_wait(struct atomisp_sub_device *asd,
unsigned int *handle);
/*
* Used by ISR to notify ACC stage finished.
* This is internally used and does not export as IOCTL.
*/
void atomisp_acc_done(struct atomisp_sub_device *asd, unsigned int handle);
/*
* Appends the loaded acceleration binary extensions to the
* current ISP mode. Must be called just before atomisp_css_start().
*/
int atomisp_acc_load_extensions(struct atomisp_sub_device *asd);
/*
* Must be called after streaming is stopped:
* unloads any loaded acceleration extensions.
*/
void atomisp_acc_unload_extensions(struct atomisp_sub_device *asd);
/*
* Set acceleration firmware flags.
*/
int atomisp_acc_set_state(struct atomisp_sub_device *asd,
struct atomisp_acc_state *arg);
/*
* Get acceleration firmware flags.
*/
int atomisp_acc_get_state(struct atomisp_sub_device *asd,
struct atomisp_acc_state *arg);
#endif /* __ATOMISP_ACC_H__ */

6697
drivers/staging/media/atomisp/pci/atomisp2/atomisp_cmd.c
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File diff suppressed because it is too large Load Diff

446
drivers/staging/media/atomisp/pci/atomisp2/atomisp_cmd.h
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@ -1,446 +0,0 @@
/*
* Support for Medifield PNW Camera Imaging ISP subsystem.
*
* Copyright (c) 2010 Intel Corporation. All Rights Reserved.
*
* Copyright (c) 2010 Silicon Hive www.siliconhive.com.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
*/
#ifndef __ATOMISP_CMD_H__
#define __ATOMISP_CMD_H__
#include "../../include/linux/atomisp.h"
#include <linux/interrupt.h>
#include <linux/videodev2.h>
#include <media/v4l2-subdev.h>
#include "atomisp_internal.h"
#include "ia_css_types.h"
#include "ia_css.h"
struct atomisp_device;
struct atomisp_css_frame;
#define MSI_ENABLE_BIT 16
#define INTR_DISABLE_BIT 10
#define BUS_MASTER_ENABLE 2
#define MEMORY_SPACE_ENABLE 1
#define INTR_IER 24
#define INTR_IIR 16
#ifdef ISP2401
#define RUNMODE_MASK (ATOMISP_RUN_MODE_VIDEO | ATOMISP_RUN_MODE_STILL_CAPTURE \
| ATOMISP_RUN_MODE_PREVIEW)
/* FIXME: check if can go */
extern int atomisp_punit_hpll_freq;
#endif
/*
* Helper function
*/
void dump_sp_dmem(struct atomisp_device *isp, unsigned int addr,
unsigned int size);
struct camera_mipi_info *atomisp_to_sensor_mipi_info(struct v4l2_subdev *sd);
struct atomisp_video_pipe *atomisp_to_video_pipe(struct video_device *dev);
struct atomisp_acc_pipe *atomisp_to_acc_pipe(struct video_device *dev);
int atomisp_reset(struct atomisp_device *isp);
void atomisp_flush_bufs_and_wakeup(struct atomisp_sub_device *asd);
void atomisp_clear_css_buffer_counters(struct atomisp_sub_device *asd);
#ifndef ISP2401
bool atomisp_buffers_queued(struct atomisp_sub_device *asd);
#else
bool atomisp_buffers_queued_pipe(struct atomisp_video_pipe *pipe);
#endif
/* TODO:should be here instead of atomisp_helper.h
extern void __iomem *atomisp_io_base;
static inline void __iomem *atomisp_get_io_virt_addr(unsigned int address)
{
void __iomem *ret = atomisp_io_base + (address & 0x003FFFFF);
return ret;
}
*/
/*
* Interrupt functions
*/
void atomisp_msi_irq_init(struct atomisp_device *isp, struct pci_dev *dev);
void atomisp_msi_irq_uninit(struct atomisp_device *isp, struct pci_dev *dev);
void atomisp_wdt_work(struct work_struct *work);
void atomisp_wdt(struct timer_list *t);
void atomisp_setup_flash(struct atomisp_sub_device *asd);
irqreturn_t atomisp_isr(int irq, void *dev);
irqreturn_t atomisp_isr_thread(int irq, void *isp_ptr);
const struct atomisp_format_bridge *get_atomisp_format_bridge_from_mbus(
u32 mbus_code);
bool atomisp_is_mbuscode_raw(uint32_t code);
int atomisp_get_frame_pgnr(struct atomisp_device *isp,
const struct atomisp_css_frame *frame, u32 *p_pgnr);
void atomisp_delayed_init_work(struct work_struct *work);
/*
* Get internal fmt according to V4L2 fmt
*/
bool atomisp_is_viewfinder_support(struct atomisp_device *isp);
/*
* ISP features control function
*/
/*
#ifdef ISP2401
* Function to set sensor runmode by user when
* ATOMISP_IOC_S_SENSOR_RUNMODE ioctl was called
*/
int atomisp_set_sensor_runmode(struct atomisp_sub_device *asd,
struct atomisp_s_runmode *runmode);
/*
#endif
* Function to enable/disable lens geometry distortion correction (GDC) and
* chromatic aberration correction (CAC)
*/
int atomisp_gdc_cac(struct atomisp_sub_device *asd, int flag,
__s32 *value);
/*
* Function to enable/disable low light mode (including ANR)
*/
int atomisp_low_light(struct atomisp_sub_device *asd, int flag,
__s32 *value);
/*
* Function to enable/disable extra noise reduction (XNR) in low light
* condition
*/
int atomisp_xnr(struct atomisp_sub_device *asd, int flag, int *arg);
int atomisp_formats(struct atomisp_sub_device *asd, int flag,
struct atomisp_formats_config *config);
/*
* Function to configure noise reduction
*/
int atomisp_nr(struct atomisp_sub_device *asd, int flag,
struct atomisp_nr_config *config);
/*
* Function to configure temporal noise reduction (TNR)
*/
int atomisp_tnr(struct atomisp_sub_device *asd, int flag,
struct atomisp_tnr_config *config);
/*
* Function to configure black level compensation
*/
int atomisp_black_level(struct atomisp_sub_device *asd, int flag,
struct atomisp_ob_config *config);
/*
* Function to configure edge enhancement
*/
int atomisp_ee(struct atomisp_sub_device *asd, int flag,
struct atomisp_ee_config *config);
/*
* Function to update Gamma table for gamma, brightness and contrast config
*/
int atomisp_gamma(struct atomisp_sub_device *asd, int flag,
struct atomisp_gamma_table *config);
/*
* Function to update Ctc table for Chroma Enhancement
*/
int atomisp_ctc(struct atomisp_sub_device *asd, int flag,
struct atomisp_ctc_table *config);
/*
* Function to update gamma correction parameters
*/
int atomisp_gamma_correction(struct atomisp_sub_device *asd, int flag,
struct atomisp_gc_config *config);
/*
* Function to update Gdc table for gdc
*/
int atomisp_gdc_cac_table(struct atomisp_sub_device *asd, int flag,
struct atomisp_morph_table *config);
/*
* Function to update table for macc
*/
int atomisp_macc_table(struct atomisp_sub_device *asd, int flag,
struct atomisp_macc_config *config);
/*
* Function to get DIS statistics.
*/
int atomisp_get_dis_stat(struct atomisp_sub_device *asd,
struct atomisp_dis_statistics *stats);
/*
* Function to get DVS2 BQ resolution settings
*/
int atomisp_get_dvs2_bq_resolutions(struct atomisp_sub_device *asd,
struct atomisp_dvs2_bq_resolutions *bq_res);
/*
* Function to set the DIS coefficients.
*/
int atomisp_set_dis_coefs(struct atomisp_sub_device *asd,
struct atomisp_dis_coefficients *coefs);
/*
* Function to set the DIS motion vector.
*/
int atomisp_set_dis_vector(struct atomisp_sub_device *asd,
struct atomisp_dis_vector *vector);
/*
* Function to set/get 3A stat from isp
*/
int atomisp_3a_stat(struct atomisp_sub_device *asd, int flag,
struct atomisp_3a_statistics *config);
/*
* Function to get metadata from isp
*/
int atomisp_get_metadata(struct atomisp_sub_device *asd, int flag,
struct atomisp_metadata *config);
int atomisp_get_metadata_by_type(struct atomisp_sub_device *asd, int flag,
struct atomisp_metadata_with_type *config);
int atomisp_set_parameters(struct video_device *vdev,
struct atomisp_parameters *arg);
/*
* Function to set/get isp parameters to isp
*/
int atomisp_param(struct atomisp_sub_device *asd, int flag,
struct atomisp_parm *config);
/*
* Function to configure color effect of the image
*/
int atomisp_color_effect(struct atomisp_sub_device *asd, int flag,
__s32 *effect);
/*
* Function to configure bad pixel correction
*/
int atomisp_bad_pixel(struct atomisp_sub_device *asd, int flag,
__s32 *value);
/*
* Function to configure bad pixel correction params
*/
int atomisp_bad_pixel_param(struct atomisp_sub_device *asd, int flag,
struct atomisp_dp_config *config);
/*
* Function to enable/disable video image stablization
*/
int atomisp_video_stable(struct atomisp_sub_device *asd, int flag,
__s32 *value);
/*
* Function to configure fixed pattern noise
*/
int atomisp_fixed_pattern(struct atomisp_sub_device *asd, int flag,
__s32 *value);
/*
* Function to configure fixed pattern noise table
*/
int atomisp_fixed_pattern_table(struct atomisp_sub_device *asd,
struct v4l2_framebuffer *config);
/*
* Function to configure false color correction
*/
int atomisp_false_color(struct atomisp_sub_device *asd, int flag,
__s32 *value);
/*
* Function to configure false color correction params
*/
int atomisp_false_color_param(struct atomisp_sub_device *asd, int flag,
struct atomisp_de_config *config);
/*
* Function to configure white balance params
*/
int atomisp_white_balance_param(struct atomisp_sub_device *asd, int flag,
struct atomisp_wb_config *config);
int atomisp_3a_config_param(struct atomisp_sub_device *asd, int flag,
struct atomisp_3a_config *config);
/*
* Function to setup digital zoom
*/
int atomisp_digital_zoom(struct atomisp_sub_device *asd, int flag,
__s32 *value);
/*
* Function set camera_prefiles.xml current sensor pixel array size
*/
int atomisp_set_array_res(struct atomisp_sub_device *asd,
struct atomisp_resolution *config);
/*
* Function to calculate real zoom region for every pipe
*/
int atomisp_calculate_real_zoom_region(struct atomisp_sub_device *asd,
struct atomisp_css_dz_config *dz_config,
enum atomisp_css_pipe_id css_pipe_id);
int atomisp_cp_general_isp_parameters(struct atomisp_sub_device *asd,
struct atomisp_parameters *arg,
struct atomisp_css_params *css_param,
bool from_user);
int atomisp_cp_lsc_table(struct atomisp_sub_device *asd,
struct atomisp_shading_table *source_st,
struct atomisp_css_params *css_param,
bool from_user);
int atomisp_css_cp_dvs2_coefs(struct atomisp_sub_device *asd,
struct ia_css_dvs2_coefficients *coefs,
struct atomisp_css_params *css_param,
bool from_user);
int atomisp_cp_morph_table(struct atomisp_sub_device *asd,
struct atomisp_morph_table *source_morph_table,
struct atomisp_css_params *css_param,
bool from_user);
int atomisp_cp_dvs_6axis_config(struct atomisp_sub_device *asd,
struct atomisp_dvs_6axis_config *user_6axis_config,
struct atomisp_css_params *css_param,
bool from_user);
int atomisp_makeup_css_parameters(struct atomisp_sub_device *asd,
struct atomisp_parameters *arg,
struct atomisp_css_params *css_param);
int atomisp_compare_grid(struct atomisp_sub_device *asd,
struct atomisp_grid_info *atomgrid);
int atomisp_get_sensor_mode_data(struct atomisp_sub_device *asd,
struct atomisp_sensor_mode_data *config);
int atomisp_get_fmt(struct video_device *vdev, struct v4l2_format *f);
/* This function looks up the closest available resolution. */
int atomisp_try_fmt(struct video_device *vdev, struct v4l2_format *f,
bool *res_overflow);
int atomisp_set_fmt(struct video_device *vdev, struct v4l2_format *f);
int atomisp_set_fmt_file(struct video_device *vdev, struct v4l2_format *f);
int atomisp_set_shading_table(struct atomisp_sub_device *asd,
struct atomisp_shading_table *shading_table);
int atomisp_offline_capture_configure(struct atomisp_sub_device *asd,
struct atomisp_cont_capture_conf *cvf_config);
int atomisp_ospm_dphy_down(struct atomisp_device *isp);
int atomisp_ospm_dphy_up(struct atomisp_device *isp);
int atomisp_exif_makernote(struct atomisp_sub_device *asd,
struct atomisp_makernote_info *config);
void atomisp_free_internal_buffers(struct atomisp_sub_device *asd);
int atomisp_s_ae_window(struct atomisp_sub_device *asd,
struct atomisp_ae_window *arg);
int atomisp_flash_enable(struct atomisp_sub_device *asd,
int num_frames);
int atomisp_freq_scaling(struct atomisp_device *vdev,
enum atomisp_dfs_mode mode,
bool force);
void atomisp_buf_done(struct atomisp_sub_device *asd, int error,
enum atomisp_css_buffer_type buf_type,
enum atomisp_css_pipe_id css_pipe_id,
bool q_buffers, enum atomisp_input_stream_id stream_id);
void atomisp_css_flush(struct atomisp_device *isp);
int atomisp_source_pad_to_stream_id(struct atomisp_sub_device *asd,
uint16_t source_pad);
/*
* Events. Only one event has to be exported for now.
*/
void atomisp_eof_event(struct atomisp_sub_device *asd, uint8_t exp_id);
enum mipi_port_id __get_mipi_port(struct atomisp_device *isp,
enum atomisp_camera_port port);
bool atomisp_is_vf_pipe(struct atomisp_video_pipe *pipe);
void atomisp_apply_css_parameters(
struct atomisp_sub_device *asd,
struct atomisp_css_params *css_param);
void atomisp_free_css_parameters(struct atomisp_css_params *css_param);
void atomisp_handle_parameter_and_buffer(struct atomisp_video_pipe *pipe);
void atomisp_flush_params_queue(struct atomisp_video_pipe *asd);
/*
* Function to do Raw Buffer related operation, after enable Lock Unlock Raw Buffer
*/
int atomisp_exp_id_unlock(struct atomisp_sub_device *asd, int *exp_id);
int atomisp_exp_id_capture(struct atomisp_sub_device *asd, int *exp_id);
/*
* Function to update Raw Buffer bitmap
*/
int atomisp_set_raw_buffer_bitmap(struct atomisp_sub_device *asd, int exp_id);
void atomisp_init_raw_buffer_bitmap(struct atomisp_sub_device *asd);
/*
* Function to enable/disable zoom for capture pipe
*/
int atomisp_enable_dz_capt_pipe(struct atomisp_sub_device *asd,
unsigned int *enable);
/*
* Function to get metadata type bu pipe id
*/
enum atomisp_metadata_type
atomisp_get_metadata_type(struct atomisp_sub_device *asd,
enum ia_css_pipe_id pipe_id);
/*
* Function for HAL to inject a fake event to wake up poll thread
*/
int atomisp_inject_a_fake_event(struct atomisp_sub_device *asd, int *event);
/*
* Function for HAL to query how many invalid frames at the beginning of ISP
* pipeline output
*/
int atomisp_get_invalid_frame_num(struct video_device *vdev,
int *invalid_frame_num);
int atomisp_mrfld_power_up(struct atomisp_device *isp);
int atomisp_mrfld_power_down(struct atomisp_device *isp);
int atomisp_runtime_suspend(struct device *dev);
int atomisp_runtime_resume(struct device *dev);
#endif /* __ATOMISP_CMD_H__ */

75
drivers/staging/media/atomisp/pci/atomisp2/atomisp_common.h
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@ -1,75 +0,0 @@
/*
* Support for Medifield PNW Camera Imaging ISP subsystem.
*
* Copyright (c) 2010 Intel Corporation. All Rights Reserved.
*
* Copyright (c) 2010 Silicon Hive www.siliconhive.com.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
*/
#ifndef __ATOMISP_COMMON_H__
#define __ATOMISP_COMMON_H__
#include "../../include/linux/atomisp.h"
#include <linux/v4l2-mediabus.h>
#include <media/videobuf-core.h>
#include "atomisp_compat.h"
#include "ia_css.h"
extern int dbg_level;
extern int dbg_func;
extern int mipicsi_flag;
extern int pad_w;
extern int pad_h;
#define CSS_DTRACE_VERBOSITY_LEVEL 5 /* Controls trace verbosity */
#define CSS_DTRACE_VERBOSITY_TIMEOUT 9 /* Verbosity on ISP timeout */
#define MRFLD_MAX_ZOOM_FACTOR 1024
#ifdef ISP2401
#define ATOMISP_CSS_ISP_PIPE_VERSION_2_2 0
#define ATOMISP_CSS_ISP_PIPE_VERSION_2_7 1
#endif
#define IS_ISP2401(isp) \
(((isp)->media_dev.hw_revision & ATOMISP_HW_REVISION_MASK) \
>= (ATOMISP_HW_REVISION_ISP2401_LEGACY << ATOMISP_HW_REVISION_SHIFT))
struct atomisp_format_bridge {
unsigned int pixelformat;
unsigned int depth;
u32 mbus_code;
enum atomisp_css_frame_format sh_fmt;
unsigned char description[32]; /* the same as struct v4l2_fmtdesc */
bool planar;
};
struct atomisp_fmt {
u32 pixelformat;
u32 depth;
u32 bytesperline;
u32 framesize;
u32 imagesize;
u32 width;
u32 height;
u32 bayer_order;
};
struct atomisp_buffer {
struct videobuf_buffer vb;
};
#endif

662
drivers/staging/media/atomisp/pci/atomisp2/atomisp_compat.h
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@ -1,662 +0,0 @@
/*
* Support for Clovertrail PNW Camera Imaging ISP subsystem.
*
* Copyright (c) 2012 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
*/
#ifndef __ATOMISP_COMPAT_H__
#define __ATOMISP_COMPAT_H__
#include "atomisp_compat_css20.h"
#include "../../include/linux/atomisp.h"
#include <media/videobuf-vmalloc.h>
#define CSS_RX_IRQ_INFO_BUFFER_OVERRUN \
CSS_ID(CSS_RX_IRQ_INFO_BUFFER_OVERRUN)
#define CSS_RX_IRQ_INFO_ENTER_SLEEP_MODE \
CSS_ID(CSS_RX_IRQ_INFO_ENTER_SLEEP_MODE)
#define CSS_RX_IRQ_INFO_EXIT_SLEEP_MODE \
CSS_ID(CSS_RX_IRQ_INFO_EXIT_SLEEP_MODE)
#define CSS_RX_IRQ_INFO_ECC_CORRECTED \
CSS_ID(CSS_RX_IRQ_INFO_ECC_CORRECTED)
#define CSS_RX_IRQ_INFO_ERR_SOT \
CSS_ID(CSS_RX_IRQ_INFO_ERR_SOT)
#define CSS_RX_IRQ_INFO_ERR_SOT_SYNC \
CSS_ID(CSS_RX_IRQ_INFO_ERR_SOT_SYNC)
#define CSS_RX_IRQ_INFO_ERR_CONTROL \
CSS_ID(CSS_RX_IRQ_INFO_ERR_CONTROL)
#define CSS_RX_IRQ_INFO_ERR_ECC_DOUBLE \
CSS_ID(CSS_RX_IRQ_INFO_ERR_ECC_DOUBLE)
#define CSS_RX_IRQ_INFO_ERR_CRC \
CSS_ID(CSS_RX_IRQ_INFO_ERR_CRC)
#define CSS_RX_IRQ_INFO_ERR_UNKNOWN_ID \
CSS_ID(CSS_RX_IRQ_INFO_ERR_UNKNOWN_ID)
#define CSS_RX_IRQ_INFO_ERR_FRAME_SYNC \
CSS_ID(CSS_RX_IRQ_INFO_ERR_FRAME_SYNC)
#define CSS_RX_IRQ_INFO_ERR_FRAME_DATA \
CSS_ID(CSS_RX_IRQ_INFO_ERR_FRAME_DATA)
#define CSS_RX_IRQ_INFO_ERR_DATA_TIMEOUT \
CSS_ID(CSS_RX_IRQ_INFO_ERR_DATA_TIMEOUT)
#define CSS_RX_IRQ_INFO_ERR_UNKNOWN_ESC \
CSS_ID(CSS_RX_IRQ_INFO_ERR_UNKNOWN_ESC)
#define CSS_RX_IRQ_INFO_ERR_LINE_SYNC \
CSS_ID(CSS_RX_IRQ_INFO_ERR_LINE_SYNC)
#define CSS_RX_IRQ_INFO_INIT_TIMEOUT \
CSS_ID(CSS_RX_IRQ_INFO_INIT_TIMEOUT)
#define CSS_IRQ_INFO_CSS_RECEIVER_SOF CSS_ID(CSS_IRQ_INFO_CSS_RECEIVER_SOF)
#define CSS_IRQ_INFO_CSS_RECEIVER_EOF CSS_ID(CSS_IRQ_INFO_CSS_RECEIVER_EOF)
#define CSS_IRQ_INFO_CSS_RECEIVER_FIFO_OVERFLOW \
CSS_ID(CSS_IRQ_INFO_CSS_RECEIVER_FIFO_OVERFLOW)
#define CSS_EVENT_OUTPUT_FRAME_DONE CSS_EVENT(OUTPUT_FRAME_DONE)
#define CSS_EVENT_SEC_OUTPUT_FRAME_DONE CSS_EVENT(SECOND_OUTPUT_FRAME_DONE)
#define CSS_EVENT_VF_OUTPUT_FRAME_DONE CSS_EVENT(VF_OUTPUT_FRAME_DONE)
#define CSS_EVENT_SEC_VF_OUTPUT_FRAME_DONE CSS_EVENT(SECOND_VF_OUTPUT_FRAME_DONE)
#define CSS_EVENT_3A_STATISTICS_DONE CSS_EVENT(3A_STATISTICS_DONE)
#define CSS_EVENT_DIS_STATISTICS_DONE CSS_EVENT(DIS_STATISTICS_DONE)
#define CSS_EVENT_PIPELINE_DONE CSS_EVENT(PIPELINE_DONE)
#define CSS_EVENT_METADATA_DONE CSS_EVENT(METADATA_DONE)
#define CSS_EVENT_ACC_STAGE_COMPLETE CSS_EVENT(ACC_STAGE_COMPLETE)
#define CSS_EVENT_TIMER CSS_EVENT(TIMER)
#define CSS_BUFFER_TYPE_METADATA CSS_ID(CSS_BUFFER_TYPE_METADATA)
#define CSS_BUFFER_TYPE_3A_STATISTICS CSS_ID(CSS_BUFFER_TYPE_3A_STATISTICS)
#define CSS_BUFFER_TYPE_DIS_STATISTICS CSS_ID(CSS_BUFFER_TYPE_DIS_STATISTICS)
#define CSS_BUFFER_TYPE_INPUT_FRAME CSS_ID(CSS_BUFFER_TYPE_INPUT_FRAME)
#define CSS_BUFFER_TYPE_OUTPUT_FRAME CSS_ID(CSS_BUFFER_TYPE_OUTPUT_FRAME)
#define CSS_BUFFER_TYPE_SEC_OUTPUT_FRAME CSS_ID(CSS_BUFFER_TYPE_SEC_OUTPUT_FRAME)
#define CSS_BUFFER_TYPE_VF_OUTPUT_FRAME CSS_ID(CSS_BUFFER_TYPE_VF_OUTPUT_FRAME)
#define CSS_BUFFER_TYPE_SEC_VF_OUTPUT_FRAME CSS_ID(CSS_BUFFER_TYPE_SEC_VF_OUTPUT_FRAME)
#define CSS_BUFFER_TYPE_RAW_OUTPUT_FRAME \
CSS_ID(CSS_BUFFER_TYPE_RAW_OUTPUT_FRAME)
#define CSS_FORMAT_RAW_8 CSS_FORMAT(RAW_8)
#define CSS_FORMAT_RAW_10 CSS_FORMAT(RAW_10)
#define CSS_FORMAT_RAW_12 CSS_FORMAT(RAW_12)
#define CSS_FORMAT_RAW_16 CSS_FORMAT(RAW_16)
#define CSS_CAPTURE_MODE_RAW CSS_ID(CSS_CAPTURE_MODE_RAW)
#define CSS_CAPTURE_MODE_BAYER CSS_ID(CSS_CAPTURE_MODE_BAYER)
#define CSS_CAPTURE_MODE_PRIMARY CSS_ID(CSS_CAPTURE_MODE_PRIMARY)
#define CSS_CAPTURE_MODE_ADVANCED CSS_ID(CSS_CAPTURE_MODE_ADVANCED)
#define CSS_CAPTURE_MODE_LOW_LIGHT CSS_ID(CSS_CAPTURE_MODE_LOW_LIGHT)
#define CSS_MORPH_TABLE_NUM_PLANES CSS_ID(CSS_MORPH_TABLE_NUM_PLANES)
#define CSS_FRAME_FORMAT_NV11 CSS_ID(CSS_FRAME_FORMAT_NV11)
#define CSS_FRAME_FORMAT_NV12 CSS_ID(CSS_FRAME_FORMAT_NV12)
#define CSS_FRAME_FORMAT_NV16 CSS_ID(CSS_FRAME_FORMAT_NV16)
#define CSS_FRAME_FORMAT_NV21 CSS_ID(CSS_FRAME_FORMAT_NV21)
#define CSS_FRAME_FORMAT_NV61 CSS_ID(CSS_FRAME_FORMAT_NV61)
#define CSS_FRAME_FORMAT_YV12 CSS_ID(CSS_FRAME_FORMAT_YV12)
#define CSS_FRAME_FORMAT_YV16 CSS_ID(CSS_FRAME_FORMAT_YV16)
#define CSS_FRAME_FORMAT_YUV420 CSS_ID(CSS_FRAME_FORMAT_YUV420)
#define CSS_FRAME_FORMAT_YUV420_16 CSS_ID(CSS_FRAME_FORMAT_YUV420_16)
#define CSS_FRAME_FORMAT_YUV422 CSS_ID(CSS_FRAME_FORMAT_YUV422)
#define CSS_FRAME_FORMAT_YUV422_16 CSS_ID(CSS_FRAME_FORMAT_YUV422_16)
#define CSS_FRAME_FORMAT_UYVY CSS_ID(CSS_FRAME_FORMAT_UYVY)
#define CSS_FRAME_FORMAT_YUYV CSS_ID(CSS_FRAME_FORMAT_YUYV)
#define CSS_FRAME_FORMAT_YUV444 CSS_ID(CSS_FRAME_FORMAT_YUV444)
#define CSS_FRAME_FORMAT_YUV_LINE CSS_ID(CSS_FRAME_FORMAT_YUV_LINE)
#define CSS_FRAME_FORMAT_RAW CSS_ID(CSS_FRAME_FORMAT_RAW)
#define CSS_FRAME_FORMAT_RGB565 CSS_ID(CSS_FRAME_FORMAT_RGB565)
#define CSS_FRAME_FORMAT_PLANAR_RGB888 CSS_ID(CSS_FRAME_FORMAT_PLANAR_RGB888)
#define CSS_FRAME_FORMAT_RGBA888 CSS_ID(CSS_FRAME_FORMAT_RGBA888)
#define CSS_FRAME_FORMAT_QPLANE6 CSS_ID(CSS_FRAME_FORMAT_QPLANE6)
#define CSS_FRAME_FORMAT_BINARY_8 CSS_ID(CSS_FRAME_FORMAT_BINARY_8)
struct atomisp_device;
struct atomisp_sub_device;
struct video_device;
enum atomisp_input_stream_id;
struct atomisp_metadata_buf {
struct ia_css_metadata *metadata;
void *md_vptr;
struct list_head list;
};
void atomisp_css_debug_dump_sp_sw_debug_info(void);
void atomisp_css_debug_dump_debug_info(const char *context);
void atomisp_css_debug_set_dtrace_level(const unsigned int trace_level);
void atomisp_store_uint32(hrt_address addr, uint32_t data);
void atomisp_load_uint32(hrt_address addr, uint32_t *data);
int atomisp_css_init(struct atomisp_device *isp);
void atomisp_css_uninit(struct atomisp_device *isp);
void atomisp_css_suspend(struct atomisp_device *isp);
int atomisp_css_resume(struct atomisp_device *isp);
void atomisp_css_init_struct(struct atomisp_sub_device *asd);
int atomisp_css_irq_translate(struct atomisp_device *isp,
unsigned int *infos);
void atomisp_css_rx_get_irq_info(enum mipi_port_id port,
unsigned int *infos);
void atomisp_css_rx_clear_irq_info(enum mipi_port_id port,
unsigned int infos);
int atomisp_css_irq_enable(struct atomisp_device *isp,
enum atomisp_css_irq_info info, bool enable);
int atomisp_q_video_buffer_to_css(struct atomisp_sub_device *asd,
struct videobuf_vmalloc_memory *vm_mem,
enum atomisp_input_stream_id stream_id,
enum atomisp_css_buffer_type css_buf_type,
enum atomisp_css_pipe_id css_pipe_id);
int atomisp_q_s3a_buffer_to_css(struct atomisp_sub_device *asd,
struct atomisp_s3a_buf *s3a_buf,
enum atomisp_input_stream_id stream_id,
enum atomisp_css_pipe_id css_pipe_id);
int atomisp_q_metadata_buffer_to_css(struct atomisp_sub_device *asd,
struct atomisp_metadata_buf *metadata_buf,
enum atomisp_input_stream_id stream_id,
enum atomisp_css_pipe_id css_pipe_id);
int atomisp_q_dis_buffer_to_css(struct atomisp_sub_device *asd,
struct atomisp_dis_buf *dis_buf,
enum atomisp_input_stream_id stream_id,
enum atomisp_css_pipe_id css_pipe_id);
void atomisp_css_mmu_invalidate_cache(void);
void atomisp_css_mmu_invalidate_tlb(void);
int atomisp_css_start(struct atomisp_sub_device *asd,
enum atomisp_css_pipe_id pipe_id, bool in_reset);
void atomisp_css_update_isp_params(struct atomisp_sub_device *asd);
void atomisp_css_update_isp_params_on_pipe(struct atomisp_sub_device *asd,
struct ia_css_pipe *pipe);
int atomisp_css_queue_buffer(struct atomisp_sub_device *asd,
enum atomisp_input_stream_id stream_id,
enum atomisp_css_pipe_id pipe_id,
enum atomisp_css_buffer_type buf_type,
struct atomisp_css_buffer *isp_css_buffer);
int atomisp_css_dequeue_buffer(struct atomisp_sub_device *asd,
enum atomisp_input_stream_id stream_id,
enum atomisp_css_pipe_id pipe_id,
enum atomisp_css_buffer_type buf_type,
struct atomisp_css_buffer *isp_css_buffer);
int atomisp_css_allocate_stat_buffers(struct atomisp_sub_device *asd,
uint16_t stream_id,
struct atomisp_s3a_buf *s3a_buf,
struct atomisp_dis_buf *dis_buf,
struct atomisp_metadata_buf *md_buf);
void atomisp_css_free_stat_buffers(struct atomisp_sub_device *asd);
void atomisp_css_free_3a_buffer(struct atomisp_s3a_buf *s3a_buf);
void atomisp_css_free_dis_buffer(struct atomisp_dis_buf *dis_buf);
void atomisp_css_free_metadata_buffer(struct atomisp_metadata_buf *metadata_buf);
int atomisp_css_get_grid_info(struct atomisp_sub_device *asd,
enum atomisp_css_pipe_id pipe_id,
int source_pad);
int atomisp_alloc_3a_output_buf(struct atomisp_sub_device *asd);
int atomisp_alloc_dis_coef_buf(struct atomisp_sub_device *asd);
int atomisp_alloc_metadata_output_buf(struct atomisp_sub_device *asd);
void atomisp_free_metadata_output_buf(struct atomisp_sub_device *asd);
void atomisp_css_get_dis_statistics(struct atomisp_sub_device *asd,
struct atomisp_css_buffer *isp_css_buffer,
struct ia_css_isp_dvs_statistics_map *dvs_map);
int atomisp_css_dequeue_event(struct atomisp_css_event *current_event);
void atomisp_css_temp_pipe_to_pipe_id(struct atomisp_sub_device *asd,
struct atomisp_css_event *current_event);
int atomisp_css_isys_set_resolution(struct atomisp_sub_device *asd,
enum atomisp_input_stream_id stream_id,
struct v4l2_mbus_framefmt *ffmt,
int isys_stream);
void atomisp_css_isys_set_link(struct atomisp_sub_device *asd,
enum atomisp_input_stream_id stream_id,
int link,
int isys_stream);
void atomisp_css_isys_set_valid(struct atomisp_sub_device *asd,
enum atomisp_input_stream_id stream_id,
bool valid,
int isys_stream);
void atomisp_css_isys_set_format(struct atomisp_sub_device *asd,
enum atomisp_input_stream_id stream_id,
enum atomisp_input_format format,
int isys_stream);
int atomisp_css_set_default_isys_config(struct atomisp_sub_device *asd,
enum atomisp_input_stream_id stream_id,
struct v4l2_mbus_framefmt *ffmt);
int atomisp_css_isys_two_stream_cfg(struct atomisp_sub_device *asd,
enum atomisp_input_stream_id stream_id,
enum atomisp_input_format input_format);
void atomisp_css_isys_two_stream_cfg_update_stream1(
struct atomisp_sub_device *asd,
enum atomisp_input_stream_id stream_id,
enum atomisp_input_format input_format,
unsigned int width, unsigned int height);
void atomisp_css_isys_two_stream_cfg_update_stream2(
struct atomisp_sub_device *asd,
enum atomisp_input_stream_id stream_id,
enum atomisp_input_format input_format,
unsigned int width, unsigned int height);
int atomisp_css_input_set_resolution(struct atomisp_sub_device *asd,
enum atomisp_input_stream_id stream_id,
struct v4l2_mbus_framefmt *ffmt);
void atomisp_css_input_set_binning_factor(struct atomisp_sub_device *asd,
enum atomisp_input_stream_id stream_id,
unsigned int bin_factor);
void atomisp_css_input_set_bayer_order(struct atomisp_sub_device *asd,
enum atomisp_input_stream_id stream_id,
enum atomisp_css_bayer_order bayer_order);
void atomisp_css_input_set_format(struct atomisp_sub_device *asd,
enum atomisp_input_stream_id stream_id,
enum atomisp_input_format format);
int atomisp_css_input_set_effective_resolution(
struct atomisp_sub_device *asd,
enum atomisp_input_stream_id stream_id,
unsigned int width,
unsigned int height);
void atomisp_css_video_set_dis_envelope(struct atomisp_sub_device *asd,
unsigned int dvs_w, unsigned int dvs_h);
void atomisp_css_input_set_two_pixels_per_clock(
struct atomisp_sub_device *asd,
bool two_ppc);
void atomisp_css_enable_raw_binning(struct atomisp_sub_device *asd,
bool enable);
void atomisp_css_enable_dz(struct atomisp_sub_device *asd, bool enable);
void atomisp_css_capture_set_mode(struct atomisp_sub_device *asd,
enum atomisp_css_capture_mode mode);
void atomisp_css_input_set_mode(struct atomisp_sub_device *asd,
enum atomisp_css_input_mode mode);
void atomisp_css_capture_enable_online(struct atomisp_sub_device *asd,
unsigned short stream_index, bool enable);
void atomisp_css_preview_enable_online(struct atomisp_sub_device *asd,
unsigned short stream_index, bool enable);
void atomisp_css_video_enable_online(struct atomisp_sub_device *asd,
bool enable);
void atomisp_css_enable_continuous(struct atomisp_sub_device *asd,
bool enable);
void atomisp_css_enable_cvf(struct atomisp_sub_device *asd,
bool enable);
int atomisp_css_input_configure_port(struct atomisp_sub_device *asd,
enum mipi_port_id port,
unsigned int num_lanes,
unsigned int timeout,
unsigned int mipi_freq,
enum atomisp_input_format metadata_format,
unsigned int metadata_width,
unsigned int metadata_height);
int atomisp_css_frame_allocate(struct atomisp_css_frame **frame,
unsigned int width, unsigned int height,
enum atomisp_css_frame_format format,
unsigned int padded_width,
unsigned int raw_bit_depth);
int atomisp_css_frame_allocate_from_info(struct atomisp_css_frame **frame,
const struct atomisp_css_frame_info *info);
void atomisp_css_frame_free(struct atomisp_css_frame *frame);
int atomisp_css_frame_map(struct atomisp_css_frame **frame,
const struct atomisp_css_frame_info *info,
const void __user *data, uint16_t attribute,
void *context);
int atomisp_css_set_black_frame(struct atomisp_sub_device *asd,
const struct atomisp_css_frame *raw_black_frame);
int atomisp_css_allocate_continuous_frames(bool init_time,
struct atomisp_sub_device *asd);
void atomisp_css_update_continuous_frames(struct atomisp_sub_device *asd);
void atomisp_create_pipes_stream(struct atomisp_sub_device *asd);
void atomisp_destroy_pipes_stream_force(struct atomisp_sub_device *asd);
int atomisp_css_stop(struct atomisp_sub_device *asd,
enum atomisp_css_pipe_id pipe_id, bool in_reset);
int atomisp_css_continuous_set_num_raw_frames(
struct atomisp_sub_device *asd,
int num_frames);
void atomisp_css_disable_vf_pp(struct atomisp_sub_device *asd,
bool disable);
int atomisp_css_copy_configure_output(struct atomisp_sub_device *asd,
unsigned int stream_index,
unsigned int width, unsigned int height,
unsigned int padded_width,
enum atomisp_css_frame_format format);
int atomisp_css_yuvpp_configure_output(struct atomisp_sub_device *asd,
unsigned int stream_index,
unsigned int width, unsigned int height,
unsigned int padded_width,
enum atomisp_css_frame_format format);
int atomisp_css_yuvpp_configure_viewfinder(
struct atomisp_sub_device *asd,
unsigned int stream_index,
unsigned int width, unsigned int height,
unsigned int min_width,
enum atomisp_css_frame_format format);
int atomisp_css_yuvpp_get_output_frame_info(
struct atomisp_sub_device *asd,
unsigned int stream_index,
struct atomisp_css_frame_info *info);
int atomisp_css_yuvpp_get_viewfinder_frame_info(
struct atomisp_sub_device *asd,
unsigned int stream_index,
struct atomisp_css_frame_info *info);
int atomisp_css_preview_configure_output(struct atomisp_sub_device *asd,
unsigned int width, unsigned int height,
unsigned int min_width,
enum atomisp_css_frame_format format);
int atomisp_css_capture_configure_output(struct atomisp_sub_device *asd,
unsigned int width, unsigned int height,
unsigned int min_width,
enum atomisp_css_frame_format format);
int atomisp_css_video_configure_output(struct atomisp_sub_device *asd,
unsigned int width, unsigned int height,
unsigned int min_width,
enum atomisp_css_frame_format format);
int atomisp_get_css_frame_info(struct atomisp_sub_device *asd,
uint16_t source_pad,
struct atomisp_css_frame_info *frame_info);
int atomisp_css_video_configure_viewfinder(struct atomisp_sub_device *asd,
unsigned int width, unsigned int height,
unsigned int min_width,
enum atomisp_css_frame_format format);
int atomisp_css_capture_configure_viewfinder(
struct atomisp_sub_device *asd,
unsigned int width, unsigned int height,
unsigned int min_width,
enum atomisp_css_frame_format format);
int atomisp_css_video_get_viewfinder_frame_info(
struct atomisp_sub_device *asd,
struct atomisp_css_frame_info *info);
int atomisp_css_capture_get_viewfinder_frame_info(
struct atomisp_sub_device *asd,
struct atomisp_css_frame_info *info);
int atomisp_css_copy_get_output_frame_info(
struct atomisp_sub_device *asd,
unsigned int stream_index,
struct atomisp_css_frame_info *info);
int atomisp_css_capture_get_output_raw_frame_info(
struct atomisp_sub_device *asd,
struct atomisp_css_frame_info *info);
int atomisp_css_preview_get_output_frame_info(
struct atomisp_sub_device *asd,
struct atomisp_css_frame_info *info);
int atomisp_css_capture_get_output_frame_info(
struct atomisp_sub_device *asd,
struct atomisp_css_frame_info *info);
int atomisp_css_video_get_output_frame_info(
struct atomisp_sub_device *asd,
struct atomisp_css_frame_info *info);
int atomisp_css_preview_configure_pp_input(
struct atomisp_sub_device *asd,
unsigned int width, unsigned int height);
int atomisp_css_capture_configure_pp_input(
struct atomisp_sub_device *asd,
unsigned int width, unsigned int height);
int atomisp_css_video_configure_pp_input(
struct atomisp_sub_device *asd,
unsigned int width, unsigned int height);
int atomisp_css_offline_capture_configure(struct atomisp_sub_device *asd,
int num_captures, unsigned int skip, int offset);
int atomisp_css_exp_id_capture(struct atomisp_sub_device *asd, int exp_id);
int atomisp_css_exp_id_unlock(struct atomisp_sub_device *asd, int exp_id);
int atomisp_css_capture_enable_xnr(struct atomisp_sub_device *asd,
bool enable);
void atomisp_css_send_input_frame(struct atomisp_sub_device *asd,
unsigned short *data, unsigned int width,
unsigned int height);
bool atomisp_css_isp_has_started(void);
void atomisp_css_request_flash(struct atomisp_sub_device *asd);
void atomisp_css_set_wb_config(struct atomisp_sub_device *asd,
struct atomisp_css_wb_config *wb_config);
void atomisp_css_set_ob_config(struct atomisp_sub_device *asd,
struct atomisp_css_ob_config *ob_config);
void atomisp_css_set_dp_config(struct atomisp_sub_device *asd,
struct atomisp_css_dp_config *dp_config);
void atomisp_css_set_de_config(struct atomisp_sub_device *asd,
struct atomisp_css_de_config *de_config);
void atomisp_css_set_dz_config(struct atomisp_sub_device *asd,
struct atomisp_css_dz_config *dz_config);
void atomisp_css_set_default_de_config(struct atomisp_sub_device *asd);
void atomisp_css_set_ce_config(struct atomisp_sub_device *asd,
struct atomisp_css_ce_config *ce_config);
void atomisp_css_set_nr_config(struct atomisp_sub_device *asd,
struct atomisp_css_nr_config *nr_config);
void atomisp_css_set_ee_config(struct atomisp_sub_device *asd,
struct atomisp_css_ee_config *ee_config);
void atomisp_css_set_tnr_config(struct atomisp_sub_device *asd,
struct atomisp_css_tnr_config *tnr_config);
void atomisp_css_set_cc_config(struct atomisp_sub_device *asd,
struct atomisp_css_cc_config *cc_config);
void atomisp_css_set_macc_table(struct atomisp_sub_device *asd,
struct atomisp_css_macc_table *macc_table);
void atomisp_css_set_gamma_table(struct atomisp_sub_device *asd,
struct atomisp_css_gamma_table *gamma_table);
void atomisp_css_set_ctc_table(struct atomisp_sub_device *asd,
struct atomisp_css_ctc_table *ctc_table);
void atomisp_css_set_gc_config(struct atomisp_sub_device *asd,
struct atomisp_css_gc_config *gc_config);
void atomisp_css_set_3a_config(struct atomisp_sub_device *asd,
struct atomisp_css_3a_config *s3a_config);
void atomisp_css_video_set_dis_vector(struct atomisp_sub_device *asd,
struct atomisp_dis_vector *vector);
void atomisp_css_set_dvs2_coefs(struct atomisp_sub_device *asd,
struct ia_css_dvs2_coefficients *coefs);
int atomisp_css_set_dis_coefs(struct atomisp_sub_device *asd,
struct atomisp_dis_coefficients *coefs);
void atomisp_css_set_zoom_factor(struct atomisp_sub_device *asd,
unsigned int zoom);
int atomisp_css_get_wb_config(struct atomisp_sub_device *asd,
struct atomisp_wb_config *config);
int atomisp_css_get_ob_config(struct atomisp_sub_device *asd,
struct atomisp_ob_config *config);
int atomisp_css_get_dp_config(struct atomisp_sub_device *asd,
struct atomisp_dp_config *config);
int atomisp_css_get_de_config(struct atomisp_sub_device *asd,
struct atomisp_de_config *config);
int atomisp_css_get_nr_config(struct atomisp_sub_device *asd,
struct atomisp_nr_config *config);
int atomisp_css_get_ee_config(struct atomisp_sub_device *asd,
struct atomisp_ee_config *config);
int atomisp_css_get_tnr_config(struct atomisp_sub_device *asd,
struct atomisp_tnr_config *config);
int atomisp_css_get_ctc_table(struct atomisp_sub_device *asd,
struct atomisp_ctc_table *config);
int atomisp_css_get_gamma_table(struct atomisp_sub_device *asd,
struct atomisp_gamma_table *config);
int atomisp_css_get_gc_config(struct atomisp_sub_device *asd,
struct atomisp_gc_config *config);
int atomisp_css_get_3a_config(struct atomisp_sub_device *asd,
struct atomisp_3a_config *config);
int atomisp_css_get_formats_config(struct atomisp_sub_device *asd,
struct atomisp_formats_config *formats_config);
void atomisp_css_set_formats_config(struct atomisp_sub_device *asd,
struct atomisp_css_formats_config *formats_config);
int atomisp_css_get_zoom_factor(struct atomisp_sub_device *asd,
unsigned int *zoom);
struct atomisp_css_shading_table *atomisp_css_shading_table_alloc(
unsigned int width, unsigned int height);
void atomisp_css_set_shading_table(struct atomisp_sub_device *asd,
struct atomisp_css_shading_table *table);
void atomisp_css_shading_table_free(struct atomisp_css_shading_table *table);
struct atomisp_css_morph_table *atomisp_css_morph_table_allocate(
unsigned int width, unsigned int height);
void atomisp_css_set_morph_table(struct atomisp_sub_device *asd,
struct atomisp_css_morph_table *table);
void atomisp_css_get_morph_table(struct atomisp_sub_device *asd,
struct atomisp_css_morph_table *table);
void atomisp_css_morph_table_free(struct atomisp_css_morph_table *table);
void atomisp_css_set_cont_prev_start_time(struct atomisp_device *isp,
unsigned int overlap);
int atomisp_css_get_dis_stat(struct atomisp_sub_device *asd,
struct atomisp_dis_statistics *stats);
int atomisp_css_update_stream(struct atomisp_sub_device *asd);
int atomisp_css_create_acc_pipe(struct atomisp_sub_device *asd);
int atomisp_css_start_acc_pipe(struct atomisp_sub_device *asd);
int atomisp_css_stop_acc_pipe(struct atomisp_sub_device *asd);
void atomisp_css_destroy_acc_pipe(struct atomisp_sub_device *asd);
int atomisp_css_load_acc_extension(struct atomisp_sub_device *asd,
struct atomisp_css_fw_info *fw,
enum atomisp_css_pipe_id pipe_id,
unsigned int type);
void atomisp_css_unload_acc_extension(struct atomisp_sub_device *asd,
struct atomisp_css_fw_info *fw,
enum atomisp_css_pipe_id pipe_id);
int atomisp_css_wait_acc_finish(struct atomisp_sub_device *asd);
void atomisp_css_acc_done(struct atomisp_sub_device *asd);
int atomisp_css_load_acc_binary(struct atomisp_sub_device *asd,
struct atomisp_css_fw_info *fw,
unsigned int index);
void atomisp_css_unload_acc_binary(struct atomisp_sub_device *asd);
struct atomisp_acc_fw;
int atomisp_css_set_acc_parameters(struct atomisp_acc_fw *acc_fw);
int atomisp_css_isr_thread(struct atomisp_device *isp,
bool *frame_done_found,
bool *css_pipe_done);
bool atomisp_css_valid_sof(struct atomisp_device *isp);
void atomisp_en_dz_capt_pipe(struct atomisp_sub_device *asd, bool enable);
#endif

4704
drivers/staging/media/atomisp/pci/atomisp2/atomisp_compat_css20.c
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drivers/staging/media/atomisp/pci/atomisp2/atomisp_compat_css20.h
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/*
* Support for Clovertrail PNW Camera Imaging ISP subsystem.
*
* Copyright (c) 2013 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
*/
#ifndef __ATOMISP_COMPAT_CSS20_H__
#define __ATOMISP_COMPAT_CSS20_H__
#include <media/v4l2-mediabus.h>
#include "ia_css.h"
#include "ia_css_types.h"
#include "ia_css_acc_types.h"
#include "sh_css_legacy.h"
#define ATOMISP_CSS2_PIPE_MAX 2
#define ATOMISP_CSS2_NUM_OFFLINE_INIT_CONTINUOUS_FRAMES 3
#define ATOMISP_CSS2_NUM_OFFLINE_INIT_CONTINUOUS_FRAMES_LOCK_EN 4
#define ATOMISP_CSS2_NUM_DVS_FRAME_DELAY 2
#define atomisp_css_pipe_id ia_css_pipe_id
#define atomisp_css_pipeline ia_css_pipe
#define atomisp_css_buffer_type ia_css_buffer_type
#define atomisp_css_dis_data ia_css_isp_dvs_statistics
#define atomisp_css_irq_info ia_css_irq_info
#define atomisp_css_isp_config ia_css_isp_config
#define atomisp_css_bayer_order ia_css_bayer_order
#define atomisp_css_capture_mode ia_css_capture_mode
#define atomisp_css_input_mode ia_css_input_mode
#define atomisp_css_frame ia_css_frame
#define atomisp_css_frame_format ia_css_frame_format
#define atomisp_css_frame_info ia_css_frame_info
#define atomisp_css_dp_config ia_css_dp_config
#define atomisp_css_wb_config ia_css_wb_config
#define atomisp_css_cc_config ia_css_cc_config
#define atomisp_css_nr_config ia_css_nr_config
#define atomisp_css_ee_config ia_css_ee_config
#define atomisp_css_ob_config ia_css_ob_config
#define atomisp_css_de_config ia_css_de_config
#define atomisp_css_dz_config ia_css_dz_config
#define atomisp_css_ce_config ia_css_ce_config
#define atomisp_css_gc_config ia_css_gc_config
#define atomisp_css_tnr_config ia_css_tnr_config
#define atomisp_css_cnr_config ia_css_cnr_config
#define atomisp_css_ctc_config ia_css_ctc_config
#define atomisp_css_3a_config ia_css_3a_config
#define atomisp_css_ecd_config ia_css_ecd_config
#define atomisp_css_ynr_config ia_css_ynr_config
#define atomisp_css_fc_config ia_css_fc_config
#define atomisp_css_aa_config ia_css_aa_config
#define atomisp_css_baa_config ia_css_aa_config
#define atomisp_css_anr_config ia_css_anr_config
#define atomisp_css_xnr_config ia_css_xnr_config
#define atomisp_css_macc_config ia_css_macc_config
#define atomisp_css_gamma_table ia_css_gamma_table
#define atomisp_css_ctc_table ia_css_ctc_table
#define atomisp_css_macc_table ia_css_macc_table
#define atomisp_css_xnr_table ia_css_xnr_table
#define atomisp_css_rgb_gamma_table ia_css_rgb_gamma_table
#define atomisp_css_anr_thres ia_css_anr_thres
#define atomisp_css_dvs_6axis ia_css_dvs_6axis_config
#define atomisp_css_grid_info ia_css_grid_info
#define atomisp_css_3a_grid_info ia_css_3a_grid_info
#define atomisp_css_dvs_grid_info ia_css_dvs_grid_info
#define atomisp_css_shading_table ia_css_shading_table
#define atomisp_css_morph_table ia_css_morph_table
#define atomisp_css_dvs_6axis_config ia_css_dvs_6axis_config
#define atomisp_css_fw_info ia_css_fw_info
#define atomisp_css_formats_config ia_css_formats_config
#define CSS_PIPE_ID_PREVIEW IA_CSS_PIPE_ID_PREVIEW
#define CSS_PIPE_ID_COPY IA_CSS_PIPE_ID_COPY
#define CSS_PIPE_ID_VIDEO IA_CSS_PIPE_ID_VIDEO
#define CSS_PIPE_ID_CAPTURE IA_CSS_PIPE_ID_CAPTURE
#define CSS_PIPE_ID_ACC IA_CSS_PIPE_ID_ACC
#define CSS_PIPE_ID_YUVPP IA_CSS_PIPE_ID_YUVPP
#define CSS_PIPE_ID_NUM IA_CSS_PIPE_ID_NUM
#define CSS_INPUT_MODE_SENSOR IA_CSS_INPUT_MODE_BUFFERED_SENSOR
#define CSS_INPUT_MODE_FIFO IA_CSS_INPUT_MODE_FIFO
#define CSS_INPUT_MODE_TPG IA_CSS_INPUT_MODE_TPG
#define CSS_INPUT_MODE_PRBS IA_CSS_INPUT_MODE_PRBS
#define CSS_INPUT_MODE_MEMORY IA_CSS_INPUT_MODE_MEMORY
#define CSS_IRQ_INFO_CSS_RECEIVER_ERROR IA_CSS_IRQ_INFO_CSS_RECEIVER_ERROR
#define CSS_IRQ_INFO_EVENTS_READY IA_CSS_IRQ_INFO_EVENTS_READY
#define CSS_IRQ_INFO_INPUT_SYSTEM_ERROR \
IA_CSS_IRQ_INFO_INPUT_SYSTEM_ERROR
#define CSS_IRQ_INFO_IF_ERROR IA_CSS_IRQ_INFO_IF_ERROR
#define CSS_BUFFER_TYPE_NUM IA_CSS_BUFFER_TYPE_NUM
#define CSS_FRAME_FLASH_STATE_NONE IA_CSS_FRAME_FLASH_STATE_NONE
#define CSS_FRAME_FLASH_STATE_PARTIAL IA_CSS_FRAME_FLASH_STATE_PARTIAL
#define CSS_FRAME_FLASH_STATE_FULL IA_CSS_FRAME_FLASH_STATE_FULL
#define CSS_BAYER_ORDER_GRBG IA_CSS_BAYER_ORDER_GRBG
#define CSS_BAYER_ORDER_RGGB IA_CSS_BAYER_ORDER_RGGB
#define CSS_BAYER_ORDER_BGGR IA_CSS_BAYER_ORDER_BGGR
#define CSS_BAYER_ORDER_GBRG IA_CSS_BAYER_ORDER_GBRG
/*
* Hide IA_ naming difference in otherwise common CSS macros.
*/
#define CSS_ID(val) (IA_ ## val)
#define CSS_EVENT(val) (IA_CSS_EVENT_TYPE_ ## val)
#define CSS_FORMAT(val) (ATOMISP_INPUT_FORMAT_ ## val)
#define CSS_EVENT_PORT_EOF CSS_EVENT(PORT_EOF)
#define CSS_EVENT_FRAME_TAGGED CSS_EVENT(FRAME_TAGGED)
#define CSS_MIPI_FRAME_BUFFER_SIZE_1 0x60000
#define CSS_MIPI_FRAME_BUFFER_SIZE_2 0x80000
struct atomisp_device;
struct atomisp_sub_device;
#define MAX_STREAMS_PER_CHANNEL 2
/*
* These are used to indicate the css stream state, corresponding
* stream handling can be done via judging the different state.
*/
enum atomisp_css_stream_state {
CSS_STREAM_UNINIT,
CSS_STREAM_CREATED,
CSS_STREAM_STARTED,
CSS_STREAM_STOPPED,
};
/*
* Sensor of external ISP can send multiple steams with different mipi data
* type in the same virtual channel. This information needs to come from the
* sensor or external ISP
*/
struct atomisp_css_isys_config_info {
unsigned int input_format;
unsigned int width;
unsigned int height;
};
struct atomisp_stream_env {
struct ia_css_stream *stream;
struct ia_css_stream_config stream_config;
struct ia_css_stream_info stream_info;
struct ia_css_pipe *pipes[IA_CSS_PIPE_ID_NUM];
struct ia_css_pipe *multi_pipes[IA_CSS_PIPE_ID_NUM];
struct ia_css_pipe_config pipe_configs[IA_CSS_PIPE_ID_NUM];
struct ia_css_pipe_extra_config pipe_extra_configs[IA_CSS_PIPE_ID_NUM];
bool update_pipe[IA_CSS_PIPE_ID_NUM];
enum atomisp_css_stream_state stream_state;
struct ia_css_stream *acc_stream;
enum atomisp_css_stream_state acc_stream_state;
struct ia_css_stream_config acc_stream_config;
unsigned int ch_id; /* virtual channel ID */
unsigned int isys_configs;
struct atomisp_css_isys_config_info isys_info[MAX_STREAMS_PER_CHANNEL];
};
struct atomisp_css_env {
struct ia_css_env isp_css_env;
struct ia_css_fw isp_css_fw;
};
struct atomisp_s3a_buf {
struct ia_css_isp_3a_statistics *s3a_data;
struct ia_css_isp_3a_statistics_map *s3a_map;
struct list_head list;
};
struct atomisp_dis_buf {
struct atomisp_css_dis_data *dis_data;
struct ia_css_isp_dvs_statistics_map *dvs_map;
struct list_head list;
};
struct atomisp_css_buffer {
struct ia_css_buffer css_buffer;
};
struct atomisp_css_event {
enum atomisp_css_pipe_id pipe;
struct ia_css_event event;
};
void atomisp_css_set_macc_config(struct atomisp_sub_device *asd,
struct atomisp_css_macc_config *macc_config);
void atomisp_css_set_ecd_config(struct atomisp_sub_device *asd,
struct atomisp_css_ecd_config *ecd_config);
void atomisp_css_set_ynr_config(struct atomisp_sub_device *asd,
struct atomisp_css_ynr_config *ynr_config);
void atomisp_css_set_fc_config(struct atomisp_sub_device *asd,
struct atomisp_css_fc_config *fc_config);
void atomisp_css_set_aa_config(struct atomisp_sub_device *asd,
struct atomisp_css_aa_config *aa_config);
void atomisp_css_set_baa_config(struct atomisp_sub_device *asd,
struct atomisp_css_baa_config *baa_config);
void atomisp_css_set_anr_config(struct atomisp_sub_device *asd,
struct atomisp_css_anr_config *anr_config);
void atomisp_css_set_xnr_config(struct atomisp_sub_device *asd,
struct atomisp_css_xnr_config *xnr_config);
void atomisp_css_set_cnr_config(struct atomisp_sub_device *asd,
struct atomisp_css_cnr_config *cnr_config);
void atomisp_css_set_ctc_config(struct atomisp_sub_device *asd,
struct atomisp_css_ctc_config *ctc_config);
void atomisp_css_set_yuv2rgb_cc_config(struct atomisp_sub_device *asd,
struct atomisp_css_cc_config *yuv2rgb_cc_config);
void atomisp_css_set_rgb2yuv_cc_config(struct atomisp_sub_device *asd,
struct atomisp_css_cc_config *rgb2yuv_cc_config);
void atomisp_css_set_xnr_table(struct atomisp_sub_device *asd,
struct atomisp_css_xnr_table *xnr_table);
void atomisp_css_set_r_gamma_table(struct atomisp_sub_device *asd,
struct atomisp_css_rgb_gamma_table *r_gamma_table);
void atomisp_css_set_g_gamma_table(struct atomisp_sub_device *asd,
struct atomisp_css_rgb_gamma_table *g_gamma_table);
void atomisp_css_set_b_gamma_table(struct atomisp_sub_device *asd,
struct atomisp_css_rgb_gamma_table *b_gamma_table);
void atomisp_css_set_anr_thres(struct atomisp_sub_device *asd,
struct atomisp_css_anr_thres *anr_thres);
int atomisp_css_check_firmware_version(struct atomisp_device *isp);
int atomisp_css_load_firmware(struct atomisp_device *isp);
void atomisp_css_unload_firmware(struct atomisp_device *isp);
void atomisp_css_set_dvs_6axis(struct atomisp_sub_device *asd,
struct atomisp_css_dvs_6axis *dvs_6axis);
unsigned int atomisp_css_debug_get_dtrace_level(void);
int atomisp_css_debug_dump_isp_binary(void);
int atomisp_css_dump_sp_raw_copy_linecount(bool reduced);
int atomisp_css_dump_blob_infor(void);
void atomisp_css_set_isp_config_id(struct atomisp_sub_device *asd,
uint32_t isp_config_id);
void atomisp_css_set_isp_config_applied_frame(struct atomisp_sub_device *asd,
struct atomisp_css_frame *output_frame);
int atomisp_get_css_dbgfunc(void);
int atomisp_set_css_dbgfunc(struct atomisp_device *isp, int opt);
struct atomisp_css_dvs_grid_info *atomisp_css_get_dvs_grid_info(
struct atomisp_css_grid_info *grid_info);
#endif

1225
drivers/staging/media/atomisp/pci/atomisp2/atomisp_compat_ioctl32.c
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drivers/staging/media/atomisp/pci/atomisp2/atomisp_compat_ioctl32.h
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/*
* Support for Intel Camera Imaging ISP subsystem.
*
* Copyright (c) 2013 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
*/
#ifndef __ATOMISP_COMPAT_IOCTL32_H__
#define __ATOMISP_COMPAT_IOCTL32_H__
#include <linux/compat.h>
#include <linux/videodev2.h>
#include "atomisp_compat.h"
struct atomisp_histogram32 {
unsigned int num_elements;
compat_uptr_t data;
};
struct atomisp_dvs2_stat_types32 {
compat_uptr_t odd_real; /** real part of the odd statistics*/
compat_uptr_t odd_imag; /** imaginary part of the odd statistics*/
compat_uptr_t even_real;/** real part of the even statistics*/
compat_uptr_t even_imag;/** imaginary part of the even statistics*/
};
struct atomisp_dvs2_coef_types32 {
compat_uptr_t odd_real; /** real part of the odd coefficients*/
compat_uptr_t odd_imag; /** imaginary part of the odd coefficients*/
compat_uptr_t even_real;/** real part of the even coefficients*/
compat_uptr_t even_imag;/** imaginary part of the even coefficients*/
};
struct atomisp_dvs2_statistics32 {
struct atomisp_dvs_grid_info grid_info;
struct atomisp_dvs2_stat_types32 hor_prod;
struct atomisp_dvs2_stat_types32 ver_prod;
};
struct atomisp_dis_statistics32 {
struct atomisp_dvs2_statistics32 dvs2_stat;
uint32_t exp_id;
};
struct atomisp_dis_coefficients32 {
struct atomisp_dvs_grid_info grid_info;
struct atomisp_dvs2_coef_types32 hor_coefs;
struct atomisp_dvs2_coef_types32 ver_coefs;
};
struct atomisp_3a_statistics32 {
struct atomisp_grid_info grid_info;
compat_uptr_t data;
compat_uptr_t rgby_data;
uint32_t exp_id;
uint32_t isp_config_id;
};
struct atomisp_metadata_with_type32 {
/* to specify which type of metadata to get */
enum atomisp_metadata_type type;
compat_uptr_t data;
uint32_t width;
uint32_t height;
uint32_t stride; /* in bytes */
uint32_t exp_id; /* exposure ID */
compat_uptr_t effective_width;
};
struct atomisp_metadata32 {
compat_uptr_t data;
uint32_t width;
uint32_t height;
uint32_t stride;
uint32_t exp_id;
compat_uptr_t effective_width;
};
struct atomisp_morph_table32 {
unsigned int enabled;
unsigned int height;
unsigned int width; /* number of valid elements per line */
compat_uptr_t coordinates_x[ATOMISP_MORPH_TABLE_NUM_PLANES];
compat_uptr_t coordinates_y[ATOMISP_MORPH_TABLE_NUM_PLANES];
};
struct v4l2_framebuffer32 {
__u32 capability;
__u32 flags;
compat_uptr_t base;
struct v4l2_pix_format fmt;
};
struct atomisp_overlay32 {
/* the frame containing the overlay data The overlay frame width should
* be the multiples of 2*ISP_VEC_NELEMS. The overlay frame height
* should be the multiples of 2.
*/
compat_uptr_t frame;
/* Y value of overlay background */
unsigned char bg_y;
/* U value of overlay background */
char bg_u;
/* V value of overlay background */
char bg_v;
/* the blending percent of input data for Y subpixels */
unsigned char blend_input_perc_y;
/* the blending percent of input data for U subpixels */
unsigned char blend_input_perc_u;
/* the blending percent of input data for V subpixels */
unsigned char blend_input_perc_v;
/* the blending percent of overlay data for Y subpixels */
unsigned char blend_overlay_perc_y;
/* the blending percent of overlay data for U subpixels */
unsigned char blend_overlay_perc_u;
/* the blending percent of overlay data for V subpixels */
unsigned char blend_overlay_perc_v;
/* the overlay start x pixel position on output frame It should be the
multiples of 2*ISP_VEC_NELEMS. */
unsigned int overlay_start_x;
/* the overlay start y pixel position on output frame It should be the
multiples of 2. */
unsigned int overlay_start_y;
};
struct atomisp_calibration_group32 {
unsigned int size;
unsigned int type;
compat_uptr_t calb_grp_values;
};
struct atomisp_acc_fw_load32 {
unsigned int size;
unsigned int fw_handle;
compat_uptr_t data;
};
struct atomisp_acc_fw_arg32 {
unsigned int fw_handle;
unsigned int index;
compat_uptr_t value;
compat_size_t size;
};
struct v4l2_private_int_data32 {
__u32 size;
compat_uptr_t data;
__u32 reserved[2];
};
struct atomisp_shading_table32 {
__u32 enable;
__u32 sensor_width;
__u32 sensor_height;
__u32 width;
__u32 height;
__u32 fraction_bits;
compat_uptr_t data[ATOMISP_NUM_SC_COLORS];
};
struct atomisp_acc_map32 {
__u32 flags; /* Flags, see list below */
__u32 length; /* Length of data in bytes */
compat_uptr_t user_ptr; /* Pointer into user space */
compat_ulong_t css_ptr; /* Pointer into CSS address space */
__u32 reserved[4]; /* Set to zero */
};
struct atomisp_acc_s_mapped_arg32 {
unsigned int fw_handle;
__u32 memory; /* one of enum atomisp_acc_memory */
compat_size_t length;
compat_ulong_t css_ptr;
};
struct atomisp_parameters32 {
compat_uptr_t wb_config; /* White Balance config */
compat_uptr_t cc_config; /* Color Correction config */
compat_uptr_t tnr_config; /* Temporal Noise Reduction */
compat_uptr_t ecd_config; /* Eigen Color Demosaicing */
compat_uptr_t ynr_config; /* Y(Luma) Noise Reduction */
compat_uptr_t fc_config; /* Fringe Control */
compat_uptr_t formats_config; /* Formats Control */
compat_uptr_t cnr_config; /* Chroma Noise Reduction */
compat_uptr_t macc_config; /* MACC */
compat_uptr_t ctc_config; /* Chroma Tone Control */
compat_uptr_t aa_config; /* Anti-Aliasing */
compat_uptr_t baa_config; /* Anti-Aliasing */
compat_uptr_t ce_config;
compat_uptr_t dvs_6axis_config;
compat_uptr_t ob_config; /* Objective Black config */
compat_uptr_t dp_config; /* Dead Pixel config */
compat_uptr_t nr_config; /* Noise Reduction config */
compat_uptr_t ee_config; /* Edge Enhancement config */
compat_uptr_t de_config; /* Demosaic config */
compat_uptr_t gc_config; /* Gamma Correction config */
compat_uptr_t anr_config; /* Advanced Noise Reduction */
compat_uptr_t a3a_config; /* 3A Statistics config */
compat_uptr_t xnr_config; /* eXtra Noise Reduction */
compat_uptr_t dz_config; /* Digital Zoom */
compat_uptr_t yuv2rgb_cc_config; /* Color
Correction config */
compat_uptr_t rgb2yuv_cc_config; /* Color
Correction config */
compat_uptr_t macc_table;
compat_uptr_t gamma_table;
compat_uptr_t ctc_table;
compat_uptr_t xnr_table;
compat_uptr_t r_gamma_table;
compat_uptr_t g_gamma_table;
compat_uptr_t b_gamma_table;
compat_uptr_t motion_vector; /* For 2-axis DVS */
compat_uptr_t shading_table;
compat_uptr_t morph_table;
compat_uptr_t dvs_coefs; /* DVS 1.0 coefficients */
compat_uptr_t dvs2_coefs; /* DVS 2.0 coefficients */
compat_uptr_t capture_config;
compat_uptr_t anr_thres;
compat_uptr_t lin_2500_config; /* Skylake: Linearization config */
compat_uptr_t obgrid_2500_config; /* Skylake: OBGRID config */
compat_uptr_t bnr_2500_config; /* Skylake: bayer denoise config */
compat_uptr_t shd_2500_config; /* Skylake: shading config */
compat_uptr_t dm_2500_config; /* Skylake: demosaic config */
compat_uptr_t rgbpp_2500_config; /* Skylake: RGBPP config */
compat_uptr_t dvs_stat_2500_config; /* Skylake: DVS STAT config */
compat_uptr_t lace_stat_2500_config; /* Skylake: LACE STAT config */
compat_uptr_t yuvp1_2500_config; /* Skylake: yuvp1 config */
compat_uptr_t yuvp2_2500_config; /* Skylake: yuvp2 config */
compat_uptr_t tnr_2500_config; /* Skylake: TNR config */
compat_uptr_t dpc_2500_config; /* Skylake: DPC config */
compat_uptr_t awb_2500_config; /* Skylake: auto white balance config */
compat_uptr_t awb_fr_2500_config; /* Skylake: auto white balance filter response config */
compat_uptr_t anr_2500_config; /* Skylake: ANR config */
compat_uptr_t af_2500_config; /* Skylake: auto focus config */
compat_uptr_t ae_2500_config; /* Skylake: auto exposure config */
compat_uptr_t bds_2500_config; /* Skylake: bayer downscaler config */
compat_uptr_t dvs_2500_config; /* Skylake: digital video stabilization config */
compat_uptr_t res_mgr_2500_config;
/*
* Output frame pointer the config is to be applied to (optional),
* set to NULL to make this config is applied as global.
*/
compat_uptr_t output_frame;
/*
* Unique ID to track which config was actually applied to a particular
* frame, driver will send this id back with output frame together.
*/
uint32_t isp_config_id;
uint32_t per_frame_setting;
};
struct atomisp_acc_fw_load_to_pipe32 {
__u32 flags; /* Flags, see below for valid values */
unsigned int fw_handle; /* Handle, filled by kernel. */
__u32 size; /* Firmware binary size */
compat_uptr_t data; /* Pointer to firmware */
__u32 type; /* Binary type */
__u32 reserved[3]; /* Set to zero */
};
struct atomisp_dvs_6axis_config32 {
uint32_t exp_id;
uint32_t width_y;
uint32_t height_y;
uint32_t width_uv;
uint32_t height_uv;
compat_uptr_t xcoords_y;
compat_uptr_t ycoords_y;
compat_uptr_t xcoords_uv;
compat_uptr_t ycoords_uv;
};
struct atomisp_sensor_ae_bracketing_lut32 {
compat_uptr_t lut;
unsigned int lut_size;
};
#define ATOMISP_IOC_G_HISTOGRAM32 \
_IOWR('v', BASE_VIDIOC_PRIVATE + 3, struct atomisp_histogram32)
#define ATOMISP_IOC_S_HISTOGRAM32 \
_IOW('v', BASE_VIDIOC_PRIVATE + 3, struct atomisp_histogram32)
#define ATOMISP_IOC_G_DIS_STAT32 \
_IOWR('v', BASE_VIDIOC_PRIVATE + 6, struct atomisp_dis_statistics32)
#define ATOMISP_IOC_S_DIS_COEFS32 \
_IOW('v', BASE_VIDIOC_PRIVATE + 6, struct atomisp_dis_coefficients32)
#define ATOMISP_IOC_S_DIS_VECTOR32 \
_IOW('v', BASE_VIDIOC_PRIVATE + 6, struct atomisp_dvs_6axis_config32)
#define ATOMISP_IOC_G_3A_STAT32 \
_IOWR('v', BASE_VIDIOC_PRIVATE + 7, struct atomisp_3a_statistics32)
#define ATOMISP_IOC_G_ISP_GDC_TAB32 \
_IOR('v', BASE_VIDIOC_PRIVATE + 10, struct atomisp_morph_table32)
#define ATOMISP_IOC_S_ISP_GDC_TAB32 \
_IOW('v', BASE_VIDIOC_PRIVATE + 10, struct atomisp_morph_table32)
#define ATOMISP_IOC_S_ISP_FPN_TABLE32 \
_IOW('v', BASE_VIDIOC_PRIVATE + 17, struct v4l2_framebuffer32)
#define ATOMISP_IOC_G_ISP_OVERLAY32 \
_IOWR('v', BASE_VIDIOC_PRIVATE + 18, struct atomisp_overlay32)
#define ATOMISP_IOC_S_ISP_OVERLAY32 \
_IOW('v', BASE_VIDIOC_PRIVATE + 18, struct atomisp_overlay32)
#define ATOMISP_IOC_G_SENSOR_CALIBRATION_GROUP32 \
_IOWR('v', BASE_VIDIOC_PRIVATE + 22, struct atomisp_calibration_group32)
#define ATOMISP_IOC_ACC_LOAD32 \
_IOWR('v', BASE_VIDIOC_PRIVATE + 24, struct atomisp_acc_fw_load32)
#define ATOMISP_IOC_ACC_S_ARG32 \
_IOW('v', BASE_VIDIOC_PRIVATE + 24, struct atomisp_acc_fw_arg32)
#define ATOMISP_IOC_ACC_DESTAB32 \
_IOW('v', BASE_VIDIOC_PRIVATE + 25, struct atomisp_acc_fw_arg32)
#define ATOMISP_IOC_G_SENSOR_PRIV_INT_DATA32 \
_IOWR('v', BASE_VIDIOC_PRIVATE + 26, struct v4l2_private_int_data32)
#define ATOMISP_IOC_S_ISP_SHD_TAB32 \
_IOWR('v', BASE_VIDIOC_PRIVATE + 27, struct atomisp_shading_table32)
#define ATOMISP_IOC_G_MOTOR_PRIV_INT_DATA32 \
_IOWR('v', BASE_VIDIOC_PRIVATE + 29, struct v4l2_private_int_data32)
#define ATOMISP_IOC_ACC_MAP32 \
_IOWR('v', BASE_VIDIOC_PRIVATE + 30, struct atomisp_acc_map32)
#define ATOMISP_IOC_ACC_UNMAP32 \
_IOW('v', BASE_VIDIOC_PRIVATE + 30, struct atomisp_acc_map32)
#define ATOMISP_IOC_ACC_S_MAPPED_ARG32 \
_IOW('v', BASE_VIDIOC_PRIVATE + 30, struct atomisp_acc_s_mapped_arg32)
#define ATOMISP_IOC_ACC_LOAD_TO_PIPE32 \
_IOWR('v', BASE_VIDIOC_PRIVATE + 31, struct atomisp_acc_fw_load_to_pipe32)
#define ATOMISP_IOC_S_PARAMETERS32 \
_IOW('v', BASE_VIDIOC_PRIVATE + 32, struct atomisp_parameters32)
#define ATOMISP_IOC_G_METADATA32 \
_IOWR('v', BASE_VIDIOC_PRIVATE + 34, struct atomisp_metadata32)
#define ATOMISP_IOC_G_METADATA_BY_TYPE32 \
_IOWR('v', BASE_VIDIOC_PRIVATE + 34, struct atomisp_metadata_with_type32)
#define ATOMISP_IOC_S_SENSOR_AE_BRACKETING_LUT32 \
_IOW('v', BASE_VIDIOC_PRIVATE + 43, struct atomisp_sensor_ae_bracketing_lut32)
#endif /* __ATOMISP_COMPAT_IOCTL32_H__ */

442
drivers/staging/media/atomisp/pci/atomisp2/atomisp_csi2.c
View File

@ -1,442 +0,0 @@
/*
* Support for Medifield PNW Camera Imaging ISP subsystem.
*
* Copyright (c) 2010 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
*/
#include <media/v4l2-event.h>
#include <media/v4l2-mediabus.h>
#include "atomisp_cmd.h"
#include "atomisp_internal.h"
#include "atomisp-regs.h"
static struct v4l2_mbus_framefmt *__csi2_get_format(struct
atomisp_mipi_csi2_device
*csi2,
struct
v4l2_subdev_pad_config *cfg,
enum
v4l2_subdev_format_whence
which, unsigned int pad)
{
if (which == V4L2_SUBDEV_FORMAT_TRY)
return v4l2_subdev_get_try_format(&csi2->subdev, cfg, pad);
else
return &csi2->formats[pad];
}
/*
* csi2_enum_mbus_code - Handle pixel format enumeration
* @sd : pointer to v4l2 subdev structure
* @fh : V4L2 subdev file handle
* @code : pointer to v4l2_subdev_pad_mbus_code_enum structure
* return -EINVAL or zero on success
*/
static int csi2_enum_mbus_code(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_mbus_code_enum *code)
{
const struct atomisp_in_fmt_conv *ic = atomisp_in_fmt_conv;
unsigned int i = 0;
while (ic->code) {
if (i == code->index) {
code->code = ic->code;
return 0;
}
i++, ic++;
}
return -EINVAL;
}
/*
* csi2_get_format - Handle get format by pads subdev method
* @sd : pointer to v4l2 subdev structure
* @fh : V4L2 subdev file handle
* @pad: pad num
* @fmt: pointer to v4l2 format structure
* return -EINVAL or zero on sucess
*/
static int csi2_get_format(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_format *fmt)
{
struct atomisp_mipi_csi2_device *csi2 = v4l2_get_subdevdata(sd);
struct v4l2_mbus_framefmt *format;
format = __csi2_get_format(csi2, cfg, fmt->which, fmt->pad);
fmt->format = *format;
return 0;
}
int atomisp_csi2_set_ffmt(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
unsigned int which, uint16_t pad,
struct v4l2_mbus_framefmt *ffmt)
{
struct atomisp_mipi_csi2_device *csi2 = v4l2_get_subdevdata(sd);
struct v4l2_mbus_framefmt *actual_ffmt =
#ifndef ISP2401
__csi2_get_format(csi2, cfg, which, pad);
#else
__csi2_get_format(csi2, cfg, which, pad);
#endif
if (pad == CSI2_PAD_SINK) {
const struct atomisp_in_fmt_conv *ic;
struct v4l2_mbus_framefmt tmp_ffmt;
ic = atomisp_find_in_fmt_conv(ffmt->code);
if (ic)
actual_ffmt->code = ic->code;
else
actual_ffmt->code = atomisp_in_fmt_conv[0].code;
actual_ffmt->width = clamp_t(
u32, ffmt->width, ATOM_ISP_MIN_WIDTH,
ATOM_ISP_MAX_WIDTH);
actual_ffmt->height = clamp_t(
u32, ffmt->height, ATOM_ISP_MIN_HEIGHT,
ATOM_ISP_MAX_HEIGHT);
tmp_ffmt = *ffmt = *actual_ffmt;
return atomisp_csi2_set_ffmt(sd, cfg, which, CSI2_PAD_SOURCE,
&tmp_ffmt);
}
/* FIXME: DPCM decompression */
*actual_ffmt = *ffmt =
#ifndef ISP2401
*__csi2_get_format(csi2, cfg, which, CSI2_PAD_SINK);
#else
*__csi2_get_format(csi2, cfg, which, CSI2_PAD_SINK);
#endif
return 0;
}
/*
* csi2_set_format - Handle set format by pads subdev method
* @sd : pointer to v4l2 subdev structure
* @fh : V4L2 subdev file handle
* @pad: pad num
* @fmt: pointer to v4l2 format structure
* return -EINVAL or zero on success
*/
static int csi2_set_format(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_format *fmt)
{
return atomisp_csi2_set_ffmt(sd, cfg, fmt->which, fmt->pad,
&fmt->format);
}
/*
* csi2_set_stream - Enable/Disable streaming on the CSI2 module
* @sd: ISP CSI2 V4L2 subdevice
* @enable: Enable/disable stream (1/0)
*
* Return 0 on success or a negative error code otherwise.
*/
static int csi2_set_stream(struct v4l2_subdev *sd, int enable)
{
return 0;
}
/* subdev core operations */
static const struct v4l2_subdev_core_ops csi2_core_ops = {
};
/* subdev video operations */
static const struct v4l2_subdev_video_ops csi2_video_ops = {
.s_stream = csi2_set_stream,
};
/* subdev pad operations */
static const struct v4l2_subdev_pad_ops csi2_pad_ops = {
.enum_mbus_code = csi2_enum_mbus_code,
.get_fmt = csi2_get_format,
.set_fmt = csi2_set_format,
.link_validate = v4l2_subdev_link_validate_default,
};
/* subdev operations */
static const struct v4l2_subdev_ops csi2_ops = {
.core = &csi2_core_ops,
.video = &csi2_video_ops,
.pad = &csi2_pad_ops,
};
#ifndef ISP2401
#endif
/*
* csi2_link_setup - Setup CSI2 connections.
* @entity : Pointer to media entity structure
* @local : Pointer to local pad array
* @remote : Pointer to remote pad array
* @flags : Link flags
* return -EINVAL or zero on success
*/
static int csi2_link_setup(struct media_entity *entity,
const struct media_pad *local,
const struct media_pad *remote, u32 flags)
{
struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
struct atomisp_mipi_csi2_device *csi2 = v4l2_get_subdevdata(sd);
u32 result = local->index | is_media_entity_v4l2_subdev(remote->entity);
switch (result) {
case CSI2_PAD_SOURCE | MEDIA_ENT_F_OLD_BASE:
/* not supported yet */
return -EINVAL;
case CSI2_PAD_SOURCE | MEDIA_ENT_F_V4L2_SUBDEV_UNKNOWN:
if (flags & MEDIA_LNK_FL_ENABLED) {
if (csi2->output & ~CSI2_OUTPUT_ISP_SUBDEV)
return -EBUSY;
csi2->output |= CSI2_OUTPUT_ISP_SUBDEV;
} else {
csi2->output &= ~CSI2_OUTPUT_ISP_SUBDEV;
}
break;
default:
/* Link from camera to CSI2 is fixed... */
return -EINVAL;
}
return 0;
}
/* media operations */
static const struct media_entity_operations csi2_media_ops = {
.link_setup = csi2_link_setup,
.link_validate = v4l2_subdev_link_validate,
};
/*
* ispcsi2_init_entities - Initialize subdev and media entity.
* @csi2: Pointer to ispcsi2 structure.
* return -ENOMEM or zero on success
*/
static int mipi_csi2_init_entities(struct atomisp_mipi_csi2_device *csi2,
int port)
{
struct v4l2_subdev *sd = &csi2->subdev;
struct media_pad *pads = csi2->pads;
struct media_entity *me = &sd->entity;
int ret;
v4l2_subdev_init(sd, &csi2_ops);
snprintf(sd->name, sizeof(sd->name), "ATOM ISP CSI2-port%d", port);
v4l2_set_subdevdata(sd, csi2);
sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
pads[CSI2_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
pads[CSI2_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
me->ops = &csi2_media_ops;
me->function = MEDIA_ENT_F_V4L2_SUBDEV_UNKNOWN;
ret = media_entity_pads_init(me, CSI2_PADS_NUM, pads);
if (ret < 0)
return ret;
csi2->formats[CSI2_PAD_SINK].code =
csi2->formats[CSI2_PAD_SOURCE].code =
atomisp_in_fmt_conv[0].code;
return 0;
}
void
atomisp_mipi_csi2_unregister_entities(struct atomisp_mipi_csi2_device *csi2)
{
media_entity_cleanup(&csi2->subdev.entity);
v4l2_device_unregister_subdev(&csi2->subdev);
}
int atomisp_mipi_csi2_register_entities(struct atomisp_mipi_csi2_device *csi2,
struct v4l2_device *vdev)
{
int ret;
/* Register the subdev and video nodes. */
ret = v4l2_device_register_subdev(vdev, &csi2->subdev);
if (ret < 0)
goto error;
return 0;
error:
atomisp_mipi_csi2_unregister_entities(csi2);
return ret;
}
static const int LIMIT_SHIFT = 6; /* Limit numeric range into 31 bits */
static int
atomisp_csi2_configure_calc(const short int coeffs[2], int mipi_freq, int def)
{
/* Delay counter accuracy, 1/0.0625 for ANN/CHT, 1/0.125 for BXT */
static const int accinv = 16; /* 1 / COUNT_ACC */
int r;
if (mipi_freq >> LIMIT_SHIFT <= 0)
return def;
r = accinv * coeffs[1] * (500000000 >> LIMIT_SHIFT);
r /= mipi_freq >> LIMIT_SHIFT;
r += accinv * coeffs[0];
return r;
}
static void atomisp_csi2_configure_isp2401(struct atomisp_sub_device *asd)
{
/*
* The ISP2401 new input system CSI2+ receiver has several
* parameters affecting the receiver timings. These depend
* on the MIPI bus frequency F in Hz (sensor transmitter rate)
* as follows:
* register value = (A/1e9 + B * UI) / COUNT_ACC
* where
* UI = 1 / (2 * F) in seconds
* COUNT_ACC = counter accuracy in seconds
* For ANN and CHV, COUNT_ACC = 0.0625 ns
* For BXT, COUNT_ACC = 0.125 ns
* A and B are coefficients from the table below,
* depending whether the register minimum or maximum value is
* calculated.
* Minimum Maximum
* Clock lane A B A B
* reg_rx_csi_dly_cnt_termen_clane 0 0 38 0
* reg_rx_csi_dly_cnt_settle_clane 95 -8 300 -16
* Data lanes
* reg_rx_csi_dly_cnt_termen_dlane0 0 0 35 4
* reg_rx_csi_dly_cnt_settle_dlane0 85 -2 145 -6
* reg_rx_csi_dly_cnt_termen_dlane1 0 0 35 4
* reg_rx_csi_dly_cnt_settle_dlane1 85 -2 145 -6
* reg_rx_csi_dly_cnt_termen_dlane2 0 0 35 4
* reg_rx_csi_dly_cnt_settle_dlane2 85 -2 145 -6
* reg_rx_csi_dly_cnt_termen_dlane3 0 0 35 4
* reg_rx_csi_dly_cnt_settle_dlane3 85 -2 145 -6
*
* We use the minimum values in the calculations below.
*/
static const short int coeff_clk_termen[] = { 0, 0 };
static const short int coeff_clk_settle[] = { 95, -8 };
static const short int coeff_dat_termen[] = { 0, 0 };
static const short int coeff_dat_settle[] = { 85, -2 };
static const int TERMEN_DEFAULT = 0 * 0;
static const int SETTLE_DEFAULT = 0x480;
static const hrt_address csi2_port_base[] = {
[ATOMISP_CAMERA_PORT_PRIMARY] = CSI2_PORT_A_BASE,
[ATOMISP_CAMERA_PORT_SECONDARY] = CSI2_PORT_B_BASE,
[ATOMISP_CAMERA_PORT_TERTIARY] = CSI2_PORT_C_BASE,
};
/* Number of lanes on each port, excluding clock lane */
static const unsigned char csi2_port_lanes[] = {
[ATOMISP_CAMERA_PORT_PRIMARY] = 4,
[ATOMISP_CAMERA_PORT_SECONDARY] = 2,
[ATOMISP_CAMERA_PORT_TERTIARY] = 2,
};
static const hrt_address csi2_lane_base[] = {
CSI2_LANE_CL_BASE,
CSI2_LANE_D0_BASE,
CSI2_LANE_D1_BASE,
CSI2_LANE_D2_BASE,
CSI2_LANE_D3_BASE,
};
int clk_termen;
int clk_settle;
int dat_termen;
int dat_settle;
struct v4l2_control ctrl;
struct atomisp_device *isp = asd->isp;
struct camera_mipi_info *mipi_info;
int mipi_freq = 0;
enum atomisp_camera_port port;
int n;
mipi_info = atomisp_to_sensor_mipi_info(
isp->inputs[asd->input_curr].camera);
port = mipi_info->port;
ctrl.id = V4L2_CID_LINK_FREQ;
if (v4l2_g_ctrl
(isp->inputs[asd->input_curr].camera->ctrl_handler, &ctrl) == 0)
mipi_freq = ctrl.value;
clk_termen = atomisp_csi2_configure_calc(coeff_clk_termen,
mipi_freq, TERMEN_DEFAULT);
clk_settle = atomisp_csi2_configure_calc(coeff_clk_settle,
mipi_freq, SETTLE_DEFAULT);
dat_termen = atomisp_csi2_configure_calc(coeff_dat_termen,
mipi_freq, TERMEN_DEFAULT);
dat_settle = atomisp_csi2_configure_calc(coeff_dat_settle,
mipi_freq, SETTLE_DEFAULT);
for (n = 0; n < csi2_port_lanes[port] + 1; n++) {
hrt_address base = csi2_port_base[port] + csi2_lane_base[n];
atomisp_store_uint32(base + CSI2_REG_RX_CSI_DLY_CNT_TERMEN,
n == 0 ? clk_termen : dat_termen);
atomisp_store_uint32(base + CSI2_REG_RX_CSI_DLY_CNT_SETTLE,
n == 0 ? clk_settle : dat_settle);
}
}
void atomisp_csi2_configure(struct atomisp_sub_device *asd)
{
if (IS_HWREVISION(asd->isp, ATOMISP_HW_REVISION_ISP2401))
atomisp_csi2_configure_isp2401(asd);
}
/*
* atomisp_mipi_csi2_cleanup - Routine for module driver cleanup
*/
void atomisp_mipi_csi2_cleanup(struct atomisp_device *isp)
{
}
#ifndef ISP2401
#endif
int atomisp_mipi_csi2_init(struct atomisp_device *isp)
{
struct atomisp_mipi_csi2_device *csi2_port;
unsigned int i;
int ret;
for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) {
csi2_port = &isp->csi2_port[i];
csi2_port->isp = isp;
ret = mipi_csi2_init_entities(csi2_port, i);
if (ret < 0)
goto fail;
}
return 0;
fail:
atomisp_mipi_csi2_cleanup(isp);
return ret;
}

57
drivers/staging/media/atomisp/pci/atomisp2/atomisp_csi2.h
View File

@ -1,57 +0,0 @@
/*
* Support for Medifield PNW Camera Imaging ISP subsystem.
*
* Copyright (c) 2010 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
*/
#ifndef __ATOMISP_CSI2_H__
#define __ATOMISP_CSI2_H__
#include <media/v4l2-subdev.h>
#include <media/v4l2-ctrls.h>
#define CSI2_PAD_SINK 0
#define CSI2_PAD_SOURCE 1
#define CSI2_PADS_NUM 2
#define CSI2_OUTPUT_ISP_SUBDEV (1 << 0)
#define CSI2_OUTPUT_MEMORY (1 << 1)
struct atomisp_device;
struct v4l2_device;
struct atomisp_sub_device;
struct atomisp_mipi_csi2_device {
struct v4l2_subdev subdev;
struct media_pad pads[CSI2_PADS_NUM];
struct v4l2_mbus_framefmt formats[CSI2_PADS_NUM];
struct v4l2_ctrl_handler ctrls;
struct atomisp_device *isp;
u32 output; /* output direction */
};
int atomisp_csi2_set_ffmt(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg,
unsigned int which, uint16_t pad,
struct v4l2_mbus_framefmt *ffmt);
int atomisp_mipi_csi2_init(struct atomisp_device *isp);
void atomisp_mipi_csi2_cleanup(struct atomisp_device *isp);
void atomisp_mipi_csi2_unregister_entities(
struct atomisp_mipi_csi2_device *csi2);
int atomisp_mipi_csi2_register_entities(struct atomisp_mipi_csi2_device *csi2,
struct v4l2_device *vdev);
void atomisp_csi2_configure(struct atomisp_sub_device *asd);
#endif /* __ATOMISP_CSI2_H__ */

408
drivers/staging/media/atomisp/pci/atomisp2/atomisp_dfs_tables.h
View File

@ -1,408 +0,0 @@
/*
* Support for Intel Camera Imaging ISP subsystem.
*
* Copyright (c) 2013 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
*/
#ifndef __ATOMISP_DFS_TABLES_H__
#define __ATOMISP_DFS_TABLES_H__
#include <linux/kernel.h>
struct atomisp_freq_scaling_rule {
unsigned int width;
unsigned int height;
unsigned short fps;
unsigned int isp_freq;
unsigned int run_mode;
};
struct atomisp_dfs_config {
unsigned int lowest_freq;
unsigned int max_freq_at_vmin;
unsigned int highest_freq;
const struct atomisp_freq_scaling_rule *dfs_table;
unsigned int dfs_table_size;
};
static const struct atomisp_freq_scaling_rule dfs_rules_merr[] = {
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_400MHZ,
.run_mode = ATOMISP_RUN_MODE_VIDEO,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_400MHZ,
.run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_400MHZ,
.run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_400MHZ,
.run_mode = ATOMISP_RUN_MODE_PREVIEW,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_457MHZ,
.run_mode = ATOMISP_RUN_MODE_SDV,
},
};
/* Merrifield and Moorefield DFS rules */
static const struct atomisp_dfs_config dfs_config_merr = {
.lowest_freq = ISP_FREQ_200MHZ,
.max_freq_at_vmin = ISP_FREQ_400MHZ,
.highest_freq = ISP_FREQ_457MHZ,
.dfs_table = dfs_rules_merr,
.dfs_table_size = ARRAY_SIZE(dfs_rules_merr),
};
static const struct atomisp_freq_scaling_rule dfs_rules_merr_1179[] = {
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_400MHZ,
.run_mode = ATOMISP_RUN_MODE_VIDEO,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_400MHZ,
.run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_400MHZ,
.run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_400MHZ,
.run_mode = ATOMISP_RUN_MODE_PREVIEW,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_400MHZ,
.run_mode = ATOMISP_RUN_MODE_SDV,
},
};
static const struct atomisp_dfs_config dfs_config_merr_1179 = {
.lowest_freq = ISP_FREQ_200MHZ,
.max_freq_at_vmin = ISP_FREQ_400MHZ,
.highest_freq = ISP_FREQ_400MHZ,
.dfs_table = dfs_rules_merr_1179,
.dfs_table_size = ARRAY_SIZE(dfs_rules_merr_1179),
};
static const struct atomisp_freq_scaling_rule dfs_rules_merr_117a[] = {
{
.width = 1920,
.height = 1080,
.fps = 30,
.isp_freq = ISP_FREQ_266MHZ,
.run_mode = ATOMISP_RUN_MODE_VIDEO,
},
{
.width = 1080,
.height = 1920,
.fps = 30,
#ifndef ISP2401
.isp_freq = ISP_FREQ_266MHZ,
#else
.isp_freq = ISP_FREQ_400MHZ,
#endif
.run_mode = ATOMISP_RUN_MODE_VIDEO,
},
{
.width = 1920,
.height = 1080,
.fps = 45,
.isp_freq = ISP_FREQ_320MHZ,
.run_mode = ATOMISP_RUN_MODE_VIDEO,
},
{
.width = 1080,
.height = 1920,
.fps = 45,
.isp_freq = ISP_FREQ_320MHZ,
.run_mode = ATOMISP_RUN_MODE_VIDEO,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = 60,
.isp_freq = ISP_FREQ_356MHZ,
.run_mode = ATOMISP_RUN_MODE_VIDEO,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_200MHZ,
.run_mode = ATOMISP_RUN_MODE_VIDEO,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_400MHZ,
.run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_400MHZ,
.run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_200MHZ,
.run_mode = ATOMISP_RUN_MODE_PREVIEW,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_400MHZ,
.run_mode = ATOMISP_RUN_MODE_SDV,
},
};
static const struct atomisp_dfs_config dfs_config_merr_117a = {
.lowest_freq = ISP_FREQ_200MHZ,
.max_freq_at_vmin = ISP_FREQ_200MHZ,
.highest_freq = ISP_FREQ_400MHZ,
.dfs_table = dfs_rules_merr_117a,
.dfs_table_size = ARRAY_SIZE(dfs_rules_merr_117a),
};
static const struct atomisp_freq_scaling_rule dfs_rules_byt[] = {
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_400MHZ,
.run_mode = ATOMISP_RUN_MODE_VIDEO,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_400MHZ,
.run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_400MHZ,
.run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_400MHZ,
.run_mode = ATOMISP_RUN_MODE_PREVIEW,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_400MHZ,
.run_mode = ATOMISP_RUN_MODE_SDV,
},
};
static const struct atomisp_dfs_config dfs_config_byt = {
.lowest_freq = ISP_FREQ_200MHZ,
.max_freq_at_vmin = ISP_FREQ_400MHZ,
.highest_freq = ISP_FREQ_400MHZ,
.dfs_table = dfs_rules_byt,
.dfs_table_size = ARRAY_SIZE(dfs_rules_byt),
};
static const struct atomisp_freq_scaling_rule dfs_rules_byt_cr[] = {
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_320MHZ,
.run_mode = ATOMISP_RUN_MODE_VIDEO,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_320MHZ,
.run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_320MHZ,
.run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_320MHZ,
.run_mode = ATOMISP_RUN_MODE_PREVIEW,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_320MHZ,
.run_mode = ATOMISP_RUN_MODE_SDV,
},
};
static const struct atomisp_dfs_config dfs_config_byt_cr = {
.lowest_freq = ISP_FREQ_200MHZ,
.max_freq_at_vmin = ISP_FREQ_320MHZ,
.highest_freq = ISP_FREQ_320MHZ,
.dfs_table = dfs_rules_byt_cr,
.dfs_table_size = ARRAY_SIZE(dfs_rules_byt_cr),
};
static const struct atomisp_freq_scaling_rule dfs_rules_cht[] = {
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_320MHZ,
.run_mode = ATOMISP_RUN_MODE_VIDEO,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_356MHZ,
.run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_320MHZ,
.run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_320MHZ,
.run_mode = ATOMISP_RUN_MODE_PREVIEW,
},
{
.width = 1280,
.height = 720,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_320MHZ,
.run_mode = ATOMISP_RUN_MODE_SDV,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_356MHZ,
.run_mode = ATOMISP_RUN_MODE_SDV,
},
};
static const struct atomisp_freq_scaling_rule dfs_rules_cht_soc[] = {
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_356MHZ,
.run_mode = ATOMISP_RUN_MODE_VIDEO,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_356MHZ,
.run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_320MHZ,
.run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_320MHZ,
.run_mode = ATOMISP_RUN_MODE_PREVIEW,
},
{
.width = ISP_FREQ_RULE_ANY,
.height = ISP_FREQ_RULE_ANY,
.fps = ISP_FREQ_RULE_ANY,
.isp_freq = ISP_FREQ_356MHZ,
.run_mode = ATOMISP_RUN_MODE_SDV,
},
};
static const struct atomisp_dfs_config dfs_config_cht = {
.lowest_freq = ISP_FREQ_100MHZ,
.max_freq_at_vmin = ISP_FREQ_356MHZ,
.highest_freq = ISP_FREQ_356MHZ,
.dfs_table = dfs_rules_cht,
.dfs_table_size = ARRAY_SIZE(dfs_rules_cht),
};
static const struct atomisp_dfs_config dfs_config_cht_soc = {
.lowest_freq = ISP_FREQ_100MHZ,
.max_freq_at_vmin = ISP_FREQ_356MHZ,
.highest_freq = ISP_FREQ_356MHZ,
.dfs_table = dfs_rules_cht_soc,
.dfs_table_size = ARRAY_SIZE(dfs_rules_cht_soc),
};
#endif /* __ATOMISP_DFS_TABLES_H__ */

205
drivers/staging/media/atomisp/pci/atomisp2/atomisp_drvfs.c
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@ -1,205 +0,0 @@
/*
* Support for atomisp driver sysfs interface
*
* Copyright (c) 2014 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
*/
#include <linux/device.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include "atomisp_compat.h"
#include "atomisp_internal.h"
#include "atomisp_ioctl.h"
#include "atomisp_drvfs.h"
#include "hmm/hmm.h"
/*
* _iunit_debug:
* dbglvl: iunit css driver trace level
* dbgopt: iunit debug option:
* bit 0: binary list
* bit 1: running binary
* bit 2: memory statistic
*/
struct _iunit_debug {
struct device_driver *drv;
struct atomisp_device *isp;
unsigned int dbglvl;
unsigned int dbgfun;
unsigned int dbgopt;
};
#define OPTION_BIN_LIST (1<<0)
#define OPTION_BIN_RUN (1<<1)
#define OPTION_MEM_STAT (1<<2)
#define OPTION_VALID (OPTION_BIN_LIST \
| OPTION_BIN_RUN \
| OPTION_MEM_STAT)
static struct _iunit_debug iunit_debug = {
.dbglvl = 0,
.dbgopt = OPTION_BIN_LIST,
};
static inline int iunit_dump_dbgopt(struct atomisp_device *isp,
unsigned int opt)
{
int ret = 0;
if (opt & OPTION_VALID) {
if (opt & OPTION_BIN_LIST) {
ret = atomisp_css_dump_blob_infor();
if (ret) {
dev_err(atomisp_dev, "%s dump blob infor err[ret:%d]\n",
__func__, ret);
goto opt_err;
}
}
if (opt & OPTION_BIN_RUN) {
if (atomisp_streaming_count(isp)) {
atomisp_css_dump_sp_raw_copy_linecount(true);
atomisp_css_debug_dump_isp_binary();
} else {
ret = -EPERM;
dev_err(atomisp_dev, "%s dump running bin err[ret:%d]\n",
__func__, ret);
goto opt_err;
}
}
if (opt & OPTION_MEM_STAT)
hmm_show_mem_stat(__func__, __LINE__);
} else {
ret = -EINVAL;
dev_err(atomisp_dev, "%s dump nothing[ret=%d]\n", __func__,
ret);
}
opt_err:
return ret;
}
static ssize_t iunit_dbglvl_show(struct device_driver *drv, char *buf)
{
iunit_debug.dbglvl = atomisp_css_debug_get_dtrace_level();
return sprintf(buf, "dtrace level:%u\n", iunit_debug.dbglvl);
}
static ssize_t iunit_dbglvl_store(struct device_driver *drv, const char *buf,
size_t size)
{
if (kstrtouint(buf, 10, &iunit_debug.dbglvl)
|| iunit_debug.dbglvl < 1
|| iunit_debug.dbglvl > 9) {
return -ERANGE;
}
atomisp_css_debug_set_dtrace_level(iunit_debug.dbglvl);
return size;
}
static ssize_t iunit_dbgfun_show(struct device_driver *drv, char *buf)
{
iunit_debug.dbgfun = atomisp_get_css_dbgfunc();
return sprintf(buf, "dbgfun opt:%u\n", iunit_debug.dbgfun);
}
static ssize_t iunit_dbgfun_store(struct device_driver *drv, const char *buf,
size_t size)
{
unsigned int opt;
int ret;
ret = kstrtouint(buf, 10, &opt);
if (ret)
return ret;
ret = atomisp_set_css_dbgfunc(iunit_debug.isp, opt);
if (ret)
return ret;
iunit_debug.dbgfun = opt;
return size;
}
static ssize_t iunit_dbgopt_show(struct device_driver *drv, char *buf)
{
return sprintf(buf, "option:0x%x\n", iunit_debug.dbgopt);
}
static ssize_t iunit_dbgopt_store(struct device_driver *drv, const char *buf,
size_t size)
{
unsigned int opt;
int ret;
ret = kstrtouint(buf, 10, &opt);
if (ret)
return ret;
iunit_debug.dbgopt = opt;
ret = iunit_dump_dbgopt(iunit_debug.isp, iunit_debug.dbgopt);
if (ret)
return ret;
return size;
}
static const struct driver_attribute iunit_drvfs_attrs[] = {
__ATTR(dbglvl, 0644, iunit_dbglvl_show, iunit_dbglvl_store),
__ATTR(dbgfun, 0644, iunit_dbgfun_show, iunit_dbgfun_store),
__ATTR(dbgopt, 0644, iunit_dbgopt_show, iunit_dbgopt_store),
};
static int iunit_drvfs_create_files(struct device_driver *drv)
{
int i, ret = 0;
for (i = 0; i < ARRAY_SIZE(iunit_drvfs_attrs); i++)
ret |= driver_create_file(drv, &iunit_drvfs_attrs[i]);
return ret;
}
static void iunit_drvfs_remove_files(struct device_driver *drv)
{
int i;
for (i = 0; i < ARRAY_SIZE(iunit_drvfs_attrs); i++)
driver_remove_file(drv, &iunit_drvfs_attrs[i]);
}
int atomisp_drvfs_init(struct device_driver *drv, struct atomisp_device *isp)
{
int ret;
iunit_debug.isp = isp;
iunit_debug.drv = drv;
ret = iunit_drvfs_create_files(iunit_debug.drv);
if (ret) {
dev_err(atomisp_dev, "drvfs_create_files error: %d\n", ret);
iunit_drvfs_remove_files(iunit_debug.drv);
}
return ret;
}
void atomisp_drvfs_exit(void)
{
iunit_drvfs_remove_files(iunit_debug.drv);
}

24
drivers/staging/media/atomisp/pci/atomisp2/atomisp_drvfs.h
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@ -1,24 +0,0 @@
/*
* Support for atomisp driver sysfs interface.
*
* Copyright (c) 2014 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
*/
#ifndef __ATOMISP_DRVFS_H__
#define __ATOMISP_DRVFS_H__
int atomisp_drvfs_init(struct device_driver *drv, struct atomisp_device *isp);
void atomisp_drvfs_exit(void);
#endif /* __ATOMISP_DRVFS_H__ */

225
drivers/staging/media/atomisp/pci/atomisp2/atomisp_file.c
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@ -1,225 +0,0 @@
/*
* Support for Medifield PNW Camera Imaging ISP subsystem.
*
* Copyright (c) 2010 Intel Corporation. All Rights Reserved.
*
* Copyright (c) 2010 Silicon Hive www.siliconhive.com.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
*/
#include <media/v4l2-event.h>
#include <media/v4l2-mediabus.h>
#include <media/videobuf-vmalloc.h>
#include <linux/delay.h>
#include "ia_css.h"
#include "atomisp_cmd.h"
#include "atomisp_common.h"
#include "atomisp_file.h"
#include "atomisp_internal.h"
#include "atomisp_ioctl.h"
static void file_work(struct work_struct *work)
{
struct atomisp_file_device *file_dev =
container_of(work, struct atomisp_file_device, work);
struct atomisp_device *isp = file_dev->isp;
/* only support file injection on subdev0 */
struct atomisp_sub_device *asd = &isp->asd[0];
struct atomisp_video_pipe *out_pipe = &asd->video_in;
unsigned short *buf = videobuf_to_vmalloc(out_pipe->outq.bufs[0]);
struct v4l2_mbus_framefmt isp_sink_fmt;
if (asd->streaming != ATOMISP_DEVICE_STREAMING_ENABLED)
return;
dev_dbg(isp->dev, ">%s: ready to start streaming\n", __func__);
isp_sink_fmt = *atomisp_subdev_get_ffmt(&asd->subdev, NULL,
V4L2_SUBDEV_FORMAT_ACTIVE,
ATOMISP_SUBDEV_PAD_SINK);
while (!atomisp_css_isp_has_started())
usleep_range(1000, 1500);
atomisp_css_send_input_frame(asd, buf, isp_sink_fmt.width,
isp_sink_fmt.height);
dev_dbg(isp->dev, "<%s: streaming done\n", __func__);
}
static int file_input_s_stream(struct v4l2_subdev *sd, int enable)
{
struct atomisp_file_device *file_dev = v4l2_get_subdevdata(sd);
struct atomisp_device *isp = file_dev->isp;
/* only support file injection on subdev0 */
struct atomisp_sub_device *asd = &isp->asd[0];
dev_dbg(isp->dev, "%s: enable %d\n", __func__, enable);
if (enable) {
if (asd->streaming != ATOMISP_DEVICE_STREAMING_ENABLED)
return 0;
queue_work(file_dev->work_queue, &file_dev->work);
return 0;
}
cancel_work_sync(&file_dev->work);
return 0;
}
static int file_input_get_fmt(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_format *format)
{
struct v4l2_mbus_framefmt *fmt = &format->format;
struct atomisp_file_device *file_dev = v4l2_get_subdevdata(sd);
struct atomisp_device *isp = file_dev->isp;
/* only support file injection on subdev0 */
struct atomisp_sub_device *asd = &isp->asd[0];
struct v4l2_mbus_framefmt *isp_sink_fmt;
if (format->pad)
return -EINVAL;
isp_sink_fmt = atomisp_subdev_get_ffmt(&asd->subdev, NULL,
V4L2_SUBDEV_FORMAT_ACTIVE,
ATOMISP_SUBDEV_PAD_SINK);
fmt->width = isp_sink_fmt->width;
fmt->height = isp_sink_fmt->height;
fmt->code = isp_sink_fmt->code;
return 0;
}
static int file_input_set_fmt(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_format *format)
{
struct v4l2_mbus_framefmt *fmt = &format->format;
if (format->pad)
return -EINVAL;
file_input_get_fmt(sd, cfg, format);
if (format->which == V4L2_SUBDEV_FORMAT_TRY)
cfg->try_fmt = *fmt;
return 0;
}
static int file_input_log_status(struct v4l2_subdev *sd)
{
/*to fake*/
return 0;
}
static int file_input_s_power(struct v4l2_subdev *sd, int on)
{
/* to fake */
return 0;
}
static int file_input_enum_mbus_code(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_mbus_code_enum *code)
{
/*to fake*/
return 0;
}
static int file_input_enum_frame_size(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_frame_size_enum *fse)
{
/*to fake*/
return 0;
}
static int file_input_enum_frame_ival(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_frame_interval_enum
*fie)
{
/*to fake*/
return 0;
}
static const struct v4l2_subdev_video_ops file_input_video_ops = {
.s_stream = file_input_s_stream,
};
static const struct v4l2_subdev_core_ops file_input_core_ops = {
.log_status = file_input_log_status,
.s_power = file_input_s_power,
};
static const struct v4l2_subdev_pad_ops file_input_pad_ops = {
.enum_mbus_code = file_input_enum_mbus_code,
.enum_frame_size = file_input_enum_frame_size,
.enum_frame_interval = file_input_enum_frame_ival,
.get_fmt = file_input_get_fmt,
.set_fmt = file_input_set_fmt,
};
static const struct v4l2_subdev_ops file_input_ops = {
.core = &file_input_core_ops,
.video = &file_input_video_ops,
.pad = &file_input_pad_ops,
};
void
atomisp_file_input_unregister_entities(struct atomisp_file_device *file_dev)
{
media_entity_cleanup(&file_dev->sd.entity);
v4l2_device_unregister_subdev(&file_dev->sd);
}
int atomisp_file_input_register_entities(struct atomisp_file_device *file_dev,
struct v4l2_device *vdev)
{
/* Register the subdev and video nodes. */
return v4l2_device_register_subdev(vdev, &file_dev->sd);
}
void atomisp_file_input_cleanup(struct atomisp_device *isp)
{
struct atomisp_file_device *file_dev = &isp->file_dev;
if (file_dev->work_queue) {
destroy_workqueue(file_dev->work_queue);
file_dev->work_queue = NULL;
}
}
int atomisp_file_input_init(struct atomisp_device *isp)
{
struct atomisp_file_device *file_dev = &isp->file_dev;
struct v4l2_subdev *sd = &file_dev->sd;
struct media_pad *pads = file_dev->pads;
struct media_entity *me = &sd->entity;
file_dev->isp = isp;
file_dev->work_queue = alloc_workqueue(isp->v4l2_dev.name, 0, 1);
if (file_dev->work_queue == NULL) {
dev_err(isp->dev, "Failed to initialize file inject workq\n");
return -ENOMEM;
}
INIT_WORK(&file_dev->work, file_work);
v4l2_subdev_init(sd, &file_input_ops);
sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
strcpy(sd->name, "file_input_subdev");
v4l2_set_subdevdata(sd, file_dev);
pads[0].flags = MEDIA_PAD_FL_SINK;
me->function = MEDIA_ENT_F_V4L2_SUBDEV_UNKNOWN;
return media_entity_pads_init(me, 1, pads);
}

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drivers/staging/media/atomisp/pci/atomisp2/atomisp_file.h
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/*
* Support for Medifield PNW Camera Imaging ISP subsystem.
*
* Copyright (c) 2010 Intel Corporation. All Rights Reserved.
*
* Copyright (c) 2010 Silicon Hive www.siliconhive.com.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
*/
#ifndef __ATOMISP_FILE_H__
#define __ATOMISP_FILE_H__
#include <media/media-entity.h>
#include <media/v4l2-subdev.h>
struct atomisp_device;
struct atomisp_file_device {
struct v4l2_subdev sd;
struct atomisp_device *isp;
struct media_pad pads[1];
struct workqueue_struct *work_queue;
struct work_struct work;
};
void atomisp_file_input_cleanup(struct atomisp_device *isp);
int atomisp_file_input_init(struct atomisp_device *isp);
void atomisp_file_input_unregister_entities(
struct atomisp_file_device *file_dev);
int atomisp_file_input_register_entities(struct atomisp_file_device *file_dev,
struct v4l2_device *vdev);
#endif /* __ATOMISP_FILE_H__ */

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drivers/staging/media/atomisp/pci/atomisp2/atomisp_fops.c
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drivers/staging/media/atomisp/pci/atomisp2/atomisp_fops.h
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/*
* Support for Medifield PNW Camera Imaging ISP subsystem.
*
* Copyright (c) 2010 Intel Corporation. All Rights Reserved.
*
* Copyright (c) 2010 Silicon Hive www.siliconhive.com.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
*/
#ifndef __ATOMISP_FOPS_H__
#define __ATOMISP_FOPS_H__
#include "atomisp_subdev.h"
int atomisp_q_video_buffers_to_css(struct atomisp_sub_device *asd,
struct atomisp_video_pipe *pipe,
enum atomisp_input_stream_id stream_id,
enum atomisp_css_buffer_type css_buf_type,
enum atomisp_css_pipe_id css_pipe_id);
unsigned int atomisp_dev_users(struct atomisp_device *isp);
unsigned int atomisp_sub_dev_users(struct atomisp_sub_device *asd);
/*
* Memory help functions for image frame and private parameters
*/
int atomisp_videobuf_mmap_mapper(struct videobuf_queue *q,
struct vm_area_struct *vma);
int atomisp_qbuf_to_css(struct atomisp_device *isp,
struct atomisp_video_pipe *pipe,
struct videobuf_buffer *vb);
int atomisp_qbuffers_to_css(struct atomisp_sub_device *asd);
extern const struct v4l2_file_operations atomisp_fops;
extern bool defer_fw_load;
#endif /* __ATOMISP_FOPS_H__ */

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drivers/staging/media/atomisp/pci/atomisp2/atomisp_helper.h
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/*
* Support for Medifield PNW Camera Imaging ISP subsystem.
*
* Copyright (c) 2010 Intel Corporation. All Rights Reserved.
*
* Copyright (c) 2010 Silicon Hive www.siliconhive.com.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
*/
#ifndef _atomisp_helper_h_
#define _atomisp_helper_h_
extern void __iomem *atomisp_io_base;
static inline void __iomem *atomisp_get_io_virt_addr(unsigned int address)
{
void __iomem *ret = atomisp_io_base + (address & 0x003FFFFF);
return ret;
}
#endif

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drivers/staging/media/atomisp/pci/atomisp2/atomisp_internal.h
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/*
* Support for Medifield PNW Camera Imaging ISP subsystem.
*
* Copyright (c) 2010 Intel Corporation. All Rights Reserved.
*
* Copyright (c) 2010 Silicon Hive www.siliconhive.com.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
*/
#ifndef __ATOMISP_INTERNAL_H__
#define __ATOMISP_INTERNAL_H__
#include "../../include/linux/atomisp_platform.h"
#include <linux/firmware.h>
#include <linux/kernel.h>
#include <linux/pm_qos.h>
#include <linux/idr.h>
#include <media/media-device.h>
#include <media/v4l2-subdev.h>
#ifndef ISP2401
#include "ia_css_types.h"
#include "sh_css_legacy.h"
#else
/*#include "ia_css_types.h"*/
/*#include "sh_css_legacy.h"*/
#endif
#include "atomisp_csi2.h"
#include "atomisp_file.h"
#include "atomisp_subdev.h"
#include "atomisp_tpg.h"
#include "atomisp_compat.h"
#include "gp_device.h"
#include "irq.h"
#include <linux/vmalloc.h>
#define V4L2_EVENT_FRAME_END 5
#define IS_HWREVISION(isp, rev) \
(((isp)->media_dev.hw_revision & ATOMISP_HW_REVISION_MASK) == \
((rev) << ATOMISP_HW_REVISION_SHIFT))
#define MAX_STREAM_NUM 2
#define ATOMISP_PCI_DEVICE_SOC_MASK 0xfff8
/* MRFLD with 0x1178: ISP freq can burst to 457MHz */
#define ATOMISP_PCI_DEVICE_SOC_MRFLD 0x1178
/* MRFLD with 0x1179: max ISP freq limited to 400MHz */
#define ATOMISP_PCI_DEVICE_SOC_MRFLD_1179 0x1179
/* MRFLD with 0x117a: max ISP freq is 400MHz and max freq at Vmin is 200MHz */
#define ATOMISP_PCI_DEVICE_SOC_MRFLD_117A 0x117a
#define ATOMISP_PCI_DEVICE_SOC_BYT 0x0f38
#define ATOMISP_PCI_DEVICE_SOC_ANN 0x1478
#define ATOMISP_PCI_DEVICE_SOC_CHT 0x22b8
#define ATOMISP_PCI_REV_MRFLD_A0_MAX 0
#define ATOMISP_PCI_REV_BYT_A0_MAX 4
#define ATOM_ISP_STEP_WIDTH 2
#define ATOM_ISP_STEP_HEIGHT 2
#define ATOM_ISP_MIN_WIDTH 4
#define ATOM_ISP_MIN_HEIGHT 4
#define ATOM_ISP_MAX_WIDTH UINT_MAX
#define ATOM_ISP_MAX_HEIGHT UINT_MAX
/* sub-QCIF resolution */
#define ATOM_RESOLUTION_SUBQCIF_WIDTH 128
#define ATOM_RESOLUTION_SUBQCIF_HEIGHT 96
#define ATOM_ISP_MAX_WIDTH_TMP 1280
#define ATOM_ISP_MAX_HEIGHT_TMP 720
#define ATOM_ISP_I2C_BUS_1 4
#define ATOM_ISP_I2C_BUS_2 5
#define ATOM_ISP_POWER_DOWN 0
#define ATOM_ISP_POWER_UP 1
#define ATOM_ISP_MAX_INPUTS 4
#define ATOMISP_SC_TYPE_SIZE 2
#define ATOMISP_ISP_TIMEOUT_DURATION (2 * HZ)
#define ATOMISP_EXT_ISP_TIMEOUT_DURATION (6 * HZ)
#define ATOMISP_ISP_FILE_TIMEOUT_DURATION (60 * HZ)
#define ATOMISP_WDT_KEEP_CURRENT_DELAY 0
#define ATOMISP_ISP_MAX_TIMEOUT_COUNT 2
#define ATOMISP_CSS_STOP_TIMEOUT_US 200000
#define ATOMISP_CSS_Q_DEPTH 3
#define ATOMISP_CSS_EVENTS_MAX 16
#define ATOMISP_CONT_RAW_FRAMES 15
#define ATOMISP_METADATA_QUEUE_DEPTH_FOR_HAL 8
#define ATOMISP_S3A_BUF_QUEUE_DEPTH_FOR_HAL 8
#define ATOMISP_DELAYED_INIT_NOT_QUEUED 0
#define ATOMISP_DELAYED_INIT_QUEUED 1
#define ATOMISP_DELAYED_INIT_DONE 2
#define ATOMISP_CALC_CSS_PREV_OVERLAP(lines) \
((lines) * 38 / 100 & 0xfffffe)
/*
* Define how fast CPU should be able to serve ISP interrupts.
* The bigger the value, the higher risk that the ISP is not
* triggered sufficiently fast for it to process image during
* vertical blanking time, increasing risk of dropped frames.
* 1000 us is a reasonable value considering that the processing
* time is typically ~2000 us.
*/
#define ATOMISP_MAX_ISR_LATENCY 1000
/* Add new YUVPP pipe for SOC sensor. */
#define ATOMISP_CSS_SUPPORT_YUVPP 1
#define ATOMISP_CSS_OUTPUT_SECOND_INDEX 1
#define ATOMISP_CSS_OUTPUT_DEFAULT_INDEX 0
/*
* ATOMISP_SOC_CAMERA
* This is to differentiate between ext-isp and soc camera in
* Moorefield/Baytrail platform.
*/
#define ATOMISP_SOC_CAMERA(asd) \
(asd->isp->inputs[asd->input_curr].type == SOC_CAMERA \
&& asd->isp->inputs[asd->input_curr].camera_caps-> \
sensor[asd->sensor_curr].stream_num == 1)
#define ATOMISP_USE_YUVPP(asd) \
(ATOMISP_SOC_CAMERA(asd) && ATOMISP_CSS_SUPPORT_YUVPP && \
!asd->copy_mode)
#define ATOMISP_DEPTH_SENSOR_STREAMON_COUNT 2
#define ATOMISP_DEPTH_DEFAULT_MASTER_SENSOR 0
#define ATOMISP_DEPTH_DEFAULT_SLAVE_SENSOR 1
#ifdef ISP2401
#define ATOMISP_ION_DEVICE_FD_OFFSET 16
#define ATOMISP_ION_SHARED_FD_MASK (0xFFFF)
#define ATOMISP_ION_DEVICE_FD_MASK (~ATOMISP_ION_SHARED_FD_MASK)
#define ION_FD_UNSET (-1)
#endif
#define DIV_NEAREST_STEP(n, d, step) \
round_down((2 * (n) + (d) * (step))/(2 * (d)), (step))
struct atomisp_input_subdev {
unsigned int type;
enum atomisp_camera_port port;
struct v4l2_subdev *camera;
struct v4l2_subdev *motor;
struct v4l2_frmsizeenum frame_size;
/*
* To show this resource is used by
* which stream, in ISP multiple stream mode
*/
struct atomisp_sub_device *asd;
const struct atomisp_camera_caps *camera_caps;
int sensor_index;
};
enum atomisp_dfs_mode {
ATOMISP_DFS_MODE_AUTO = 0,
ATOMISP_DFS_MODE_LOW,
ATOMISP_DFS_MODE_MAX,
};
struct atomisp_regs {
/* PCI config space info */
u16 pcicmdsts;
u32 ispmmadr;
u32 msicap;
u32 msi_addr;
u16 msi_data;
u8 intr;
u32 interrupt_control;
u32 pmcs;
u32 cg_dis;
u32 i_control;
/* I-Unit PHY related info */
u32 csi_rcomp_config;
u32 csi_afe_dly;
u32 csi_control;
/* New for MRFLD */
u32 csi_afe_rcomp_config;
u32 csi_afe_hs_control;
u32 csi_deadline_control;
u32 csi_access_viol;
};
struct atomisp_sw_contex {
bool file_input;
int power_state;
int running_freq;
};
#define ATOMISP_DEVICE_STREAMING_DISABLED 0
#define ATOMISP_DEVICE_STREAMING_ENABLED 1
#define ATOMISP_DEVICE_STREAMING_STOPPING 2
/*
* ci device struct
*/
struct atomisp_device {
struct pci_dev *pdev;
struct device *dev;
struct v4l2_device v4l2_dev;
struct media_device media_dev;
struct atomisp_platform_data *pdata;
void *mmu_l1_base;
const struct firmware *firmware;
struct pm_qos_request pm_qos;
s32 max_isr_latency;
/*
* ISP modules
* Multiple streams are represents by multiple
* atomisp_sub_device instances
*/
struct atomisp_sub_device *asd;
/*
* this will be assiged dyanamically.
* For Merr/BTY(ISP2400), 2 streams are supported.
*/
unsigned int num_of_streams;
struct atomisp_mipi_csi2_device csi2_port[ATOMISP_CAMERA_NR_PORTS];
struct atomisp_tpg_device tpg;
struct atomisp_file_device file_dev;
/* Purpose of mutex is to protect and serialize use of isp data
* structures and css API calls. */
struct rt_mutex mutex;
/*
* Serialise streamoff: mutex is dropped during streamoff to
* cancel the watchdog queue. MUST be acquired BEFORE
* "mutex".
*/
struct mutex streamoff_mutex;
unsigned int input_cnt;
struct atomisp_input_subdev inputs[ATOM_ISP_MAX_INPUTS];
struct v4l2_subdev *flash;
struct v4l2_subdev *motor;
struct atomisp_regs saved_regs;
struct atomisp_sw_contex sw_contex;
struct atomisp_css_env css_env;
/* isp timeout status flag */
bool isp_timeout;
bool isp_fatal_error;
struct workqueue_struct *wdt_work_queue;
struct work_struct wdt_work;
#ifndef ISP2401
atomic_t wdt_count;
#endif
atomic_t wdt_work_queued;
spinlock_t lock; /* Just for streaming below */
bool need_gfx_throttle;
unsigned int mipi_frame_size;
const struct atomisp_dfs_config *dfs;
unsigned int hpll_freq;
bool css_initialized;
};
#define v4l2_dev_to_atomisp_device(dev) \
container_of(dev, struct atomisp_device, v4l2_dev)
extern struct device *atomisp_dev;
#define atomisp_is_wdt_running(a) timer_pending(&(a)->wdt)
#ifdef ISP2401
extern void atomisp_wdt_refresh_pipe(struct atomisp_video_pipe *pipe,
unsigned int delay);
#endif
extern void atomisp_wdt_refresh(struct atomisp_sub_device *asd, unsigned int delay);
#ifndef ISP2401
extern void atomisp_wdt_start(struct atomisp_sub_device *asd);
#else
extern void atomisp_wdt_start(struct atomisp_video_pipe *pipe);
extern void atomisp_wdt_stop_pipe(struct atomisp_video_pipe *pipe, bool sync);
#endif
extern void atomisp_wdt_stop(struct atomisp_sub_device *asd, bool sync);
#endif /* __ATOMISP_INTERNAL_H__ */

3123
drivers/staging/media/atomisp/pci/atomisp2/atomisp_ioctl.c
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drivers/staging/media/atomisp/pci/atomisp2/atomisp_ioctl.h
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/*
* Support for Medifield PNW Camera Imaging ISP subsystem.
*
* Copyright (c) 2010 Intel Corporation. All Rights Reserved.
*
* Copyright (c) 2010 Silicon Hive www.siliconhive.com.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
*/
#ifndef __ATOMISP_IOCTL_H__
#define __ATOMISP_IOCTL_H__
#include "ia_css.h"
struct atomisp_device;
struct atomisp_video_pipe;
extern const struct atomisp_format_bridge atomisp_output_fmts[];
const struct atomisp_format_bridge *atomisp_get_format_bridge(
unsigned int pixelformat);
#ifndef ISP2401
const struct atomisp_format_bridge *atomisp_get_format_bridge_from_mbus(
u32 mbus_code);
#else
const struct atomisp_format_bridge *atomisp_get_format_bridge_from_mbus(u32
mbus_code);
#endif
int atomisp_alloc_css_stat_bufs(struct atomisp_sub_device *asd,
uint16_t stream_id);
int __atomisp_streamoff(struct file *file, void *fh, enum v4l2_buf_type type);
int __atomisp_reqbufs(struct file *file, void *fh,
struct v4l2_requestbuffers *req);
int atomisp_reqbufs(struct file *file, void *fh,
struct v4l2_requestbuffers *req);
enum atomisp_css_pipe_id atomisp_get_css_pipe_id(struct atomisp_sub_device
*asd);
void atomisp_videobuf_free_buf(struct videobuf_buffer *vb);
extern const struct v4l2_file_operations atomisp_file_fops;
extern const struct v4l2_ioctl_ops atomisp_ioctl_ops;
extern const struct v4l2_ioctl_ops atomisp_file_ioctl_ops;
unsigned int atomisp_streaming_count(struct atomisp_device *isp);
unsigned int atomisp_is_acc_enabled(struct atomisp_device *isp);
/* compat_ioctl for 32bit userland app and 64bit kernel */
long atomisp_compat_ioctl32(struct file *file,
unsigned int cmd, unsigned long arg);
int atomisp_stream_on_master_slave_sensor(struct atomisp_device *isp, bool isp_timeout);
#endif /* __ATOMISP_IOCTL_H__ */

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drivers/staging/media/atomisp/pci/atomisp2/atomisp_subdev.c
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drivers/staging/media/atomisp/pci/atomisp2/atomisp_subdev.h
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/*
* Support for Medifield PNW Camera Imaging ISP subsystem.
*
* Copyright (c) 2010 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
*/
#ifndef __ATOMISP_SUBDEV_H__
#define __ATOMISP_SUBDEV_H__
#include <media/v4l2-ctrls.h>
#include <media/v4l2-device.h>
#include <media/v4l2-subdev.h>
#include <media/videobuf-core.h>
#include "atomisp_common.h"
#include "atomisp_compat.h"
#include "atomisp_v4l2.h"
#include "ia_css.h"
/* EXP_ID's ranger is 1 ~ 250 */
#define ATOMISP_MAX_EXP_ID (250)
enum atomisp_subdev_input_entity {
ATOMISP_SUBDEV_INPUT_NONE,
ATOMISP_SUBDEV_INPUT_MEMORY,
ATOMISP_SUBDEV_INPUT_CSI2,
/*
* The following enum for CSI2 port must go together in one row.
* Otherwise it breaks the code logic.
*/
ATOMISP_SUBDEV_INPUT_CSI2_PORT1,
ATOMISP_SUBDEV_INPUT_CSI2_PORT2,
ATOMISP_SUBDEV_INPUT_CSI2_PORT3,
};
#define ATOMISP_SUBDEV_PAD_SINK 0
/* capture output for still frames */
#define ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE 1
/* viewfinder output for downscaled capture output */
#define ATOMISP_SUBDEV_PAD_SOURCE_VF 2
/* preview output for display */
#define ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW 3
/* main output for video pipeline */
#define ATOMISP_SUBDEV_PAD_SOURCE_VIDEO 4
#define ATOMISP_SUBDEV_PADS_NUM 5
struct atomisp_in_fmt_conv {
u32 code;
uint8_t bpp; /* bits per pixel */
uint8_t depth; /* uncompressed */
enum atomisp_input_format atomisp_in_fmt;
enum atomisp_css_bayer_order bayer_order;
enum atomisp_input_format css_stream_fmt;
};
struct atomisp_sub_device;
struct atomisp_video_pipe {
struct video_device vdev;
enum v4l2_buf_type type;
struct media_pad pad;
struct videobuf_queue capq;
struct videobuf_queue outq;
struct list_head activeq;
struct list_head activeq_out;
/*
* the buffers waiting for per-frame parameters, this is only valid
* in per-frame setting mode.
*/
struct list_head buffers_waiting_for_param;
/* the link list to store per_frame parameters */
struct list_head per_frame_params;
unsigned int buffers_in_css;
/* irq_lock is used to protect video buffer state change operations and
* also to make activeq, activeq_out, capq and outq list
* operations atomic. */
spinlock_t irq_lock;
unsigned int users;
struct atomisp_device *isp;
struct v4l2_pix_format pix;
uint32_t sh_fmt;
struct atomisp_sub_device *asd;
/*
* This frame_config_id is got from CSS when dequueues buffers from CSS,
* it is used to indicate which parameter it has applied.
*/
unsigned int frame_config_id[VIDEO_MAX_FRAME];
/*
* This config id is set when camera HAL enqueues buffer, it has a
* non-zero value to indicate which parameter it needs to applu
*/
unsigned int frame_request_config_id[VIDEO_MAX_FRAME];
struct atomisp_css_params_with_list *frame_params[VIDEO_MAX_FRAME];
#ifdef ISP2401
/*
* move wdt from asd struct to create wdt for each pipe
*/
struct timer_list wdt;
unsigned int wdt_duration; /* in jiffies */
unsigned long wdt_expires;
atomic_t wdt_count;
#endif
};
struct atomisp_acc_pipe {
struct video_device vdev;
unsigned int users;
bool running;
struct atomisp_sub_device *asd;
struct atomisp_device *isp;
};
struct atomisp_pad_format {
struct v4l2_mbus_framefmt fmt;
struct v4l2_rect crop;
struct v4l2_rect compose;
};
/* Internal states for flash process */
enum atomisp_flash_state {
ATOMISP_FLASH_IDLE,
ATOMISP_FLASH_REQUESTED,
ATOMISP_FLASH_ONGOING,
ATOMISP_FLASH_DONE
};
/*
* This structure is used to cache the CSS parameters, it aligns to
* struct ia_css_isp_config but without un-supported and deprecated parts.
*/
struct atomisp_css_params {
struct ia_css_wb_config wb_config;
struct ia_css_cc_config cc_config;
struct ia_css_tnr_config tnr_config;
struct ia_css_ecd_config ecd_config;
struct ia_css_ynr_config ynr_config;
struct ia_css_fc_config fc_config;
struct ia_css_formats_config formats_config;
struct ia_css_cnr_config cnr_config;
struct ia_css_macc_config macc_config;
struct ia_css_ctc_config ctc_config;
struct ia_css_aa_config aa_config;
struct ia_css_aa_config baa_config;
struct ia_css_ce_config ce_config;
struct ia_css_ob_config ob_config;
struct ia_css_dp_config dp_config;
struct ia_css_de_config de_config;
struct ia_css_gc_config gc_config;
struct ia_css_nr_config nr_config;
struct ia_css_ee_config ee_config;
struct ia_css_anr_config anr_config;
struct ia_css_3a_config s3a_config;
struct ia_css_xnr_config xnr_config;
struct ia_css_dz_config dz_config;
struct ia_css_cc_config yuv2rgb_cc_config;
struct ia_css_cc_config rgb2yuv_cc_config;
struct ia_css_macc_table macc_table;
struct ia_css_gamma_table gamma_table;
struct ia_css_ctc_table ctc_table;
struct ia_css_xnr_table xnr_table;
struct ia_css_rgb_gamma_table r_gamma_table;
struct ia_css_rgb_gamma_table g_gamma_table;
struct ia_css_rgb_gamma_table b_gamma_table;
struct ia_css_vector motion_vector;
struct ia_css_anr_thres anr_thres;
struct ia_css_dvs_6axis_config *dvs_6axis;
struct ia_css_dvs2_coefficients *dvs2_coeff;
struct ia_css_shading_table *shading_table;
struct ia_css_morph_table *morph_table;
/*
* Used to store the user pointer address of the frame. driver needs to
* translate to ia_css_frame * and then set to CSS.
*/
void *output_frame;
uint32_t isp_config_id;
/* Indicates which parameters need to be updated. */
struct atomisp_parameters update_flag;
};
struct atomisp_subdev_params {
/* FIXME: Determines whether raw capture buffer are being passed to
* user space. Unimplemented for now. */
int online_process;
int yuv_ds_en;
unsigned int color_effect;
bool gdc_cac_en;
bool macc_en;
bool bad_pixel_en;
bool video_dis_en;
bool sc_en;
bool fpn_en;
bool xnr_en;
bool low_light;
int false_color;
unsigned int histogram_elenum;
/* Current grid info */
struct atomisp_css_grid_info curr_grid_info;
enum atomisp_css_pipe_id s3a_enabled_pipe;
int s3a_output_bytes;
bool dis_proj_data_valid;
struct ia_css_dz_config dz_config; /** Digital Zoom */
struct ia_css_capture_config capture_config;
struct atomisp_css_isp_config config;
/* current configurations */
struct atomisp_css_params css_param;
/*
* Intermediate buffers used to communicate data between
* CSS and user space.
*/
struct ia_css_3a_statistics *s3a_user_stat;
void *metadata_user[ATOMISP_METADATA_TYPE_NUM];
uint32_t metadata_width_size;
struct ia_css_dvs2_statistics *dvs_stat;
struct atomisp_css_dvs_6axis *dvs_6axis;
uint32_t exp_id;
int dvs_hor_coef_bytes;
int dvs_ver_coef_bytes;
int dvs_ver_proj_bytes;
int dvs_hor_proj_bytes;
/* Flash */
int num_flash_frames;
enum atomisp_flash_state flash_state;
enum atomisp_frame_status last_frame_status;
/* continuous capture */
struct atomisp_cont_capture_conf offline_parm;
/* Flag to check if driver needs to update params to css */
bool css_update_params_needed;
};
struct atomisp_css_params_with_list {
/* parameters for CSS */
struct atomisp_css_params params;
struct list_head list;
};
struct atomisp_acc_fw {
struct atomisp_css_fw_info *fw;
unsigned int handle;
unsigned int flags;
unsigned int type;
struct {
size_t length;
unsigned long css_ptr;
} args[ATOMISP_ACC_NR_MEMORY];
struct list_head list;
};
struct atomisp_map {
ia_css_ptr ptr;
size_t length;
struct list_head list;
/* FIXME: should keep book which maps are currently used
* by binaries and not allow releasing those
* which are in use. Implement by reference counting.
*/
};
struct atomisp_sub_device {
struct v4l2_subdev subdev;
struct media_pad pads[ATOMISP_SUBDEV_PADS_NUM];
struct atomisp_pad_format fmt[ATOMISP_SUBDEV_PADS_NUM];
uint16_t capture_pad; /* main capture pad; defines much of isp config */
enum atomisp_subdev_input_entity input;
unsigned int output;
struct atomisp_video_pipe video_in;
struct atomisp_video_pipe video_out_capture; /* capture output */
struct atomisp_video_pipe video_out_vf; /* viewfinder output */
struct atomisp_video_pipe video_out_preview; /* preview output */
struct atomisp_acc_pipe video_acc;
/* video pipe main output */
struct atomisp_video_pipe video_out_video_capture;
/* struct isp_subdev_params params; */
spinlock_t lock;
struct atomisp_device *isp;
struct v4l2_ctrl_handler ctrl_handler;
struct v4l2_ctrl *fmt_auto;
struct v4l2_ctrl *run_mode;
struct v4l2_ctrl *depth_mode;
struct v4l2_ctrl *vfpp;
struct v4l2_ctrl *continuous_mode;
struct v4l2_ctrl *continuous_raw_buffer_size;
struct v4l2_ctrl *continuous_viewfinder;
struct v4l2_ctrl *enable_raw_buffer_lock;
#ifdef ISP2401
struct v4l2_ctrl *ion_dev_fd;
#endif
struct v4l2_ctrl *disable_dz;
#ifdef ISP2401
struct v4l2_ctrl *select_isp_version;
#endif
struct {
struct list_head fw;
struct list_head memory_maps;
struct atomisp_css_pipeline *pipeline;
bool extension_mode;
struct ida ida;
struct completion acc_done;
void *acc_stages;
} acc;
struct atomisp_subdev_params params;
struct atomisp_stream_env stream_env[ATOMISP_INPUT_STREAM_NUM];
struct v4l2_pix_format dvs_envelop;
unsigned int s3a_bufs_in_css[CSS_PIPE_ID_NUM];
unsigned int dis_bufs_in_css;
unsigned int metadata_bufs_in_css
[ATOMISP_INPUT_STREAM_NUM][CSS_PIPE_ID_NUM];
/* The list of free and available metadata buffers for CSS */
struct list_head metadata[ATOMISP_METADATA_TYPE_NUM];
/* The list of metadata buffers which have been en-queued to CSS */
struct list_head metadata_in_css[ATOMISP_METADATA_TYPE_NUM];
/* The list of metadata buffers which are ready for userspace to get */
struct list_head metadata_ready[ATOMISP_METADATA_TYPE_NUM];
/* The list of free and available s3a stat buffers for CSS */
struct list_head s3a_stats;
/* The list of s3a stat buffers which have been en-queued to CSS */
struct list_head s3a_stats_in_css;
/* The list of s3a stat buffers which are ready for userspace to get */
struct list_head s3a_stats_ready;
struct list_head dis_stats;
struct list_head dis_stats_in_css;
spinlock_t dis_stats_lock;
struct atomisp_css_frame *vf_frame; /* TODO: needed? */
struct atomisp_css_frame *raw_output_frame;
enum atomisp_frame_status frame_status[VIDEO_MAX_FRAME];
/* This field specifies which camera (v4l2 input) is selected. */
int input_curr;
/* This field specifies which sensor is being selected when there
are multiple sensors connected to the same MIPI port. */
int sensor_curr;
atomic_t sof_count;
atomic_t sequence; /* Sequence value that is assigned to buffer. */
atomic_t sequence_temp;
unsigned int streaming; /* Hold both mutex and lock to change this */
bool stream_prepared; /* whether css stream is created */
/* subdev index: will be used to show which subdev is holding the
* resource, like which camera is used by which subdev
*/
unsigned int index;
/* delayed memory allocation for css */
struct completion init_done;
struct workqueue_struct *delayed_init_workq;
unsigned int delayed_init;
struct work_struct delayed_init_work;
unsigned int latest_preview_exp_id; /* CSS ZSL/SDV raw buffer id */
unsigned int mipi_frame_size;
bool copy_mode; /* CSI2+ use copy mode */
bool yuvpp_mode; /* CSI2+ yuvpp pipe */
int raw_buffer_bitmap[ATOMISP_MAX_EXP_ID/32 + 1]; /* Record each Raw Buffer lock status */
int raw_buffer_locked_count;
spinlock_t raw_buffer_bitmap_lock;
#ifndef ISP2401
struct timer_list wdt;
unsigned int wdt_duration; /* in jiffies */
unsigned long wdt_expires;
#endif
struct atomisp_resolution sensor_array_res;
bool high_speed_mode; /* Indicate whether now is a high speed mode */
int pending_capture_request; /* Indicates the number of pending capture requests. */
#ifndef ISP2401
#else
bool re_trigger_capture;
#endif
unsigned int preview_exp_id;
unsigned int postview_exp_id;
};
extern const struct atomisp_in_fmt_conv atomisp_in_fmt_conv[];
u32 atomisp_subdev_uncompressed_code(u32 code);
bool atomisp_subdev_is_compressed(u32 code);
const struct atomisp_in_fmt_conv *atomisp_find_in_fmt_conv(u32 code);
#ifndef ISP2401
const struct atomisp_in_fmt_conv *atomisp_find_in_fmt_conv_by_atomisp_in_fmt(
enum atomisp_input_format atomisp_in_fmt);
#else
const struct atomisp_in_fmt_conv
*atomisp_find_in_fmt_conv_by_atomisp_in_fmt(enum atomisp_input_format
atomisp_in_fmt);
#endif
const struct atomisp_in_fmt_conv *atomisp_find_in_fmt_conv_compressed(u32 code);
bool atomisp_subdev_format_conversion(struct atomisp_sub_device *asd,
unsigned int source_pad);
uint16_t atomisp_subdev_source_pad(struct video_device *vdev);
/* Get pointer to appropriate format */
struct v4l2_mbus_framefmt
*atomisp_subdev_get_ffmt(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg, uint32_t which,
uint32_t pad);
struct v4l2_rect *atomisp_subdev_get_rect(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
uint32_t which, uint32_t pad,
uint32_t target);
int atomisp_subdev_set_selection(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
uint32_t which, uint32_t pad, uint32_t target,
uint32_t flags, struct v4l2_rect *r);
/* Actually set the format */
void atomisp_subdev_set_ffmt(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg, uint32_t which,
uint32_t pad, struct v4l2_mbus_framefmt *ffmt);
int atomisp_update_run_mode(struct atomisp_sub_device *asd);
void atomisp_subdev_cleanup_pending_events(struct atomisp_sub_device *asd);
void atomisp_subdev_unregister_entities(struct atomisp_sub_device *asd);
int atomisp_subdev_register_entities(struct atomisp_sub_device *asd,
struct v4l2_device *vdev);
int atomisp_subdev_init(struct atomisp_device *isp);
void atomisp_subdev_cleanup(struct atomisp_device *isp);
int atomisp_create_pads_links(struct atomisp_device *isp);
#endif /* __ATOMISP_SUBDEV_H__ */

187
drivers/staging/media/atomisp/pci/atomisp2/atomisp_tables.h
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@ -1,187 +0,0 @@
/*
* Support for Medifield PNW Camera Imaging ISP subsystem.
*
* Copyright (c) 2010 Intel Corporation. All Rights Reserved.
*
* Copyright (c) 2010 Silicon Hive www.siliconhive.com.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
*/
#ifndef __ATOMISP_TABLES_H__
#define __ATOMISP_TABLES_H__
#include "sh_css_params.h"
/*Sepia image effect table*/
static struct atomisp_css_cc_config sepia_cc_config = {
.fraction_bits = 8,
.matrix = {141, 18, 68, -40, -5, -19, 35, 4, 16},
};
/*Negative image effect table*/
static struct atomisp_css_cc_config nega_cc_config = {
.fraction_bits = 8,
.matrix = {255, 29, 120, 0, 374, 342, 0, 672, -301},
};
/*Mono image effect table*/
static struct atomisp_css_cc_config mono_cc_config = {
.fraction_bits = 8,
.matrix = {255, 29, 120, 0, 0, 0, 0, 0, 0},
};
/*Skin whiten image effect table*/
static struct atomisp_css_macc_table skin_low_macc_table = {
.data = {
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
7168, 0, 2048, 8192,
5120, -1024, 2048, 8192,
8192, 2048, -1024, 5120,
8192, 2048, 0, 7168,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192
}
};
static struct atomisp_css_macc_table skin_medium_macc_table = {
.data = {
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
5120, 0, 6144, 8192,
3072, -1024, 2048, 6144,
6144, 2048, -1024, 3072,
8192, 6144, 0, 5120,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192
}
};
static struct atomisp_css_macc_table skin_high_macc_table = {
.data = {
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
4096, 0, 8192, 8192,
0, -2048, 4096, 6144,
6144, 4096, -2048, 0,
8192, 8192, 0, 4096,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192
}
};
/*Blue enhencement image effect table*/
static struct atomisp_css_macc_table blue_macc_table = {
.data = {
9728, -3072, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
9728, 0, -3072, 8192,
12800, 1536, -3072, 8192,
11264, 0, 0, 11264,
9728, -3072, 0, 11264
}
};
/*Green enhencement image effect table*/
static struct atomisp_css_macc_table green_macc_table = {
.data = {
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
10240, 4096, 0, 8192,
10240, 4096, 0, 12288,
12288, 0, 0, 12288,
14336, -2048, 4096, 8192,
10240, 0, 4096, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192,
8192, 0, 0, 8192
}
};
static struct atomisp_css_ctc_table vivid_ctc_table = {
.data.vamem_2 = {
0, 384, 837, 957, 1011, 1062, 1083, 1080,
1078, 1077, 1053, 1039, 1012, 992, 969, 951,
929, 906, 886, 866, 845, 823, 809, 790,
772, 758, 741, 726, 711, 701, 688, 675,
666, 656, 648, 639, 633, 626, 618, 612,
603, 594, 582, 572, 557, 545, 529, 516,
504, 491, 480, 467, 459, 447, 438, 429,
419, 412, 404, 397, 389, 382, 376, 368,
363, 357, 351, 345, 340, 336, 330, 326,
321, 318, 312, 308, 304, 300, 297, 294,
291, 286, 284, 281, 278, 275, 271, 268,
261, 257, 251, 245, 240, 235, 232, 225,
223, 218, 213, 209, 206, 204, 199, 197,
193, 189, 186, 185, 183, 179, 177, 175,
172, 170, 169, 167, 164, 164, 162, 160,
158, 157, 156, 154, 154, 152, 151, 150,
149, 148, 146, 147, 146, 144, 143, 143,
142, 141, 140, 141, 139, 138, 138, 138,
137, 136, 136, 135, 134, 134, 134, 133,
132, 132, 131, 130, 131, 130, 129, 128,
129, 127, 127, 127, 127, 125, 125, 125,
123, 123, 122, 120, 118, 115, 114, 111,
110, 108, 106, 105, 103, 102, 100, 99,
97, 97, 96, 95, 94, 93, 93, 91,
91, 91, 90, 90, 89, 89, 88, 88,
89, 88, 88, 87, 87, 87, 87, 86,
87, 87, 86, 87, 86, 86, 84, 84,
82, 80, 78, 76, 74, 72, 70, 68,
67, 65, 62, 60, 58, 56, 55, 54,
53, 51, 49, 49, 47, 45, 45, 45,
41, 40, 39, 39, 34, 33, 34, 32,
25, 23, 24, 20, 13, 9, 12, 0,
0
}
};
#endif

164
drivers/staging/media/atomisp/pci/atomisp2/atomisp_tpg.c
View File

@ -1,164 +0,0 @@
/*
* Support for Medifield PNW Camera Imaging ISP subsystem.
*
* Copyright (c) 2010 Intel Corporation. All Rights Reserved.
*
* Copyright (c) 2010 Silicon Hive www.siliconhive.com.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
*/
#include <media/v4l2-event.h>
#include <media/v4l2-mediabus.h>
#include "atomisp_internal.h"
#include "atomisp_tpg.h"
static int tpg_s_stream(struct v4l2_subdev *sd, int enable)
{
return 0;
}
static int tpg_get_fmt(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_format *format)
{
/*to fake*/
return 0;
}
static int tpg_set_fmt(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_format *format)
{
struct v4l2_mbus_framefmt *fmt = &format->format;
if (format->pad)
return -EINVAL;
/* only raw8 grbg is supported by TPG */
fmt->code = MEDIA_BUS_FMT_SGRBG8_1X8;
if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
cfg->try_fmt = *fmt;
return 0;
}
return 0;
}
static int tpg_log_status(struct v4l2_subdev *sd)
{
/*to fake*/
return 0;
}
static int tpg_s_power(struct v4l2_subdev *sd, int on)
{
return 0;
}
static int tpg_enum_mbus_code(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_mbus_code_enum *code)
{
/*to fake*/
return 0;
}
static int tpg_enum_frame_size(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_frame_size_enum *fse)
{
/*to fake*/
return 0;
}
static int tpg_enum_frame_ival(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_frame_interval_enum *fie)
{
/*to fake*/
return 0;
}
static const struct v4l2_subdev_video_ops tpg_video_ops = {
.s_stream = tpg_s_stream,
};
static const struct v4l2_subdev_core_ops tpg_core_ops = {
.log_status = tpg_log_status,
.s_power = tpg_s_power,
};
static const struct v4l2_subdev_pad_ops tpg_pad_ops = {
.enum_mbus_code = tpg_enum_mbus_code,
.enum_frame_size = tpg_enum_frame_size,
.enum_frame_interval = tpg_enum_frame_ival,
.get_fmt = tpg_get_fmt,
.set_fmt = tpg_set_fmt,
};
static const struct v4l2_subdev_ops tpg_ops = {
.core = &tpg_core_ops,
.video = &tpg_video_ops,
.pad = &tpg_pad_ops,
};
void atomisp_tpg_unregister_entities(struct atomisp_tpg_device *tpg)
{
media_entity_cleanup(&tpg->sd.entity);
v4l2_device_unregister_subdev(&tpg->sd);
}
int atomisp_tpg_register_entities(struct atomisp_tpg_device *tpg,
struct v4l2_device *vdev)
{
int ret;
/* Register the subdev and video nodes. */
ret = v4l2_device_register_subdev(vdev, &tpg->sd);
if (ret < 0)
goto error;
return 0;
error:
atomisp_tpg_unregister_entities(tpg);
return ret;
}
void atomisp_tpg_cleanup(struct atomisp_device *isp)
{
}
int atomisp_tpg_init(struct atomisp_device *isp)
{
struct atomisp_tpg_device *tpg = &isp->tpg;
struct v4l2_subdev *sd = &tpg->sd;
struct media_pad *pads = tpg->pads;
struct media_entity *me = &sd->entity;
int ret;
tpg->isp = isp;
v4l2_subdev_init(sd, &tpg_ops);
sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
strcpy(sd->name, "tpg_subdev");
v4l2_set_subdevdata(sd, tpg);
pads[0].flags = MEDIA_PAD_FL_SINK;
me->function = MEDIA_ENT_F_V4L2_SUBDEV_UNKNOWN;
ret = media_entity_pads_init(me, 1, pads);
if (ret < 0)
goto fail;
return 0;
fail:
atomisp_tpg_cleanup(isp);
return ret;
}

38
drivers/staging/media/atomisp/pci/atomisp2/atomisp_tpg.h
View File

@ -1,38 +0,0 @@
/*
* Support for Medifield PNW Camera Imaging ISP subsystem.
*
* Copyright (c) 2010 Intel Corporation. All Rights Reserved.
*
* Copyright (c) 2010 Silicon Hive www.siliconhive.com.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
*/
#ifndef __ATOMISP_TPG_H__
#define __ATOMISP_TPG_H__
#include <media/media-entity.h>
#include <media/v4l2-subdev.h>
struct atomisp_tpg_device {
struct v4l2_subdev sd;
struct atomisp_device *isp;
struct media_pad pads[1];
};
void atomisp_tpg_cleanup(struct atomisp_device *isp);
int atomisp_tpg_init(struct atomisp_device *isp);
void atomisp_tpg_unregister_entities(struct atomisp_tpg_device *tpg);
int atomisp_tpg_register_entities(struct atomisp_tpg_device *tpg,
struct v4l2_device *vdev);
#endif /* __ATOMISP_TPG_H__ */

129
drivers/staging/media/atomisp/pci/atomisp2/atomisp_trace_event.h
View File

@ -1,129 +0,0 @@
/*
* Support Camera Imaging tracer core.
*
* Copyright (c) 2013 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
*/
#undef TRACE_SYSTEM
#define TRACE_SYSTEM atomisp
#if !defined(ATOMISP_TRACE_EVENT_H) || defined(TRACE_HEADER_MULTI_READ)
#define ATOMISP_TRACE_EVENT_H
#include <linux/tracepoint.h>
#include <linux/string.h>
TRACE_EVENT(camera_meminfo,
TP_PROTO(const char *name, int uptr_size, int counter, int sys_size,
int sys_res_size, int cam_sys_use, int cam_dyc_use,
int cam_res_use),
TP_ARGS(name, uptr_size, counter, sys_size, sys_res_size, cam_sys_use,
cam_dyc_use, cam_res_use),
TP_STRUCT__entry(
__array(char, name, 24)
__field(int, uptr_size)
__field(int, counter)
__field(int, sys_size)
__field(int, sys_res_size)
__field(int, cam_res_use)
__field(int, cam_dyc_use)
__field(int, cam_sys_use)
),
TP_fast_assign(
strlcpy(__entry->name, name, 24);
__entry->uptr_size = uptr_size;
__entry->counter = counter;
__entry->sys_size = sys_size;
__entry->sys_res_size = sys_res_size;
__entry->cam_res_use = cam_res_use;
__entry->cam_dyc_use = cam_dyc_use;
__entry->cam_sys_use = cam_sys_use;
),
TP_printk(
"<%s> User ptr memory:%d pages,\tISP private memory used:%d"
" pages:\tsysFP system size:%d,\treserved size:%d"
"\tcamFP sysUse:%d,\tdycUse:%d,\tresUse:%d.\n",
__entry->name, __entry->uptr_size, __entry->counter,
__entry->sys_size, __entry->sys_res_size, __entry->cam_sys_use,
__entry->cam_dyc_use, __entry->cam_res_use)
);
TRACE_EVENT(camera_debug,
TP_PROTO(const char *name, char *info, const int line),
TP_ARGS(name, info, line),
TP_STRUCT__entry(
__array(char, name, 24)
__array(char, info, 24)
__field(int, line)
),
TP_fast_assign(
strlcpy(__entry->name, name, 24);
strlcpy(__entry->info, info, 24);
__entry->line = line;
),
TP_printk("<%s>-<%d> %s\n", __entry->name, __entry->line,
__entry->info)
);
TRACE_EVENT(ipu_cstate,
TP_PROTO(int cstate),
TP_ARGS(cstate),
TP_STRUCT__entry(
__field(int, cstate)
),
TP_fast_assign(
__entry->cstate = cstate;
),
TP_printk("cstate=%d", __entry->cstate)
);
TRACE_EVENT(ipu_pstate,
TP_PROTO(int freq, int util),
TP_ARGS(freq, util),
TP_STRUCT__entry(
__field(int, freq)
__field(int, util)
),
TP_fast_assign(
__entry->freq = freq;
__entry->util = util;
),
TP_printk("freq=%d util=%d", __entry->freq, __entry->util)
);
#endif
#undef TRACE_INCLUDE_PATH
#undef TRACE_INCLUDE_FILE
#define TRACE_INCLUDE_PATH .
#define TRACE_INCLUDE_FILE atomisp_trace_event
/* This part must be outside protection */
#include <trace/define_trace.h>

1562
drivers/staging/media/atomisp/pci/atomisp2/atomisp_v4l2.c
View File

File diff suppressed because it is too large Load Diff

40
drivers/staging/media/atomisp/pci/atomisp2/atomisp_v4l2.h
View File

@ -1,40 +0,0 @@
/*
* Support for Medifield PNW Camera Imaging ISP subsystem.
*
* Copyright (c) 2010 Intel Corporation. All Rights Reserved.
*
* Copyright (c) 2010 Silicon Hive www.siliconhive.com.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
*/
#ifndef __ATOMISP_V4L2_H__
#define __ATOMISP_V4L2_H__
struct atomisp_video_pipe;
struct atomisp_acc_pipe;
struct v4l2_device;
struct atomisp_device;
struct firmware;
int atomisp_video_init(struct atomisp_video_pipe *video, const char *name);
void atomisp_acc_init(struct atomisp_acc_pipe *video, const char *name);
void atomisp_video_unregister(struct atomisp_video_pipe *video);
int atomisp_video_register(struct atomisp_video_pipe *video,
struct v4l2_device *vdev);
void atomisp_acc_unregister(struct atomisp_acc_pipe *video);
int atomisp_acc_register(struct atomisp_acc_pipe *video,
struct v4l2_device *vdev);
const struct firmware *atomisp_load_firmware(struct atomisp_device *isp);
int atomisp_csi_lane_config(struct atomisp_device *isp);
#endif /* __ATOMISP_V4L2_H__ */

2
drivers/staging/media/atomisp/pci/atomisp2/css2400/Makefile
View File

@ -1,2 +0,0 @@
ccflags-y += -DISP2400B0
ISP2400B0 := y

376
drivers/staging/media/atomisp/pci/atomisp2/css2400/base/circbuf/interface/ia_css_circbuf.h
View File

@ -1,376 +0,0 @@
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _IA_CSS_CIRCBUF_H
#define _IA_CSS_CIRCBUF_H
#include <sp.h>
#include <type_support.h>
#include <math_support.h>
#include <assert_support.h>
#include <platform_support.h>
#include "ia_css_circbuf_comm.h"
#include "ia_css_circbuf_desc.h"
/****************************************************************
*
* Data structures.
*
****************************************************************/
/**
* @brief Data structure for the circular buffer.
*/
typedef struct ia_css_circbuf_s ia_css_circbuf_t;
struct ia_css_circbuf_s {
ia_css_circbuf_desc_t *desc; /* Pointer to the descriptor of the circbuf */
ia_css_circbuf_elem_t *elems; /* an array of elements */
};
/**
* @brief Create the circular buffer.
*
* @param cb The pointer to the circular buffer.
* @param elems An array of elements.
* @param desc The descriptor set to the size using ia_css_circbuf_desc_init().
*/
extern void ia_css_circbuf_create(
ia_css_circbuf_t *cb,
ia_css_circbuf_elem_t *elems,
ia_css_circbuf_desc_t *desc);
/**
* @brief Destroy the circular buffer.
*
* @param cb The pointer to the circular buffer.
*/
extern void ia_css_circbuf_destroy(
ia_css_circbuf_t *cb);
/**
* @brief Pop a value out of the circular buffer.
* Get a value at the head of the circular buffer.
* The user should call "ia_css_circbuf_is_empty()"
* to avoid accessing to an empty buffer.
*
* @param cb The pointer to the circular buffer.
*
* @return the pop-out value.
*/
extern uint32_t ia_css_circbuf_pop(
ia_css_circbuf_t *cb);
/**
* @brief Extract a value out of the circular buffer.
* Get a value at an arbitrary poistion in the circular
* buffer. The user should call "ia_css_circbuf_is_empty()"
* to avoid accessing to an empty buffer.
*
* @param cb The pointer to the circular buffer.
* @param offset The offset from "start" to the target position.
*
* @return the extracted value.
*/
extern uint32_t ia_css_circbuf_extract(
ia_css_circbuf_t *cb,
int offset);
/****************************************************************
*
* Inline functions.
*
****************************************************************/
/**
* @brief Set the "val" field in the element.
*
* @param elem The pointer to the element.
* @param val The value to be set.
*/
static inline void ia_css_circbuf_elem_set_val(
ia_css_circbuf_elem_t *elem,
uint32_t val)
{
OP___assert(elem != NULL);
elem->val = val;
}
/**
* @brief Initialize the element.
*
* @param elem The pointer to the element.
*/
static inline void ia_css_circbuf_elem_init(
ia_css_circbuf_elem_t *elem)
{
OP___assert(elem != NULL);
ia_css_circbuf_elem_set_val(elem, 0);
}
/**
* @brief Copy an element.
*
* @param src The element as the copy source.
* @param dest The element as the copy destination.
*/
static inline void ia_css_circbuf_elem_cpy(
ia_css_circbuf_elem_t *src,
ia_css_circbuf_elem_t *dest)
{
OP___assert(src != NULL);
OP___assert(dest != NULL);
ia_css_circbuf_elem_set_val(dest, src->val);
}
/**
* @brief Get position in the circular buffer.
*
* @param cb The pointer to the circular buffer.
* @param base The base position.
* @param offset The offset.
*
* @return the position at offset.
*/
static inline uint8_t ia_css_circbuf_get_pos_at_offset(
ia_css_circbuf_t *cb,
uint32_t base,
int offset)
{
uint8_t dest;
OP___assert(cb != NULL);
OP___assert(cb->desc != NULL);
OP___assert(cb->desc->size > 0);
/* step 1: adjudst the offset */
while (offset < 0) {
offset += cb->desc->size;
}
/* step 2: shift and round by the upper limit */
dest = OP_std_modadd(base, offset, cb->desc->size);
return dest;
}
/**
* @brief Get the offset between two positions in the circular buffer.
* Get the offset from the source position to the terminal position,
* along the direction in which the new elements come in.
*
* @param cb The pointer to the circular buffer.
* @param src_pos The source position.
* @param dest_pos The terminal position.
*
* @return the offset.
*/
static inline int ia_css_circbuf_get_offset(
ia_css_circbuf_t *cb,
uint32_t src_pos,
uint32_t dest_pos)
{
int offset;
OP___assert(cb != NULL);
OP___assert(cb->desc != NULL);
offset = (int)(dest_pos - src_pos);
offset += (offset < 0) ? cb->desc->size : 0;
return offset;
}
/**
* @brief Get the maximum number of elements.
*
* @param cb The pointer to the circular buffer.
*
* @return the maximum number of elements.
*
* TODO: Test this API.
*/
static inline uint32_t ia_css_circbuf_get_size(
ia_css_circbuf_t *cb)
{
OP___assert(cb != NULL);
OP___assert(cb->desc != NULL);
return cb->desc->size;
}
/**
* @brief Get the number of available elements.
*
* @param cb The pointer to the circular buffer.
*
* @return the number of available elements.
*/
static inline uint32_t ia_css_circbuf_get_num_elems(
ia_css_circbuf_t *cb)
{
int num;
OP___assert(cb != NULL);
OP___assert(cb->desc != NULL);
num = ia_css_circbuf_get_offset(cb, cb->desc->start, cb->desc->end);
return (uint32_t)num;
}
/**
* @brief Test if the circular buffer is empty.
*
* @param cb The pointer to the circular buffer.
*
* @return
* - true when it is empty.
* - false when it is not empty.
*/
static inline bool ia_css_circbuf_is_empty(
ia_css_circbuf_t *cb)
{
OP___assert(cb != NULL);
OP___assert(cb->desc != NULL);
return ia_css_circbuf_desc_is_empty(cb->desc);
}
/**
* @brief Test if the circular buffer is full.
*
* @param cb The pointer to the circular buffer.
*
* @return
* - true when it is full.
* - false when it is not full.
*/
static inline bool ia_css_circbuf_is_full(ia_css_circbuf_t *cb)
{
OP___assert(cb != NULL);
OP___assert(cb->desc != NULL);
return ia_css_circbuf_desc_is_full(cb->desc);
}
/**
* @brief Write a new element into the circular buffer.
* Write a new element WITHOUT checking whether the
* circular buffer is full or not. So it also overwrites
* the oldest element when the buffer is full.
*
* @param cb The pointer to the circular buffer.
* @param elem The new element.
*/
static inline void ia_css_circbuf_write(
ia_css_circbuf_t *cb,
ia_css_circbuf_elem_t elem)
{
OP___assert(cb != NULL);
OP___assert(cb->desc != NULL);
/* Cannot continue as the queue is full*/
assert(!ia_css_circbuf_is_full(cb));
ia_css_circbuf_elem_cpy(&elem, &cb->elems[cb->desc->end]);
cb->desc->end = ia_css_circbuf_get_pos_at_offset(cb, cb->desc->end, 1);
}
/**
* @brief Push a value in the circular buffer.
* Put a new value at the tail of the circular buffer.
* The user should call "ia_css_circbuf_is_full()"
* to avoid accessing to a full buffer.
*
* @param cb The pointer to the circular buffer.
* @param val The value to be pushed in.
*/
static inline void ia_css_circbuf_push(
ia_css_circbuf_t *cb,
uint32_t val)
{
ia_css_circbuf_elem_t elem;
OP___assert(cb != NULL);
/* set up an element */
ia_css_circbuf_elem_init(&elem);
ia_css_circbuf_elem_set_val(&elem, val);
/* write the element into the buffer */
ia_css_circbuf_write(cb, elem);
}
/**
* @brief Get the number of free elements.
*
* @param cb The pointer to the circular buffer.
*
* @return: The number of free elements.
*/
static inline uint32_t ia_css_circbuf_get_free_elems(
ia_css_circbuf_t *cb)
{
OP___assert(cb != NULL);
OP___assert(cb->desc != NULL);
return ia_css_circbuf_desc_get_free_elems(cb->desc);
}
/**
* @brief Peek an element in Circular Buffer.
*
* @param cb The pointer to the circular buffer.
* @param offset Offset to the element.
*
* @return the elements value.
*/
extern uint32_t ia_css_circbuf_peek(
ia_css_circbuf_t *cb,
int offset);
/**
* @brief Get an element in Circular Buffer.
*
* @param cb The pointer to the circular buffer.
* @param offset Offset to the element.
*
* @return the elements value.
*/
extern uint32_t ia_css_circbuf_peek_from_start(
ia_css_circbuf_t *cb,
int offset);
/**
* @brief Increase Size of a Circular Buffer.
* Use 'CAUTION' before using this function, This was added to
* support / fix issue with increasing size for tagger only
*
* @param cb The pointer to the circular buffer.
* @param sz_delta delta increase for new size
* @param elems (optional) pointers to new additional elements
* cb element array size will not be increased dynamically,
* but new elements should be added at the end to existing
* cb element array which if of max_size >= new size
*
* @return true on succesfully increasing the size
* false on failure
*/
extern bool ia_css_circbuf_increase_size(
ia_css_circbuf_t *cb,
unsigned int sz_delta,
ia_css_circbuf_elem_t *elems);
#endif /*_IA_CSS_CIRCBUF_H */

56
drivers/staging/media/atomisp/pci/atomisp2/css2400/base/circbuf/interface/ia_css_circbuf_comm.h
View File

@ -1,56 +0,0 @@
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _IA_CSS_CIRCBUF_COMM_H
#define _IA_CSS_CIRCBUF_COMM_H
#include <type_support.h> /* uint8_t, uint32_t */
#define IA_CSS_CIRCBUF_PADDING 1 /* The circular buffer is implemented in lock-less manner, wherein
* the head and tail can advance independently without any locks.
* But to achieve this, an extra buffer element is required to detect
* queue full & empty conditions, wherein the tail trails the head for
* full and is equal to head for empty condition. This causes 1 buffer
* not being available for use.
*/
/****************************************************************
*
* Portable Data structures
*
****************************************************************/
/**
* @brief Data structure for the circular descriptor.
*/
typedef struct ia_css_circbuf_desc_s ia_css_circbuf_desc_t;
struct ia_css_circbuf_desc_s {
uint8_t size; /* the maximum number of elements*/
uint8_t step; /* number of bytes per element */
uint8_t start; /* index of the oldest element */
uint8_t end; /* index at which to write the new element */
};
#define SIZE_OF_IA_CSS_CIRCBUF_DESC_S_STRUCT \
(4 * sizeof(uint8_t))
/**
* @brief Data structure for the circular buffer element.
*/
typedef struct ia_css_circbuf_elem_s ia_css_circbuf_elem_t;
struct ia_css_circbuf_elem_s {
uint32_t val; /* the value stored in the element */
};
#define SIZE_OF_IA_CSS_CIRCBUF_ELEM_S_STRUCT \
(sizeof(uint32_t))
#endif /*_IA_CSS_CIRCBUF_COMM_H*/

169
drivers/staging/media/atomisp/pci/atomisp2/css2400/base/circbuf/interface/ia_css_circbuf_desc.h
View File

@ -1,169 +0,0 @@
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _IA_CSS_CIRCBUF_DESC_H_
#define _IA_CSS_CIRCBUF_DESC_H_
#include <type_support.h>
#include <math_support.h>
#include <platform_support.h>
#include <sp.h>
#include "ia_css_circbuf_comm.h"
/****************************************************************
*
* Inline functions.
*
****************************************************************/
/**
* @brief Test if the circular buffer is empty.
*
* @param cb_desc The pointer to the circular buffer descriptor.
*
* @return
* - true when it is empty.
* - false when it is not empty.
*/
static inline bool ia_css_circbuf_desc_is_empty(
ia_css_circbuf_desc_t *cb_desc)
{
OP___assert(cb_desc != NULL);
return (cb_desc->end == cb_desc->start);
}
/**
* @brief Test if the circular buffer descriptor is full.
*
* @param cb_desc The pointer to the circular buffer
* descriptor.
*
* @return
* - true when it is full.
* - false when it is not full.
*/
static inline bool ia_css_circbuf_desc_is_full(
ia_css_circbuf_desc_t *cb_desc)
{
OP___assert(cb_desc != NULL);
return (OP_std_modadd(cb_desc->end, 1, cb_desc->size) == cb_desc->start);
}
/**
* @brief Initialize the circular buffer descriptor
*
* @param cb_desc The pointer circular buffer descriptor
* @param size The size of the circular buffer
*/
static inline void ia_css_circbuf_desc_init(
ia_css_circbuf_desc_t *cb_desc,
int8_t size)
{
OP___assert(cb_desc != NULL);
cb_desc->size = size;
}
/**
* @brief Get a position in the circular buffer descriptor.
*
* @param cb The pointer to the circular buffer descriptor.
* @param base The base position.
* @param offset The offset.
*
* @return the position in the circular buffer descriptor.
*/
static inline uint8_t ia_css_circbuf_desc_get_pos_at_offset(
ia_css_circbuf_desc_t *cb_desc,
uint32_t base,
int offset)
{
uint8_t dest;
OP___assert(cb_desc != NULL);
OP___assert(cb_desc->size > 0);
/* step 1: adjust the offset */
while (offset < 0) {
offset += cb_desc->size;
}
/* step 2: shift and round by the upper limit */
dest = OP_std_modadd(base, offset, cb_desc->size);
return dest;
}
/**
* @brief Get the offset between two positions in the circular buffer
* descriptor.
* Get the offset from the source position to the terminal position,
* along the direction in which the new elements come in.
*
* @param cb_desc The pointer to the circular buffer descriptor.
* @param src_pos The source position.
* @param dest_pos The terminal position.
*
* @return the offset.
*/
static inline int ia_css_circbuf_desc_get_offset(
ia_css_circbuf_desc_t *cb_desc,
uint32_t src_pos,
uint32_t dest_pos)
{
int offset;
OP___assert(cb_desc != NULL);
offset = (int)(dest_pos - src_pos);
offset += (offset < 0) ? cb_desc->size : 0;
return offset;
}
/**
* @brief Get the number of available elements.
*
* @param cb_desc The pointer to the circular buffer.
*
* @return The number of available elements.
*/
static inline uint32_t ia_css_circbuf_desc_get_num_elems(
ia_css_circbuf_desc_t *cb_desc)
{
int num;
OP___assert(cb_desc != NULL);
num = ia_css_circbuf_desc_get_offset(cb_desc,
cb_desc->start,
cb_desc->end);
return (uint32_t)num;
}
/**
* @brief Get the number of free elements.
*
* @param cb_desc The pointer to the circular buffer descriptor.
*
* @return: The number of free elements.
*/
static inline uint32_t ia_css_circbuf_desc_get_free_elems(
ia_css_circbuf_desc_t *cb_desc)
{
uint32_t num;
OP___assert(cb_desc != NULL);
num = ia_css_circbuf_desc_get_offset(cb_desc,
cb_desc->start,
cb_desc->end);
return (cb_desc->size - num);
}
#endif /*_IA_CSS_CIRCBUF_DESC_H_ */

321
drivers/staging/media/atomisp/pci/atomisp2/css2400/base/circbuf/src/circbuf.c
View File

@ -1,321 +0,0 @@
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#include "ia_css_circbuf.h"
#include <assert_support.h>
/**********************************************************************
*
* Forward declarations.
*
**********************************************************************/
/*
* @brief Read the oldest element from the circular buffer.
* Read the oldest element WITHOUT checking whehter the
* circular buffer is empty or not. The oldest element is
* also removed out from the circular buffer.
*
* @param cb The pointer to the circular buffer.
*
* @return the oldest element.
*/
static inline ia_css_circbuf_elem_t
ia_css_circbuf_read(ia_css_circbuf_t *cb);
/*
* @brief Shift a chunk of elements in the circular buffer.
* A chunk of elements (i.e. the ones from the "start" position
* to the "chunk_src" position) are shifted in the circular buffer,
* along the direction of new elements coming.
*
* @param cb The pointer to the circular buffer.
* @param chunk_src The position at which the first element in the chunk is.
* @param chunk_dest The position to which the first element in the chunk would be shift.
*/
static inline void ia_css_circbuf_shift_chunk(ia_css_circbuf_t *cb,
uint32_t chunk_src,
uint32_t chunk_dest);
/*
* @brief Get the "val" field in the element.
*
* @param elem The pointer to the element.
*
* @return the "val" field.
*/
static inline uint32_t
ia_css_circbuf_elem_get_val(ia_css_circbuf_elem_t *elem);
/**********************************************************************
*
* Non-inline functions.
*
**********************************************************************/
/*
* @brief Create the circular buffer.
* Refer to "ia_css_circbuf.h" for details.
*/
void
ia_css_circbuf_create(ia_css_circbuf_t *cb,
ia_css_circbuf_elem_t *elems,
ia_css_circbuf_desc_t *desc)
{
uint32_t i;
OP___assert(desc);
cb->desc = desc;
/* Initialize to defaults */
cb->desc->start = 0;
cb->desc->end = 0;
cb->desc->step = 0;
for (i = 0; i < cb->desc->size; i++)
ia_css_circbuf_elem_init(&elems[i]);
cb->elems = elems;
}
/*
* @brief Destroy the circular buffer.
* Refer to "ia_css_circbuf.h" for details.
*/
void ia_css_circbuf_destroy(ia_css_circbuf_t *cb)
{
cb->desc = NULL;
cb->elems = NULL;
}
/*
* @brief Pop a value out of the circular buffer.
* Refer to "ia_css_circbuf.h" for details.
*/
uint32_t ia_css_circbuf_pop(ia_css_circbuf_t *cb)
{
uint32_t ret;
ia_css_circbuf_elem_t elem;
assert(!ia_css_circbuf_is_empty(cb));
/* read an element from the buffer */
elem = ia_css_circbuf_read(cb);
ret = ia_css_circbuf_elem_get_val(&elem);
return ret;
}
/*
* @brief Extract a value out of the circular buffer.
* Refer to "ia_css_circbuf.h" for details.
*/
uint32_t ia_css_circbuf_extract(ia_css_circbuf_t *cb, int offset)
{
int max_offset;
uint32_t val;
uint32_t pos;
uint32_t src_pos;
uint32_t dest_pos;
/* get the maximum offest */
max_offset = ia_css_circbuf_get_offset(cb, cb->desc->start, cb->desc->end);
max_offset--;
/*
* Step 1: When the target element is at the "start" position.
*/
if (offset == 0) {
val = ia_css_circbuf_pop(cb);
return val;
}
/*
* Step 2: When the target element is out of the range.
*/
if (offset > max_offset) {
val = 0;
return val;
}
/*
* Step 3: When the target element is between the "start" and
* "end" position.
*/
/* get the position of the target element */
pos = ia_css_circbuf_get_pos_at_offset(cb, cb->desc->start, offset);
/* get the value from the target element */
val = ia_css_circbuf_elem_get_val(&cb->elems[pos]);
/* shift the elements */
src_pos = ia_css_circbuf_get_pos_at_offset(cb, pos, -1);
dest_pos = pos;
ia_css_circbuf_shift_chunk(cb, src_pos, dest_pos);
return val;
}
/*
* @brief Peek an element from the circular buffer.
* Refer to "ia_css_circbuf.h" for details.
*/
uint32_t ia_css_circbuf_peek(ia_css_circbuf_t *cb, int offset)
{
int pos;
pos = ia_css_circbuf_get_pos_at_offset(cb, cb->desc->end, offset);
/* get the value at the position */
return cb->elems[pos].val;
}
/*
* @brief Get the value of an element from the circular buffer.
* Refer to "ia_css_circbuf.h" for details.
*/
uint32_t ia_css_circbuf_peek_from_start(ia_css_circbuf_t *cb, int offset)
{
int pos;
pos = ia_css_circbuf_get_pos_at_offset(cb, cb->desc->start, offset);
/* get the value at the position */
return cb->elems[pos].val;
}
/* @brief increase size of a circular buffer.
* Use 'CAUTION' before using this function. This was added to
* support / fix issue with increasing size for tagger only
* Please refer to "ia_css_circbuf.h" for details.
*/
bool ia_css_circbuf_increase_size(
ia_css_circbuf_t *cb,
unsigned int sz_delta,
ia_css_circbuf_elem_t *elems)
{
uint8_t curr_size;
uint8_t curr_end;
unsigned int i = 0;
if (!cb || sz_delta == 0)
return false;
curr_size = cb->desc->size;
curr_end = cb->desc->end;
/* We assume cb was pre defined as global to allow
* increase in size */
/* FM: are we sure this cannot cause size to become too big? */
if (((uint8_t)(cb->desc->size + (uint8_t)sz_delta) > cb->desc->size) && ((uint8_t)sz_delta == sz_delta))
cb->desc->size += (uint8_t)sz_delta;
else
return false; /* overflow in size */
/* If elems are passed update them else we assume its been taken
* care before calling this function */
if (elems) {
/* cb element array size will not be increased dynamically,
* but pointers to new elements can be added at the end
* of existing pre defined cb element array of
* size >= new size if not already added */
for (i = curr_size; i < cb->desc->size; i++)
cb->elems[i] = elems[i - curr_size];
}
/* Fix Start / End */
if (curr_end < cb->desc->start) {
if (curr_end == 0) {
/* Easily fix End */
cb->desc->end = curr_size;
} else {
/* Move elements and fix Start*/
ia_css_circbuf_shift_chunk(cb,
curr_size - 1,
curr_size + sz_delta - 1);
}
}
return true;
}
/****************************************************************
*
* Inline functions.
*
****************************************************************/
/*
* @brief Get the "val" field in the element.
* Refer to "Forward declarations" for details.
*/
static inline uint32_t
ia_css_circbuf_elem_get_val(ia_css_circbuf_elem_t *elem)
{
return elem->val;
}
/*
* @brief Read the oldest element from the circular buffer.
* Refer to "Forward declarations" for details.
*/
static inline ia_css_circbuf_elem_t
ia_css_circbuf_read(ia_css_circbuf_t *cb)
{
ia_css_circbuf_elem_t elem;
/* get the element from the target position */
elem = cb->elems[cb->desc->start];
/* clear the target position */
ia_css_circbuf_elem_init(&cb->elems[cb->desc->start]);
/* adjust the "start" position */
cb->desc->start = ia_css_circbuf_get_pos_at_offset(cb, cb->desc->start, 1);
return elem;
}
/*
* @brief Shift a chunk of elements in the circular buffer.
* Refer to "Forward declarations" for details.
*/
static inline void
ia_css_circbuf_shift_chunk(ia_css_circbuf_t *cb,
uint32_t chunk_src, uint32_t chunk_dest)
{
int chunk_offset;
int chunk_sz;
int i;
/* get the chunk offset and size */
chunk_offset = ia_css_circbuf_get_offset(cb,
chunk_src, chunk_dest);
chunk_sz = ia_css_circbuf_get_offset(cb, cb->desc->start, chunk_src) + 1;
/* shift each element to its terminal position */
for (i = 0; i < chunk_sz; i++) {
/* copy the element from the source to the destination */
ia_css_circbuf_elem_cpy(&cb->elems[chunk_src],
&cb->elems[chunk_dest]);
/* clear the source position */
ia_css_circbuf_elem_init(&cb->elems[chunk_src]);
/* adjust the source/terminal positions */
chunk_src = ia_css_circbuf_get_pos_at_offset(cb, chunk_src, -1);
chunk_dest = ia_css_circbuf_get_pos_at_offset(cb, chunk_dest, -1);
}
/* adjust the index "start" */
cb->desc->start = ia_css_circbuf_get_pos_at_offset(cb, cb->desc->start, chunk_offset);
}

83
drivers/staging/media/atomisp/pci/atomisp2/css2400/base/refcount/interface/ia_css_refcount.h
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@ -1,83 +0,0 @@
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _IA_CSS_REFCOUNT_H_
#define _IA_CSS_REFCOUNT_H_
#include <type_support.h>
#include <system_types.h>
#include <ia_css_err.h>
typedef void (*clear_func)(hrt_vaddress ptr);
/*! \brief Function for initializing refcount list
*
* \param[in] size Size of the refcount list.
* \return ia_css_err
*/
extern enum ia_css_err ia_css_refcount_init(uint32_t size);
/*! \brief Function for de-initializing refcount list
*
* \return None
*/
extern void ia_css_refcount_uninit(void);
/*! \brief Function for increasing reference by 1.
*
* \param[in] id ID of the object.
* \param[in] ptr Data of the object (ptr).
* \return hrt_vaddress (saved address)
*/
extern hrt_vaddress ia_css_refcount_increment(int32_t id, hrt_vaddress ptr);
/*! \brief Function for decrease reference by 1.
*
* \param[in] id ID of the object.
* \param[in] ptr Data of the object (ptr).
*
* - true, if it is successful.
* - false, otherwise.
*/
extern bool ia_css_refcount_decrement(int32_t id, hrt_vaddress ptr);
/*! \brief Function to check if reference count is 1.
*
* \param[in] ptr Data of the object (ptr).
*
* - true, if it is successful.
* - false, otherwise.
*/
extern bool ia_css_refcount_is_single(hrt_vaddress ptr);
/*! \brief Function to clear reference list objects.
*
* \param[in] id ID of the object.
* \param[in] clear_func function to be run to free reference objects.
*
* return None
*/
extern void ia_css_refcount_clear(int32_t id,
clear_func clear_func_ptr);
/*! \brief Function to verify if object is valid
*
* \param[in] ptr Data of the object (ptr)
*
* - true, if valid
* - false, if invalid
*/
extern bool ia_css_refcount_is_valid(hrt_vaddress ptr);
#endif /* _IA_CSS_REFCOUNT_H_ */

281
drivers/staging/media/atomisp/pci/atomisp2/css2400/base/refcount/src/refcount.c
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@ -1,281 +0,0 @@
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#include "ia_css_refcount.h"
#include "memory_access/memory_access.h"
#include "sh_css_defs.h"
#include "platform_support.h"
#include "assert_support.h"
#include "ia_css_debug.h"
/* TODO: enable for other memory aswell
now only for hrt_vaddress */
struct ia_css_refcount_entry {
uint32_t count;
hrt_vaddress data;
int32_t id;
};
struct ia_css_refcount_list {
uint32_t size;
struct ia_css_refcount_entry *items;
};
static struct ia_css_refcount_list myrefcount;
static struct ia_css_refcount_entry *refcount_find_entry(hrt_vaddress ptr,
bool firstfree)
{
uint32_t i;
if (ptr == 0)
return NULL;
if (myrefcount.items == NULL) {
ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR,
"refcount_find_entry(): Ref count not initiliazed!\n");
return NULL;
}
for (i = 0; i < myrefcount.size; i++) {
if ((&myrefcount.items[i])->data == 0) {
if (firstfree) {
/* for new entry */
return &myrefcount.items[i];
}
}
if ((&myrefcount.items[i])->data == ptr) {
/* found entry */
return &myrefcount.items[i];
}
}
return NULL;
}
enum ia_css_err ia_css_refcount_init(uint32_t size)
{
enum ia_css_err err = IA_CSS_SUCCESS;
if (size == 0) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
"ia_css_refcount_init(): Size of 0 for Ref count init!\n");
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
if (myrefcount.items != NULL) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
"ia_css_refcount_init(): Ref count is already initialized\n");
return IA_CSS_ERR_INTERNAL_ERROR;
}
myrefcount.items =
sh_css_malloc(sizeof(struct ia_css_refcount_entry) * size);
if (!myrefcount.items)
err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY;
if (err == IA_CSS_SUCCESS) {
memset(myrefcount.items, 0,
sizeof(struct ia_css_refcount_entry) * size);
myrefcount.size = size;
}
return err;
}
void ia_css_refcount_uninit(void)
{
struct ia_css_refcount_entry *entry;
uint32_t i;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
"ia_css_refcount_uninit() entry\n");
for (i = 0; i < myrefcount.size; i++) {
/* driver verifier tool has issues with &arr[i]
and prefers arr + i; as these are actually equivalent
the line below uses + i
*/
entry = myrefcount.items + i;
if (entry->data != mmgr_NULL) {
/* ia_css_debug_dtrace(IA_CSS_DBG_TRACE,
"ia_css_refcount_uninit: freeing (%x)\n",
entry->data);*/
hmm_free(entry->data);
entry->data = mmgr_NULL;
entry->count = 0;
entry->id = 0;
}
}
sh_css_free(myrefcount.items);
myrefcount.items = NULL;
myrefcount.size = 0;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
"ia_css_refcount_uninit() leave\n");
}
hrt_vaddress ia_css_refcount_increment(int32_t id, hrt_vaddress ptr)
{
struct ia_css_refcount_entry *entry;
if (ptr == mmgr_NULL)
return ptr;
entry = refcount_find_entry(ptr, false);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
"ia_css_refcount_increment(%x) 0x%x\n", id, ptr);
if (!entry) {
entry = refcount_find_entry(ptr, true);
assert(entry != NULL);
if (entry == NULL)
return mmgr_NULL;
entry->id = id;
}
if (entry->id != id) {
ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR,
"ia_css_refcount_increment(): Ref count IDS do not match!\n");
return mmgr_NULL;
}
if (entry->data == ptr)
entry->count += 1;
else if (entry->data == mmgr_NULL) {
entry->data = ptr;
entry->count = 1;
} else
return mmgr_NULL;
return ptr;
}
bool ia_css_refcount_decrement(int32_t id, hrt_vaddress ptr)
{
struct ia_css_refcount_entry *entry;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
"ia_css_refcount_decrement(%x) 0x%x\n", id, ptr);
if (ptr == mmgr_NULL)
return false;
entry = refcount_find_entry(ptr, false);
if (entry) {
if (entry->id != id) {
ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR,
"ia_css_refcount_decrement(): Ref count IDS do not match!\n");
return false;
}
if (entry->count > 0) {
entry->count -= 1;
if (entry->count == 0) {
/* ia_css_debug_dtrace(IA_CSS_DBEUG_TRACE,
"ia_css_refcount_decrement: freeing\n");*/
hmm_free(ptr);
entry->data = mmgr_NULL;
entry->id = 0;
}
return true;
}
}
/* SHOULD NOT HAPPEN: ptr not managed by refcount, or not
valid anymore */
if (entry)
IA_CSS_ERROR("id %x, ptr 0x%x entry %p entry->id %x entry->count %d\n",
id, ptr, entry, entry->id, entry->count);
else
IA_CSS_ERROR("entry NULL\n");
#ifdef ISP2401
assert(false);
#endif
return false;
}
bool ia_css_refcount_is_single(hrt_vaddress ptr)
{
struct ia_css_refcount_entry *entry;
if (ptr == mmgr_NULL)
return false;
entry = refcount_find_entry(ptr, false);
if (entry)
return (entry->count == 1);
return true;
}
void ia_css_refcount_clear(int32_t id, clear_func clear_func_ptr)
{
struct ia_css_refcount_entry *entry;
uint32_t i;
uint32_t count = 0;
assert(clear_func_ptr != NULL);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_refcount_clear(%x)\n",
id);
for (i = 0; i < myrefcount.size; i++) {
/* driver verifier tool has issues with &arr[i]
and prefers arr + i; as these are actually equivalent
the line below uses + i
*/
entry = myrefcount.items + i;
if ((entry->data != mmgr_NULL) && (entry->id == id)) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
"ia_css_refcount_clear:"
" %x: 0x%x\n", id, entry->data);
if (clear_func_ptr) {
/* clear using provided function */
clear_func_ptr(entry->data);
} else {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
"ia_css_refcount_clear: "
"using hmm_free: "
"no clear_func\n");
hmm_free(entry->data);
}
#ifndef ISP2401
#else
assert(entry->count == 0);
#endif
if (entry->count != 0) {
IA_CSS_WARNING("Ref count for entry %x is not zero!", entry->id);
}
entry->data = mmgr_NULL;
entry->count = 0;
entry->id = 0;
count++;
}
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
"ia_css_refcount_clear(%x): cleared %d\n", id,
count);
}
bool ia_css_refcount_is_valid(hrt_vaddress ptr)
{
struct ia_css_refcount_entry *entry;
if (ptr == mmgr_NULL)
return false;
entry = refcount_find_entry(ptr, false);
return entry != NULL;
}

297
drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/pipe/interface/ia_css_pipe_binarydesc.h
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@ -1,297 +0,0 @@
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef __IA_CSS_PIPE_BINARYDESC_H__
#define __IA_CSS_PIPE_BINARYDESC_H__
#include <ia_css_types.h> /* ia_css_pipe */
#include <ia_css_frame_public.h> /* ia_css_frame_info */
#include <ia_css_binary.h> /* ia_css_binary_descr */
/* @brief Get a binary descriptor for copy.
*
* @param[in] pipe
* @param[out] copy_desc
* @param[in/out] in_info
* @param[in/out] out_info
* @param[in/out] vf_info
* @return None
*
*/
extern void ia_css_pipe_get_copy_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *copy_descr,
struct ia_css_frame_info *in_info,
struct ia_css_frame_info *out_info,
struct ia_css_frame_info *vf_info);
/* @brief Get a binary descriptor for vfpp.
*
* @param[in] pipe
* @param[out] vfpp_descr
* @param[in/out] in_info
* @param[in/out] out_info
* @return None
*
*/
extern void ia_css_pipe_get_vfpp_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *vf_pp_descr,
struct ia_css_frame_info *in_info,
struct ia_css_frame_info *out_info);
/* @brief Get numerator and denominator of bayer downscaling factor.
*
* @param[in] bds_factor: The bayer downscaling factor.
* (= The bds_factor member in the sh_css_bds_factor structure.)
* @param[out] bds_factor_numerator: The numerator of the bayer downscaling factor.
* (= The numerator member in the sh_css_bds_factor structure.)
* @param[out] bds_factor_denominator: The denominator of the bayer downscaling factor.
* (= The denominator member in the sh_css_bds_factor structure.)
* @return IA_CSS_SUCCESS or error code upon error.
*
*/
extern enum ia_css_err sh_css_bds_factor_get_numerator_denominator(
unsigned int bds_factor,
unsigned int *bds_factor_numerator,
unsigned int *bds_factor_denominator);
/* @brief Get a binary descriptor for preview stage.
*
* @param[in] pipe
* @param[out] preview_descr
* @param[in/out] in_info
* @param[in/out] bds_out_info
* @param[in/out] out_info
* @param[in/out] vf_info
* @return IA_CSS_SUCCESS or error code upon error.
*
*/
extern enum ia_css_err ia_css_pipe_get_preview_binarydesc(
struct ia_css_pipe * const pipe,
struct ia_css_binary_descr *preview_descr,
struct ia_css_frame_info *in_info,
struct ia_css_frame_info *bds_out_info,
struct ia_css_frame_info *out_info,
struct ia_css_frame_info *vf_info);
/* @brief Get a binary descriptor for video stage.
*
* @param[in/out] pipe
* @param[out] video_descr
* @param[in/out] in_info
* @param[in/out] bds_out_info
* @param[in/out] vf_info
* @return IA_CSS_SUCCESS or error code upon error.
*
*/
extern enum ia_css_err ia_css_pipe_get_video_binarydesc(
struct ia_css_pipe * const pipe,
struct ia_css_binary_descr *video_descr,
struct ia_css_frame_info *in_info,
struct ia_css_frame_info *bds_out_info,
struct ia_css_frame_info *out_info,
struct ia_css_frame_info *vf_info,
int stream_config_left_padding);
/* @brief Get a binary descriptor for yuv scaler stage.
*
* @param[in/out] pipe
* @param[out] yuv_scaler_descr
* @param[in/out] in_info
* @param[in/out] out_info
* @param[in/out] internal_out_info
* @param[in/out] vf_info
* @return None
*
*/
void ia_css_pipe_get_yuvscaler_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *yuv_scaler_descr,
struct ia_css_frame_info *in_info,
struct ia_css_frame_info *out_info,
struct ia_css_frame_info *internal_out_info,
struct ia_css_frame_info *vf_info);
/* @brief Get a binary descriptor for capture pp stage.
*
* @param[in/out] pipe
* @param[out] capture_pp_descr
* @param[in/out] in_info
* @param[in/out] vf_info
* @return None
*
*/
extern void ia_css_pipe_get_capturepp_binarydesc(
struct ia_css_pipe * const pipe,
struct ia_css_binary_descr *capture_pp_descr,
struct ia_css_frame_info *in_info,
struct ia_css_frame_info *out_info,
struct ia_css_frame_info *vf_info);
/* @brief Get a binary descriptor for primary capture.
*
* @param[in] pipe
* @param[out] prim_descr
* @param[in/out] in_info
* @param[in/out] out_info
* @param[in/out] vf_info
* @return None
*
*/
extern void ia_css_pipe_get_primary_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *prim_descr,
struct ia_css_frame_info *in_info,
struct ia_css_frame_info *out_info,
struct ia_css_frame_info *vf_info,
unsigned int stage_idx);
/* @brief Get a binary descriptor for pre gdc stage.
*
* @param[in] pipe
* @param[out] pre_gdc_descr
* @param[in/out] in_info
* @param[in/out] out_info
* @return None
*
*/
extern void ia_css_pipe_get_pre_gdc_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *gdc_descr,
struct ia_css_frame_info *in_info,
struct ia_css_frame_info *out_info);
/* @brief Get a binary descriptor for gdc stage.
*
* @param[in] pipe
* @param[out] gdc_descr
* @param[in/out] in_info
* @param[in/out] out_info
* @return None
*
*/
extern void ia_css_pipe_get_gdc_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *gdc_descr,
struct ia_css_frame_info *in_info,
struct ia_css_frame_info *out_info);
/* @brief Get a binary descriptor for post gdc.
*
* @param[in] pipe
* @param[out] post_gdc_descr
* @param[in/out] in_info
* @param[in/out] out_info
* @param[in/out] vf_info
* @return None
*
*/
extern void ia_css_pipe_get_post_gdc_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *post_gdc_descr,
struct ia_css_frame_info *in_info,
struct ia_css_frame_info *out_info,
struct ia_css_frame_info *vf_info);
/* @brief Get a binary descriptor for de.
*
* @param[in] pipe
* @param[out] pre_de_descr
* @param[in/out] in_info
* @param[in/out] out_info
* @return None
*
*/
extern void ia_css_pipe_get_pre_de_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *pre_de_descr,
struct ia_css_frame_info *in_info,
struct ia_css_frame_info *out_info);
/* @brief Get a binary descriptor for pre anr stage.
*
* @param[in] pipe
* @param[out] pre_anr_descr
* @param[in/out] in_info
* @param[in/out] out_info
* @return None
*
*/
extern void ia_css_pipe_get_pre_anr_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *pre_anr_descr,
struct ia_css_frame_info *in_info,
struct ia_css_frame_info *out_info);
/* @brief Get a binary descriptor for ANR stage.
*
* @param[in] pipe
* @param[out] anr_descr
* @param[in/out] in_info
* @param[in/out] out_info
* @return None
*
*/
extern void ia_css_pipe_get_anr_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *anr_descr,
struct ia_css_frame_info *in_info,
struct ia_css_frame_info *out_info);
/* @brief Get a binary descriptor for post anr stage.
*
* @param[in] pipe
* @param[out] post_anr_descr
* @param[in/out] in_info
* @param[in/out] out_info
* @param[in/out] vf_info
* @return None
*
*/
extern void ia_css_pipe_get_post_anr_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *post_anr_descr,
struct ia_css_frame_info *in_info,
struct ia_css_frame_info *out_info,
struct ia_css_frame_info *vf_info);
/* @brief Get a binary descriptor for ldc stage.
*
* @param[in/out] pipe
* @param[out] capture_pp_descr
* @param[in/out] in_info
* @param[in/out] vf_info
* @return None
*
*/
extern void ia_css_pipe_get_ldc_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *ldc_descr,
struct ia_css_frame_info *in_info,
struct ia_css_frame_info *out_info);
/* @brief Calculates the required BDS factor
*
* @param[in] input_res
* @param[in] output_res
* @param[in/out] bds_factor
* @return IA_CSS_SUCCESS or error code upon error.
*/
enum ia_css_err binarydesc_calculate_bds_factor(
struct ia_css_resolution input_res,
struct ia_css_resolution output_res,
unsigned int *bds_factor);
#endif /* __IA_CSS_PIPE_BINARYDESC_H__ */

52
drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/pipe/interface/ia_css_pipe_stagedesc.h
View File

@ -1,52 +0,0 @@
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef __IA_CSS_PIPE_STAGEDESC_H__
#define __IA_CSS_PIPE_STAGEDESC_H__
#include <ia_css_acc_types.h> /* ia_css_fw_info */
#include <ia_css_frame_public.h>
#include <ia_css_binary.h>
#include "ia_css_pipeline.h"
#include "ia_css_pipeline_common.h"
extern void ia_css_pipe_get_generic_stage_desc(
struct ia_css_pipeline_stage_desc *stage_desc,
struct ia_css_binary *binary,
struct ia_css_frame *out_frame[],
struct ia_css_frame *in_frame,
struct ia_css_frame *vf_frame);
extern void ia_css_pipe_get_firmwares_stage_desc(
struct ia_css_pipeline_stage_desc *stage_desc,
struct ia_css_binary *binary,
struct ia_css_frame *out_frame[],
struct ia_css_frame *in_frame,
struct ia_css_frame *vf_frame,
const struct ia_css_fw_info *fw,
unsigned int mode);
extern void ia_css_pipe_get_acc_stage_desc(
struct ia_css_pipeline_stage_desc *stage_desc,
struct ia_css_binary *binary,
struct ia_css_fw_info *fw);
extern void ia_css_pipe_get_sp_func_stage_desc(
struct ia_css_pipeline_stage_desc *stage_desc,
struct ia_css_frame *out_frame,
enum ia_css_pipeline_stage_sp_func sp_func,
unsigned max_input_width);
#endif /*__IA_CSS_PIPE_STAGEDESC__H__ */

39
drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/pipe/interface/ia_css_pipe_util.h
View File

@ -1,39 +0,0 @@
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef __IA_CSS_PIPE_UTIL_H__
#define __IA_CSS_PIPE_UTIL_H__
#include <ia_css_types.h>
#include <ia_css_frame_public.h>
/* @brief Get Input format bits per pixel based on stream configuration of this
* pipe.
*
* @param[in] pipe
* @return bits per pixel for the underlying stream
*
*/
extern unsigned int ia_css_pipe_util_pipe_input_format_bpp(
const struct ia_css_pipe * const pipe);
extern void ia_css_pipe_util_create_output_frames(
struct ia_css_frame *frames[]);
extern void ia_css_pipe_util_set_output_frames(
struct ia_css_frame *frames[],
unsigned int idx,
struct ia_css_frame *frame);
#endif /* __IA_CSS_PIPE_UTIL_H__ */

880
drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/pipe/src/pipe_binarydesc.c
View File

@ -1,880 +0,0 @@
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#include "ia_css_pipe_binarydesc.h"
#include "ia_css_frame_format.h"
#include "ia_css_pipe.h"
#include "ia_css_pipe_util.h"
#include "ia_css_util.h"
#include "ia_css_debug.h"
#include "sh_css_params.h"
#include <assert_support.h>
/* HRT_GDC_N */
#include "gdc_device.h"
#include <linux/kernel.h>
/* This module provides a binary descriptions to used to find a binary. Since,
* every stage is associated with a binary, it implicity helps stage
* description. Apart from providing a binary description, this module also
* populates the frame info's when required.*/
/* Generic descriptor for offline binaries. Internal function. */
static void pipe_binarydesc_get_offline(
struct ia_css_pipe const * const pipe,
const int mode,
struct ia_css_binary_descr *descr,
struct ia_css_frame_info *in_info,
struct ia_css_frame_info *out_info[],
struct ia_css_frame_info *vf_info)
{
unsigned int i;
/* in_info, out_info, vf_info can be NULL */
assert(pipe != NULL);
assert(descr != NULL);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE,
"pipe_binarydesc_get_offline() enter:\n");
descr->mode = mode;
descr->online = false;
descr->continuous = pipe->stream->config.continuous;
descr->striped = false;
descr->two_ppc = false;
descr->enable_yuv_ds = false;
descr->enable_high_speed = false;
descr->enable_dvs_6axis = false;
descr->enable_reduced_pipe = false;
descr->enable_dz = true;
descr->enable_xnr = false;
descr->enable_dpc = false;
#ifdef ISP2401
descr->enable_luma_only = false;
descr->enable_tnr = false;
#endif
descr->enable_capture_pp_bli = false;
descr->enable_fractional_ds = false;
descr->dvs_env.width = 0;
descr->dvs_env.height = 0;
descr->stream_format = pipe->stream->config.input_config.format;
descr->in_info = in_info;
descr->bds_out_info = NULL;
for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++)
descr->out_info[i] = out_info[i];
descr->vf_info = vf_info;
descr->isp_pipe_version = pipe->config.isp_pipe_version;
descr->required_bds_factor = SH_CSS_BDS_FACTOR_1_00;
descr->stream_config_left_padding = -1;
}
void ia_css_pipe_get_copy_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *copy_descr,
struct ia_css_frame_info *in_info,
struct ia_css_frame_info *out_info,
struct ia_css_frame_info *vf_info)
{
struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
unsigned int i;
/* out_info can be NULL */
assert(pipe != NULL);
assert(in_info != NULL);
IA_CSS_ENTER_PRIVATE("");
*in_info = *out_info;
out_infos[0] = out_info;
for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++)
out_infos[i] = NULL;
pipe_binarydesc_get_offline(pipe, IA_CSS_BINARY_MODE_COPY,
copy_descr, in_info, out_infos, vf_info);
copy_descr->online = true;
copy_descr->continuous = false;
copy_descr->two_ppc = (pipe->stream->config.pixels_per_clock == 2);
copy_descr->enable_dz = false;
copy_descr->isp_pipe_version = IA_CSS_PIPE_VERSION_1;
IA_CSS_LEAVE_PRIVATE("");
}
void ia_css_pipe_get_vfpp_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *vf_pp_descr,
struct ia_css_frame_info *in_info,
struct ia_css_frame_info *out_info)
{
struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
unsigned int i;
/* out_info can be NULL ??? */
assert(pipe != NULL);
assert(in_info != NULL);
IA_CSS_ENTER_PRIVATE("");
in_info->raw_bit_depth = 0;
out_infos[0] = out_info;
for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++)
out_infos[i] = NULL;
pipe_binarydesc_get_offline(pipe, IA_CSS_BINARY_MODE_VF_PP,
vf_pp_descr, in_info, out_infos, NULL);
vf_pp_descr->enable_fractional_ds = true;
IA_CSS_LEAVE_PRIVATE("");
}
static struct sh_css_bds_factor bds_factors_list[] = {
{1, 1, SH_CSS_BDS_FACTOR_1_00},
{5, 4, SH_CSS_BDS_FACTOR_1_25},
{3, 2, SH_CSS_BDS_FACTOR_1_50},
{2, 1, SH_CSS_BDS_FACTOR_2_00},
{9, 4, SH_CSS_BDS_FACTOR_2_25},
{5, 2, SH_CSS_BDS_FACTOR_2_50},
{3, 1, SH_CSS_BDS_FACTOR_3_00},
{4, 1, SH_CSS_BDS_FACTOR_4_00},
{9, 2, SH_CSS_BDS_FACTOR_4_50},
{5, 1, SH_CSS_BDS_FACTOR_5_00},
{6, 1, SH_CSS_BDS_FACTOR_6_00},
{8, 1, SH_CSS_BDS_FACTOR_8_00}
};
enum ia_css_err sh_css_bds_factor_get_numerator_denominator(
unsigned int bds_factor,
unsigned int *bds_factor_numerator,
unsigned int *bds_factor_denominator)
{
unsigned int i;
/* Loop over all bds factors until a match is found */
for (i = 0; i < ARRAY_SIZE(bds_factors_list); i++) {
if (bds_factors_list[i].bds_factor == bds_factor) {
*bds_factor_numerator = bds_factors_list[i].numerator;
*bds_factor_denominator = bds_factors_list[i].denominator;
return IA_CSS_SUCCESS;
}
}
/* Throw an error since bds_factor cannot be found
in bds_factors_list */
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
enum ia_css_err binarydesc_calculate_bds_factor(
struct ia_css_resolution input_res,
struct ia_css_resolution output_res,
unsigned int *bds_factor)
{
unsigned int i;
unsigned int in_w = input_res.width,
in_h = input_res.height,
out_w = output_res.width, out_h = output_res.height;
unsigned int max_bds_factor = 8;
unsigned int max_rounding_margin = 2;
/* delta in pixels to account for rounding margin in the calculation */
unsigned int delta = max_bds_factor * max_rounding_margin;
/* Assert if the resolutions are not set */
assert(in_w != 0 && in_h != 0);
assert(out_w != 0 && out_h != 0);
/* Loop over all bds factors until a match is found */
for (i = 0; i < ARRAY_SIZE(bds_factors_list); i++) {
unsigned num = bds_factors_list[i].numerator;
unsigned den = bds_factors_list[i].denominator;
/* See width-wise and height-wise if this bds_factor
* satisfies the condition */
bool cond = (out_w * num / den + delta > in_w) &&
(out_w * num / den <= in_w) &&
(out_h * num / den + delta > in_h) &&
(out_h * num / den <= in_h);
if (cond) {
*bds_factor = bds_factors_list[i].bds_factor;
return IA_CSS_SUCCESS;
}
}
/* Throw an error since a suitable bds_factor cannot be found */
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
enum ia_css_err ia_css_pipe_get_preview_binarydesc(
struct ia_css_pipe * const pipe,
struct ia_css_binary_descr *preview_descr,
struct ia_css_frame_info *in_info,
struct ia_css_frame_info *bds_out_info,
struct ia_css_frame_info *out_info,
struct ia_css_frame_info *vf_info)
{
enum ia_css_err err;
struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
int mode = IA_CSS_BINARY_MODE_PREVIEW;
unsigned int i;
assert(pipe != NULL);
assert(in_info != NULL);
assert(out_info != NULL);
assert(vf_info != NULL);
IA_CSS_ENTER_PRIVATE("");
/*
* Set up the info of the input frame with
* the ISP required resolution
*/
in_info->res = pipe->config.input_effective_res;
in_info->padded_width = in_info->res.width;
in_info->raw_bit_depth = ia_css_pipe_util_pipe_input_format_bpp(pipe);
if (ia_css_util_is_input_format_yuv(pipe->stream->config.input_config.format))
mode = IA_CSS_BINARY_MODE_COPY;
else
in_info->format = IA_CSS_FRAME_FORMAT_RAW;
out_infos[0] = out_info;
for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++)
out_infos[i] = NULL;
pipe_binarydesc_get_offline(pipe, mode,
preview_descr, in_info, out_infos, vf_info);
if (pipe->stream->config.online) {
preview_descr->online = pipe->stream->config.online;
preview_descr->two_ppc =
(pipe->stream->config.pixels_per_clock == 2);
}
preview_descr->stream_format = pipe->stream->config.input_config.format;
/* TODO: Remove this when bds_out_info is available! */
*bds_out_info = *in_info;
if (pipe->extra_config.enable_raw_binning) {
if (pipe->config.bayer_ds_out_res.width != 0 &&
pipe->config.bayer_ds_out_res.height != 0) {
bds_out_info->res.width =
pipe->config.bayer_ds_out_res.width;
bds_out_info->res.height =
pipe->config.bayer_ds_out_res.height;
bds_out_info->padded_width =
pipe->config.bayer_ds_out_res.width;
err =
binarydesc_calculate_bds_factor(in_info->res,
bds_out_info->res,
&preview_descr->required_bds_factor);
if (err != IA_CSS_SUCCESS)
return err;
} else {
bds_out_info->res.width = in_info->res.width / 2;
bds_out_info->res.height = in_info->res.height / 2;
bds_out_info->padded_width = in_info->padded_width / 2;
preview_descr->required_bds_factor =
SH_CSS_BDS_FACTOR_2_00;
}
} else {
/* TODO: Remove this when bds_out_info->is available! */
bds_out_info->res.width = in_info->res.width;
bds_out_info->res.height = in_info->res.height;
bds_out_info->padded_width = in_info->padded_width;
preview_descr->required_bds_factor = SH_CSS_BDS_FACTOR_1_00;
}
pipe->required_bds_factor = preview_descr->required_bds_factor;
/* bayer ds and fractional ds cannot be enabled at the same time,
so we disable bds_out_info when fractional ds is used */
if (!pipe->extra_config.enable_fractional_ds)
preview_descr->bds_out_info = bds_out_info;
else
preview_descr->bds_out_info = NULL;
/*
----Preview binary-----
--in-->|--out->|vf_veceven|--|--->vf
-----------------------
* Preview binary normally doesn't have a vf_port but
* instead it has an output port. However, the output is
* generated by vf_veceven module in which we might have
* a downscaling (by 1x, 2x, or 4x). Because the resolution
* might change, we need two different info, namely out_info
* & vf_info. In fill_binary_info we use out&vf info to
* calculate vf decimation factor.
*/
*out_info = *vf_info;
/* In case of preview_ds binary, we can do any fractional amount
* of downscale, so there is no DS needed in vf_veceven. Therefore,
* out and vf infos will be the same. Otherwise, we set out resolution
* equal to in resolution. */
if (!pipe->extra_config.enable_fractional_ds) {
/* TODO: Change this when bds_out_info is available! */
out_info->res.width = bds_out_info->res.width;
out_info->res.height = bds_out_info->res.height;
out_info->padded_width = bds_out_info->padded_width;
}
preview_descr->enable_fractional_ds =
pipe->extra_config.enable_fractional_ds;
preview_descr->enable_dpc = pipe->config.enable_dpc;
preview_descr->isp_pipe_version = pipe->config.isp_pipe_version;
IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_SUCCESS);
return IA_CSS_SUCCESS;
}
enum ia_css_err ia_css_pipe_get_video_binarydesc(
struct ia_css_pipe * const pipe,
struct ia_css_binary_descr *video_descr,
struct ia_css_frame_info *in_info,
struct ia_css_frame_info *bds_out_info,
struct ia_css_frame_info *out_info,
struct ia_css_frame_info *vf_info,
int stream_config_left_padding)
{
int mode = IA_CSS_BINARY_MODE_VIDEO;
unsigned int i;
struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
enum ia_css_err err = IA_CSS_SUCCESS;
bool stream_dz_config = false;
/* vf_info can be NULL */
assert(pipe != NULL);
assert(in_info != NULL);
/* assert(vf_info != NULL); */
IA_CSS_ENTER_PRIVATE("");
/* The solution below is not optimal; we should move to using ia_css_pipe_get_copy_binarydesc()
* But for now this fixes things; this code used to be there but was removed
* with gerrit 8908 as this was wrong for Skycam; however 240x still needs this
*/
if (ia_css_util_is_input_format_yuv(pipe->stream->config.input_config.format))
mode = IA_CSS_BINARY_MODE_COPY;
in_info->res = pipe->config.input_effective_res;
in_info->padded_width = in_info->res.width;
in_info->format = IA_CSS_FRAME_FORMAT_RAW;
in_info->raw_bit_depth = ia_css_pipe_util_pipe_input_format_bpp(pipe);
out_infos[0] = out_info;
for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++)
out_infos[i] = NULL;
pipe_binarydesc_get_offline(pipe, mode,
video_descr, in_info, out_infos, vf_info);
if (pipe->stream->config.online) {
video_descr->online = pipe->stream->config.online;
video_descr->two_ppc =
(pipe->stream->config.pixels_per_clock == 2);
}
if (mode == IA_CSS_BINARY_MODE_VIDEO) {
stream_dz_config =
((pipe->stream->isp_params_configs->dz_config.dx !=
HRT_GDC_N)
|| (pipe->stream->isp_params_configs->dz_config.dy !=
HRT_GDC_N));
video_descr->enable_dz = pipe->config.enable_dz
|| stream_dz_config;
video_descr->dvs_env = pipe->config.dvs_envelope;
video_descr->enable_yuv_ds = pipe->extra_config.enable_yuv_ds;
video_descr->enable_high_speed =
pipe->extra_config.enable_high_speed;
video_descr->enable_dvs_6axis =
pipe->extra_config.enable_dvs_6axis;
video_descr->enable_reduced_pipe =
pipe->extra_config.enable_reduced_pipe;
video_descr->isp_pipe_version = pipe->config.isp_pipe_version;
video_descr->enable_fractional_ds =
pipe->extra_config.enable_fractional_ds;
video_descr->enable_dpc =
pipe->config.enable_dpc;
#ifdef ISP2401
video_descr->enable_luma_only =
pipe->config.enable_luma_only;
video_descr->enable_tnr =
pipe->config.enable_tnr;
#endif
if (pipe->extra_config.enable_raw_binning) {
if (pipe->config.bayer_ds_out_res.width != 0 &&
pipe->config.bayer_ds_out_res.height != 0) {
bds_out_info->res.width =
pipe->config.bayer_ds_out_res.width;
bds_out_info->res.height =
pipe->config.bayer_ds_out_res.height;
bds_out_info->padded_width =
pipe->config.bayer_ds_out_res.width;
err =
binarydesc_calculate_bds_factor(
in_info->res, bds_out_info->res,
&video_descr->required_bds_factor);
if (err != IA_CSS_SUCCESS)
return err;
} else {
bds_out_info->res.width =
in_info->res.width / 2;
bds_out_info->res.height =
in_info->res.height / 2;
bds_out_info->padded_width =
in_info->padded_width / 2;
video_descr->required_bds_factor =
SH_CSS_BDS_FACTOR_2_00;
}
} else {
bds_out_info->res.width = in_info->res.width;
bds_out_info->res.height = in_info->res.height;
bds_out_info->padded_width = in_info->padded_width;
video_descr->required_bds_factor =
SH_CSS_BDS_FACTOR_1_00;
}
pipe->required_bds_factor = video_descr->required_bds_factor;
/* bayer ds and fractional ds cannot be enabled
at the same time, so we disable bds_out_info when
fractional ds is used */
if (!pipe->extra_config.enable_fractional_ds)
video_descr->bds_out_info = bds_out_info;
else
video_descr->bds_out_info = NULL;
video_descr->enable_fractional_ds =
pipe->extra_config.enable_fractional_ds;
video_descr->stream_config_left_padding = stream_config_left_padding;
}
IA_CSS_LEAVE_ERR_PRIVATE(err);
return err;
}
void ia_css_pipe_get_yuvscaler_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *yuv_scaler_descr,
struct ia_css_frame_info *in_info,
struct ia_css_frame_info *out_info,
struct ia_css_frame_info *internal_out_info,
struct ia_css_frame_info *vf_info)
{
struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
struct ia_css_frame_info *this_vf_info = NULL;
assert(pipe != NULL);
assert(in_info != NULL);
/* Note: if the following assert fails, the number of ports has been
* changed; in that case an additional initializer must be added
* a few lines below after which this assert can be updated.
*/
assert(IA_CSS_BINARY_MAX_OUTPUT_PORTS == 2);
IA_CSS_ENTER_PRIVATE("");
in_info->padded_width = in_info->res.width;
in_info->raw_bit_depth = 0;
ia_css_frame_info_set_width(in_info, in_info->res.width, 0);
out_infos[0] = out_info;
out_infos[1] = internal_out_info;
/* add initializers here if
* assert(IA_CSS_BINARY_MAX_OUTPUT_PORTS == ...);
* fails
*/
if (vf_info) {
this_vf_info = (vf_info->res.width == 0 &&
vf_info->res.height == 0) ? NULL : vf_info;
}
pipe_binarydesc_get_offline(pipe,
IA_CSS_BINARY_MODE_CAPTURE_PP,
yuv_scaler_descr,
in_info, out_infos, this_vf_info);
yuv_scaler_descr->enable_fractional_ds = true;
IA_CSS_LEAVE_PRIVATE("");
}
void ia_css_pipe_get_capturepp_binarydesc(
struct ia_css_pipe * const pipe,
struct ia_css_binary_descr *capture_pp_descr,
struct ia_css_frame_info *in_info,
struct ia_css_frame_info *out_info,
struct ia_css_frame_info *vf_info)
{
unsigned int i;
struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
assert(pipe != NULL);
assert(in_info != NULL);
assert(vf_info != NULL);
IA_CSS_ENTER_PRIVATE("");
/* the in_info is only used for resolution to enable
bayer down scaling. */
if (pipe->out_yuv_ds_input_info.res.width)
*in_info = pipe->out_yuv_ds_input_info;
else
*in_info = *out_info;
in_info->format = IA_CSS_FRAME_FORMAT_YUV420;
in_info->raw_bit_depth = 0;
ia_css_frame_info_set_width(in_info, in_info->res.width, 0);
out_infos[0] = out_info;
for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++)
out_infos[i] = NULL;
pipe_binarydesc_get_offline(pipe,
IA_CSS_BINARY_MODE_CAPTURE_PP,
capture_pp_descr,
in_info, out_infos, vf_info);
capture_pp_descr->enable_capture_pp_bli =
pipe->config.default_capture_config.enable_capture_pp_bli;
capture_pp_descr->enable_fractional_ds = true;
capture_pp_descr->enable_xnr =
pipe->config.default_capture_config.enable_xnr != 0;
IA_CSS_LEAVE_PRIVATE("");
}
/* lookup table for high quality primary binaries */
static unsigned int primary_hq_binary_modes[NUM_PRIMARY_HQ_STAGES] =
{
IA_CSS_BINARY_MODE_PRIMARY_HQ_STAGE0,
IA_CSS_BINARY_MODE_PRIMARY_HQ_STAGE1,
IA_CSS_BINARY_MODE_PRIMARY_HQ_STAGE2,
IA_CSS_BINARY_MODE_PRIMARY_HQ_STAGE3,
IA_CSS_BINARY_MODE_PRIMARY_HQ_STAGE4,
IA_CSS_BINARY_MODE_PRIMARY_HQ_STAGE5
};
void ia_css_pipe_get_primary_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *prim_descr,
struct ia_css_frame_info *in_info,
struct ia_css_frame_info *out_info,
struct ia_css_frame_info *vf_info,
unsigned int stage_idx)
{
enum ia_css_pipe_version pipe_version = pipe->config.isp_pipe_version;
int mode;
unsigned int i;
struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
assert(pipe != NULL);
assert(in_info != NULL);
assert(out_info != NULL);
assert(stage_idx < NUM_PRIMARY_HQ_STAGES);
/* vf_info can be NULL - example video_binarydescr */
/*assert(vf_info != NULL);*/
IA_CSS_ENTER_PRIVATE("");
if (pipe_version == IA_CSS_PIPE_VERSION_2_6_1)
mode = primary_hq_binary_modes[stage_idx];
else
mode = IA_CSS_BINARY_MODE_PRIMARY;
if (ia_css_util_is_input_format_yuv(pipe->stream->config.input_config.format))
mode = IA_CSS_BINARY_MODE_COPY;
in_info->res = pipe->config.input_effective_res;
in_info->padded_width = in_info->res.width;
#if !defined(HAS_NO_PACKED_RAW_PIXELS)
if (pipe->stream->config.pack_raw_pixels)
in_info->format = IA_CSS_FRAME_FORMAT_RAW_PACKED;
else
#endif
in_info->format = IA_CSS_FRAME_FORMAT_RAW;
in_info->raw_bit_depth = ia_css_pipe_util_pipe_input_format_bpp(pipe);
out_infos[0] = out_info;
for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++)
out_infos[i] = NULL;
pipe_binarydesc_get_offline(pipe, mode,
prim_descr, in_info, out_infos, vf_info);
if (pipe->stream->config.online &&
pipe->stream->config.mode != IA_CSS_INPUT_MODE_MEMORY) {
prim_descr->online = true;
prim_descr->two_ppc =
(pipe->stream->config.pixels_per_clock == 2);
prim_descr->stream_format = pipe->stream->config.input_config.format;
}
if (mode == IA_CSS_BINARY_MODE_PRIMARY) {
prim_descr->isp_pipe_version = pipe->config.isp_pipe_version;
prim_descr->enable_fractional_ds =
pipe->extra_config.enable_fractional_ds;
#ifdef ISP2401
prim_descr->enable_luma_only =
pipe->config.enable_luma_only;
#endif
/* We have both striped and non-striped primary binaries,
* if continuous viewfinder is required, then we must select
* a striped one. Otherwise we prefer to use a non-striped
* since it has better performance. */
if (pipe_version == IA_CSS_PIPE_VERSION_2_6_1)
prim_descr->striped = false;
else
#ifndef ISP2401
prim_descr->striped = prim_descr->continuous && (!pipe->stream->stop_copy_preview || !pipe->stream->disable_cont_vf);
#else
prim_descr->striped = prim_descr->continuous && !pipe->stream->disable_cont_vf;
if ((pipe->config.default_capture_config.enable_xnr != 0) &&
(pipe->extra_config.enable_dvs_6axis == true))
prim_descr->enable_xnr = true;
#endif
}
IA_CSS_LEAVE_PRIVATE("");
}
void ia_css_pipe_get_pre_gdc_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *pre_gdc_descr,
struct ia_css_frame_info *in_info,
struct ia_css_frame_info *out_info)
{
unsigned int i;
struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
assert(pipe != NULL);
assert(in_info != NULL);
assert(out_info != NULL);
IA_CSS_ENTER_PRIVATE("");
*in_info = *out_info;
in_info->format = IA_CSS_FRAME_FORMAT_RAW;
in_info->raw_bit_depth = ia_css_pipe_util_pipe_input_format_bpp(pipe);
out_infos[0] = out_info;
for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++)
out_infos[i] = NULL;
pipe_binarydesc_get_offline(pipe, IA_CSS_BINARY_MODE_PRE_ISP,
pre_gdc_descr, in_info, out_infos, NULL);
pre_gdc_descr->isp_pipe_version = pipe->config.isp_pipe_version;
IA_CSS_LEAVE_PRIVATE("");
}
void ia_css_pipe_get_gdc_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *gdc_descr,
struct ia_css_frame_info *in_info,
struct ia_css_frame_info *out_info)
{
unsigned int i;
struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
assert(pipe != NULL);
assert(in_info != NULL);
assert(out_info != NULL);
IA_CSS_ENTER_PRIVATE("");
*in_info = *out_info;
in_info->format = IA_CSS_FRAME_FORMAT_QPLANE6;
out_infos[0] = out_info;
for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++)
out_infos[i] = NULL;
pipe_binarydesc_get_offline(pipe, IA_CSS_BINARY_MODE_GDC,
gdc_descr, in_info, out_infos, NULL);
IA_CSS_LEAVE_PRIVATE("");
}
void ia_css_pipe_get_post_gdc_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *post_gdc_descr,
struct ia_css_frame_info *in_info,
struct ia_css_frame_info *out_info,
struct ia_css_frame_info *vf_info)
{
unsigned int i;
struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
assert(pipe != NULL);
assert(in_info != NULL);
assert(out_info != NULL);
assert(vf_info != NULL);
IA_CSS_ENTER_PRIVATE("");
*in_info = *out_info;
in_info->format = IA_CSS_FRAME_FORMAT_YUV420_16;
in_info->raw_bit_depth = 16;
out_infos[0] = out_info;
for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++)
out_infos[i] = NULL;
pipe_binarydesc_get_offline(pipe, IA_CSS_BINARY_MODE_POST_ISP,
post_gdc_descr, in_info, out_infos, vf_info);
post_gdc_descr->isp_pipe_version = pipe->config.isp_pipe_version;
IA_CSS_LEAVE_PRIVATE("");
}
void ia_css_pipe_get_pre_de_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *pre_de_descr,
struct ia_css_frame_info *in_info,
struct ia_css_frame_info *out_info)
{
unsigned int i;
struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
assert(pipe != NULL);
assert(in_info != NULL);
assert(out_info != NULL);
IA_CSS_ENTER_PRIVATE("");
*in_info = *out_info;
in_info->format = IA_CSS_FRAME_FORMAT_RAW;
in_info->raw_bit_depth = ia_css_pipe_util_pipe_input_format_bpp(pipe);
out_infos[0] = out_info;
for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++)
out_infos[i] = NULL;
if (pipe->config.isp_pipe_version == IA_CSS_PIPE_VERSION_1)
pipe_binarydesc_get_offline(pipe, IA_CSS_BINARY_MODE_PRE_ISP,
pre_de_descr, in_info, out_infos, NULL);
else if (pipe->config.isp_pipe_version == IA_CSS_PIPE_VERSION_2_2) {
pipe_binarydesc_get_offline(pipe, IA_CSS_BINARY_MODE_PRE_DE,
pre_de_descr, in_info, out_infos, NULL);
}
if (pipe->stream->config.online) {
pre_de_descr->online = true;
pre_de_descr->two_ppc =
(pipe->stream->config.pixels_per_clock == 2);
pre_de_descr->stream_format = pipe->stream->config.input_config.format;
}
pre_de_descr->isp_pipe_version = pipe->config.isp_pipe_version;
IA_CSS_LEAVE_PRIVATE("");
}
void ia_css_pipe_get_pre_anr_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *pre_anr_descr,
struct ia_css_frame_info *in_info,
struct ia_css_frame_info *out_info)
{
unsigned int i;
struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
assert(pipe != NULL);
assert(in_info != NULL);
assert(out_info != NULL);
IA_CSS_ENTER_PRIVATE("");
*in_info = *out_info;
in_info->format = IA_CSS_FRAME_FORMAT_RAW;
in_info->raw_bit_depth = ia_css_pipe_util_pipe_input_format_bpp(pipe);
out_infos[0] = out_info;
for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++)
out_infos[i] = NULL;
pipe_binarydesc_get_offline(pipe, IA_CSS_BINARY_MODE_PRE_ISP,
pre_anr_descr, in_info, out_infos, NULL);
if (pipe->stream->config.online) {
pre_anr_descr->online = true;
pre_anr_descr->two_ppc =
(pipe->stream->config.pixels_per_clock == 2);
pre_anr_descr->stream_format = pipe->stream->config.input_config.format;
}
pre_anr_descr->isp_pipe_version = pipe->config.isp_pipe_version;
IA_CSS_LEAVE_PRIVATE("");
}
void ia_css_pipe_get_anr_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *anr_descr,
struct ia_css_frame_info *in_info,
struct ia_css_frame_info *out_info)
{
unsigned int i;
struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
assert(pipe != NULL);
assert(in_info != NULL);
assert(out_info != NULL);
IA_CSS_ENTER_PRIVATE("");
*in_info = *out_info;
in_info->format = IA_CSS_FRAME_FORMAT_RAW;
in_info->raw_bit_depth = ANR_ELEMENT_BITS;
out_infos[0] = out_info;
for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++)
out_infos[i] = NULL;
pipe_binarydesc_get_offline(pipe, IA_CSS_BINARY_MODE_ANR,
anr_descr, in_info, out_infos, NULL);
anr_descr->isp_pipe_version = pipe->config.isp_pipe_version;
IA_CSS_LEAVE_PRIVATE("");
}
void ia_css_pipe_get_post_anr_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *post_anr_descr,
struct ia_css_frame_info *in_info,
struct ia_css_frame_info *out_info,
struct ia_css_frame_info *vf_info)
{
unsigned int i;
struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
assert(pipe != NULL);
assert(in_info != NULL);
assert(out_info != NULL);
assert(vf_info != NULL);
IA_CSS_ENTER_PRIVATE("");
*in_info = *out_info;
in_info->format = IA_CSS_FRAME_FORMAT_RAW;
in_info->raw_bit_depth = ANR_ELEMENT_BITS;
out_infos[0] = out_info;
for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++)
out_infos[i] = NULL;
pipe_binarydesc_get_offline(pipe, IA_CSS_BINARY_MODE_POST_ISP,
post_anr_descr, in_info, out_infos, vf_info);
post_anr_descr->isp_pipe_version = pipe->config.isp_pipe_version;
IA_CSS_LEAVE_PRIVATE("");
}
void ia_css_pipe_get_ldc_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *ldc_descr,
struct ia_css_frame_info *in_info,
struct ia_css_frame_info *out_info)
{
unsigned int i;
struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
assert(pipe != NULL);
assert(in_info != NULL);
assert(out_info != NULL);
IA_CSS_ENTER_PRIVATE("");
#ifndef ISP2401
*in_info = *out_info;
#else
if (pipe->out_yuv_ds_input_info.res.width)
*in_info = pipe->out_yuv_ds_input_info;
else
*in_info = *out_info;
#endif
in_info->format = IA_CSS_FRAME_FORMAT_YUV420;
in_info->raw_bit_depth = 0;
ia_css_frame_info_set_width(in_info, in_info->res.width, 0);
out_infos[0] = out_info;
for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++)
out_infos[i] = NULL;
pipe_binarydesc_get_offline(pipe, IA_CSS_BINARY_MODE_CAPTURE_PP,
ldc_descr, in_info, out_infos, NULL);
ldc_descr->enable_dvs_6axis =
pipe->extra_config.enable_dvs_6axis;
IA_CSS_LEAVE_PRIVATE("");
}

115
drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/pipe/src/pipe_stagedesc.c
View File

@ -1,115 +0,0 @@
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#include "ia_css_pipe_stagedesc.h"
#include "assert_support.h"
#include "ia_css_debug.h"
void ia_css_pipe_get_generic_stage_desc(
struct ia_css_pipeline_stage_desc *stage_desc,
struct ia_css_binary *binary,
struct ia_css_frame *out_frame[],
struct ia_css_frame *in_frame,
struct ia_css_frame *vf_frame)
{
unsigned int i;
IA_CSS_ENTER_PRIVATE("stage_desc = %p, binary = %p, out_frame = %p, in_frame = %p, vf_frame = %p",
stage_desc, binary, out_frame, in_frame, vf_frame);
assert(stage_desc != NULL && binary != NULL && binary->info != NULL);
if (stage_desc == NULL || binary == NULL || binary->info == NULL) {
IA_CSS_ERROR("invalid arguments");
goto ERR;
}
stage_desc->binary = binary;
stage_desc->firmware = NULL;
stage_desc->sp_func = IA_CSS_PIPELINE_NO_FUNC;
stage_desc->max_input_width = 0;
stage_desc->mode = binary->info->sp.pipeline.mode;
stage_desc->in_frame = in_frame;
for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) {
stage_desc->out_frame[i] = out_frame[i];
}
stage_desc->vf_frame = vf_frame;
ERR:
IA_CSS_LEAVE_PRIVATE("");
}
void ia_css_pipe_get_firmwares_stage_desc(
struct ia_css_pipeline_stage_desc *stage_desc,
struct ia_css_binary *binary,
struct ia_css_frame *out_frame[],
struct ia_css_frame *in_frame,
struct ia_css_frame *vf_frame,
const struct ia_css_fw_info *fw,
unsigned int mode)
{
unsigned int i;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_pipe_get_firmwares_stage_desc() enter:\n");
stage_desc->binary = binary;
stage_desc->firmware = fw;
stage_desc->sp_func = IA_CSS_PIPELINE_NO_FUNC;
stage_desc->max_input_width = 0;
stage_desc->mode = mode;
stage_desc->in_frame = in_frame;
for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) {
stage_desc->out_frame[i] = out_frame[i];
}
stage_desc->vf_frame = vf_frame;
}
void ia_css_pipe_get_acc_stage_desc(
struct ia_css_pipeline_stage_desc *stage_desc,
struct ia_css_binary *binary,
struct ia_css_fw_info *fw)
{
unsigned int i;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_pipe_get_acc_stage_desc() enter:\n");
stage_desc->binary = binary;
stage_desc->firmware = fw;
stage_desc->sp_func = IA_CSS_PIPELINE_NO_FUNC;
stage_desc->max_input_width = 0;
stage_desc->mode = IA_CSS_BINARY_MODE_VF_PP;
stage_desc->in_frame = NULL;
for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) {
stage_desc->out_frame[i] = NULL;
}
stage_desc->vf_frame = NULL;
}
void ia_css_pipe_get_sp_func_stage_desc(
struct ia_css_pipeline_stage_desc *stage_desc,
struct ia_css_frame *out_frame,
enum ia_css_pipeline_stage_sp_func sp_func,
unsigned max_input_width)
{
unsigned int i;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_pipe_get_sp_func_stage_desc() enter:\n");
stage_desc->binary = NULL;
stage_desc->firmware = NULL;
stage_desc->sp_func = sp_func;
stage_desc->max_input_width = max_input_width;
stage_desc->mode = (unsigned int)-1;
stage_desc->in_frame = NULL;
stage_desc->out_frame[0] = out_frame;
for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) {
stage_desc->out_frame[i] = NULL;
}
stage_desc->vf_frame = NULL;
}

51
drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/pipe/src/pipe_util.c
View File

@ -1,51 +0,0 @@
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#include "ia_css_pipe_util.h"
#include "ia_css_frame_public.h"
#include "ia_css_pipe.h"
#include "ia_css_util.h"
#include "assert_support.h"
unsigned int ia_css_pipe_util_pipe_input_format_bpp(
const struct ia_css_pipe * const pipe)
{
assert(pipe != NULL);
assert(pipe->stream != NULL);
return ia_css_util_input_format_bpp(pipe->stream->config.input_config.format,
pipe->stream->config.pixels_per_clock == 2);
}
void ia_css_pipe_util_create_output_frames(
struct ia_css_frame *frames[])
{
unsigned int i;
assert(frames != NULL);
for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) {
frames[i] = NULL;
}
}
void ia_css_pipe_util_set_output_frames(
struct ia_css_frame *frames[],
unsigned int idx,
struct ia_css_frame *frame)
{
assert(idx < IA_CSS_BINARY_MAX_OUTPUT_PORTS);
frames[idx] = frame;
}

141
drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/util/interface/ia_css_util.h
View File

@ -1,141 +0,0 @@
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef __IA_CSS_UTIL_H__
#define __IA_CSS_UTIL_H__
#include <ia_css_err.h>
#include <error_support.h>
#include <type_support.h>
#include <ia_css_frame_public.h>
#include <ia_css_stream_public.h>
#include <ia_css_stream_format.h>
/* @brief convert "errno" error code to "ia_css_err" error code
*
* @param[in] "errno" error code
* @return "ia_css_err" error code
*
*/
enum ia_css_err ia_css_convert_errno(
int in_err);
/* @brief check vf frame info.
*
* @param[in] info
* @return IA_CSS_SUCCESS or error code upon error.
*
*/
extern enum ia_css_err ia_css_util_check_vf_info(
const struct ia_css_frame_info * const info);
/* @brief check input configuration.
*
* @param[in] stream_config
* @param[in] must_be_raw
* @return IA_CSS_SUCCESS or error code upon error.
*
*/
extern enum ia_css_err ia_css_util_check_input(
const struct ia_css_stream_config * const stream_config,
bool must_be_raw,
bool must_be_yuv);
/* @brief check vf and out frame info.
*
* @param[in] out_info
* @param[in] vf_info
* @return IA_CSS_SUCCESS or error code upon error.
*
*/
extern enum ia_css_err ia_css_util_check_vf_out_info(
const struct ia_css_frame_info * const out_info,
const struct ia_css_frame_info * const vf_info);
/* @brief check width and height
*
* @param[in] width
* @param[in] height
* @return IA_CSS_SUCCESS or error code upon error.
*
*/
extern enum ia_css_err ia_css_util_check_res(
unsigned int width,
unsigned int height);
#ifdef ISP2401
/* @brief compare resolutions (less or equal)
*
* @param[in] a resolution
* @param[in] b resolution
* @return true if both dimensions of a are less or
* equal than those of b, false otherwise
*
*/
extern bool ia_css_util_res_leq(
struct ia_css_resolution a,
struct ia_css_resolution b);
/**
* @brief Check if resolution is zero
*
* @param[in] resolution The resolution to check
*
* @returns true if resolution is zero
*/
extern bool ia_css_util_resolution_is_zero(
const struct ia_css_resolution resolution);
/**
* @brief Check if resolution is even
*
* @param[in] resolution The resolution to check
*
* @returns true if resolution is even
*/
extern bool ia_css_util_resolution_is_even(
const struct ia_css_resolution resolution);
#endif
/* @brief check width and height
*
* @param[in] stream_format
* @param[in] two_ppc
* @return bits per pixel based on given parameters.
*
*/
extern unsigned int ia_css_util_input_format_bpp(
enum atomisp_input_format stream_format,
bool two_ppc);
/* @brief check if input format it raw
*
* @param[in] stream_format
* @return true if the input format is raw or false otherwise
*
*/
extern bool ia_css_util_is_input_format_raw(
enum atomisp_input_format stream_format);
/* @brief check if input format it yuv
*
* @param[in] stream_format
* @return true if the input format is yuv or false otherwise
*
*/
extern bool ia_css_util_is_input_format_yuv(
enum atomisp_input_format stream_format);
#endif /* __IA_CSS_UTIL_H__ */

227
drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/util/src/util.c
View File

@ -1,227 +0,0 @@
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#include "ia_css_util.h"
#include <ia_css_frame.h>
#include <assert_support.h>
#include <math_support.h>
/* for ia_css_binary_max_vf_width() */
#include "ia_css_binary.h"
enum ia_css_err ia_css_convert_errno(
int in_err)
{
enum ia_css_err out_err;
switch (in_err) {
case 0:
out_err = IA_CSS_SUCCESS;
break;
case EINVAL:
out_err = IA_CSS_ERR_INVALID_ARGUMENTS;
break;
case ENODATA:
out_err = IA_CSS_ERR_QUEUE_IS_EMPTY;
break;
case ENOSYS:
case ENOTSUP:
out_err = IA_CSS_ERR_INTERNAL_ERROR;
break;
case ENOBUFS:
out_err = IA_CSS_ERR_QUEUE_IS_FULL;
break;
default:
out_err = IA_CSS_ERR_INTERNAL_ERROR;
break;
}
return out_err;
}
/* MW: Table look-up ??? */
unsigned int ia_css_util_input_format_bpp(
enum atomisp_input_format format,
bool two_ppc)
{
unsigned int rval = 0;
switch (format) {
case ATOMISP_INPUT_FORMAT_YUV420_8_LEGACY:
case ATOMISP_INPUT_FORMAT_YUV420_8:
case ATOMISP_INPUT_FORMAT_YUV422_8:
case ATOMISP_INPUT_FORMAT_RGB_888:
case ATOMISP_INPUT_FORMAT_RAW_8:
case ATOMISP_INPUT_FORMAT_BINARY_8:
case ATOMISP_INPUT_FORMAT_EMBEDDED:
rval = 8;
break;
case ATOMISP_INPUT_FORMAT_YUV420_10:
case ATOMISP_INPUT_FORMAT_YUV422_10:
case ATOMISP_INPUT_FORMAT_RAW_10:
rval = 10;
break;
case ATOMISP_INPUT_FORMAT_YUV420_16:
case ATOMISP_INPUT_FORMAT_YUV422_16:
rval = 16;
break;
case ATOMISP_INPUT_FORMAT_RGB_444:
rval = 4;
break;
case ATOMISP_INPUT_FORMAT_RGB_555:
rval = 5;
break;
case ATOMISP_INPUT_FORMAT_RGB_565:
rval = 65;
break;
case ATOMISP_INPUT_FORMAT_RGB_666:
case ATOMISP_INPUT_FORMAT_RAW_6:
rval = 6;
break;
case ATOMISP_INPUT_FORMAT_RAW_7:
rval = 7;
break;
case ATOMISP_INPUT_FORMAT_RAW_12:
rval = 12;
break;
case ATOMISP_INPUT_FORMAT_RAW_14:
if (two_ppc)
rval = 14;
else
rval = 12;
break;
case ATOMISP_INPUT_FORMAT_RAW_16:
if (two_ppc)
rval = 16;
else
rval = 12;
break;
default:
rval = 0;
break;
}
return rval;
}
enum ia_css_err ia_css_util_check_vf_info(
const struct ia_css_frame_info * const info)
{
enum ia_css_err err;
unsigned int max_vf_width;
assert(info != NULL);
err = ia_css_frame_check_info(info);
if (err != IA_CSS_SUCCESS)
return err;
max_vf_width = ia_css_binary_max_vf_width();
if (max_vf_width != 0 && info->res.width > max_vf_width*2)
return IA_CSS_ERR_INVALID_ARGUMENTS;
return IA_CSS_SUCCESS;
}
enum ia_css_err ia_css_util_check_vf_out_info(
const struct ia_css_frame_info * const out_info,
const struct ia_css_frame_info * const vf_info)
{
enum ia_css_err err;
assert(out_info != NULL);
assert(vf_info != NULL);
err = ia_css_frame_check_info(out_info);
if (err != IA_CSS_SUCCESS)
return err;
err = ia_css_util_check_vf_info(vf_info);
if (err != IA_CSS_SUCCESS)
return err;
return IA_CSS_SUCCESS;
}
enum ia_css_err ia_css_util_check_res(unsigned int width, unsigned int height)
{
/* height can be odd number for jpeg/embedded data from ISYS2401 */
if (((width == 0) ||
(height == 0) ||
IS_ODD(width))) {
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
return IA_CSS_SUCCESS;
}
#ifdef ISP2401
bool ia_css_util_res_leq(struct ia_css_resolution a, struct ia_css_resolution b)
{
return a.width <= b.width && a.height <= b.height;
}
bool ia_css_util_resolution_is_zero(const struct ia_css_resolution resolution)
{
return (resolution.width == 0) || (resolution.height == 0);
}
bool ia_css_util_resolution_is_even(const struct ia_css_resolution resolution)
{
return IS_EVEN(resolution.height) && IS_EVEN(resolution.width);
}
#endif
bool ia_css_util_is_input_format_raw(enum atomisp_input_format format)
{
return ((format == ATOMISP_INPUT_FORMAT_RAW_6) ||
(format == ATOMISP_INPUT_FORMAT_RAW_7) ||
(format == ATOMISP_INPUT_FORMAT_RAW_8) ||
(format == ATOMISP_INPUT_FORMAT_RAW_10) ||
(format == ATOMISP_INPUT_FORMAT_RAW_12));
/* raw_14 and raw_16 are not supported as input formats to the ISP.
* They can only be copied to a frame in memory using the
* copy binary.
*/
}
bool ia_css_util_is_input_format_yuv(enum atomisp_input_format format)
{
return format == ATOMISP_INPUT_FORMAT_YUV420_8_LEGACY ||
format == ATOMISP_INPUT_FORMAT_YUV420_8 ||
format == ATOMISP_INPUT_FORMAT_YUV420_10 ||
format == ATOMISP_INPUT_FORMAT_YUV420_16 ||
format == ATOMISP_INPUT_FORMAT_YUV422_8 ||
format == ATOMISP_INPUT_FORMAT_YUV422_10 ||
format == ATOMISP_INPUT_FORMAT_YUV422_16;
}
enum ia_css_err ia_css_util_check_input(
const struct ia_css_stream_config * const stream_config,
bool must_be_raw,
bool must_be_yuv)
{
assert(stream_config != NULL);
if (stream_config == NULL)
return IA_CSS_ERR_INVALID_ARGUMENTS;
#ifdef IS_ISP_2400_SYSTEM
if (stream_config->input_config.effective_res.width == 0 ||
stream_config->input_config.effective_res.height == 0)
return IA_CSS_ERR_INVALID_ARGUMENTS;
#endif
if (must_be_raw &&
!ia_css_util_is_input_format_raw(stream_config->input_config.format))
return IA_CSS_ERR_INVALID_ARGUMENTS;
if (must_be_yuv &&
!ia_css_util_is_input_format_yuv(stream_config->input_config.format))
return IA_CSS_ERR_INVALID_ARGUMENTS;
return IA_CSS_SUCCESS;
}

360
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hive_isp_css_2400_system_generated/ia_css_isp_configs.c
View File

@ -1,360 +0,0 @@
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
/* Generated code: do not edit or commmit. */
#define IA_CSS_INCLUDE_CONFIGURATIONS
#include "ia_css_pipeline.h"
#include "ia_css_isp_configs.h"
#include "ia_css_debug.h"
#include "assert_support.h"
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_iterator(
const struct ia_css_binary *binary,
const struct ia_css_iterator_configuration *config_dmem)
{
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_iterator() enter:\n");
{
unsigned offset = 0;
unsigned size = 0;
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.iterator.size;
offset = binary->info->mem_offsets.offsets.config->dmem.iterator.offset;
}
if (size) {
ia_css_iterator_config((struct sh_css_isp_iterator_isp_config *)
&binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset],
config_dmem, size); }
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_iterator() leave:\n");
}
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_copy_output(
const struct ia_css_binary *binary,
const struct ia_css_copy_output_configuration *config_dmem)
{
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_copy_output() enter:\n");
{
unsigned offset = 0;
unsigned size = 0;
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.copy_output.size;
offset = binary->info->mem_offsets.offsets.config->dmem.copy_output.offset;
}
if (size) {
ia_css_copy_output_config((struct sh_css_isp_copy_output_isp_config *)
&binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset],
config_dmem, size); }
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_copy_output() leave:\n");
}
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_crop(
const struct ia_css_binary *binary,
const struct ia_css_crop_configuration *config_dmem)
{
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_crop() enter:\n");
{
unsigned offset = 0;
unsigned size = 0;
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.crop.size;
offset = binary->info->mem_offsets.offsets.config->dmem.crop.offset;
}
if (size) {
ia_css_crop_config((struct sh_css_isp_crop_isp_config *)
&binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset],
config_dmem, size); }
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_crop() leave:\n");
}
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_fpn(
const struct ia_css_binary *binary,
const struct ia_css_fpn_configuration *config_dmem)
{
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_fpn() enter:\n");
{
unsigned offset = 0;
unsigned size = 0;
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.fpn.size;
offset = binary->info->mem_offsets.offsets.config->dmem.fpn.offset;
}
if (size) {
ia_css_fpn_config((struct sh_css_isp_fpn_isp_config *)
&binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset],
config_dmem, size); }
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_fpn() leave:\n");
}
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_dvs(
const struct ia_css_binary *binary,
const struct ia_css_dvs_configuration *config_dmem)
{
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_dvs() enter:\n");
{
unsigned offset = 0;
unsigned size = 0;
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.dvs.size;
offset = binary->info->mem_offsets.offsets.config->dmem.dvs.offset;
}
if (size) {
ia_css_dvs_config((struct sh_css_isp_dvs_isp_config *)
&binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset],
config_dmem, size); }
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_dvs() leave:\n");
}
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_qplane(
const struct ia_css_binary *binary,
const struct ia_css_qplane_configuration *config_dmem)
{
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_qplane() enter:\n");
{
unsigned offset = 0;
unsigned size = 0;
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.qplane.size;
offset = binary->info->mem_offsets.offsets.config->dmem.qplane.offset;
}
if (size) {
ia_css_qplane_config((struct sh_css_isp_qplane_isp_config *)
&binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset],
config_dmem, size); }
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_qplane() leave:\n");
}
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_output0(
const struct ia_css_binary *binary,
const struct ia_css_output0_configuration *config_dmem)
{
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_output0() enter:\n");
{
unsigned offset = 0;
unsigned size = 0;
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.output0.size;
offset = binary->info->mem_offsets.offsets.config->dmem.output0.offset;
}
if (size) {
ia_css_output0_config((struct sh_css_isp_output_isp_config *)
&binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset],
config_dmem, size); }
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_output0() leave:\n");
}
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_output1(
const struct ia_css_binary *binary,
const struct ia_css_output1_configuration *config_dmem)
{
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_output1() enter:\n");
{
unsigned offset = 0;
unsigned size = 0;
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.output1.size;
offset = binary->info->mem_offsets.offsets.config->dmem.output1.offset;
}
if (size) {
ia_css_output1_config((struct sh_css_isp_output_isp_config *)
&binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset],
config_dmem, size); }
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_output1() leave:\n");
}
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_output(
const struct ia_css_binary *binary,
const struct ia_css_output_configuration *config_dmem)
{
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_output() enter:\n");
{
unsigned offset = 0;
unsigned size = 0;
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.output.size;
offset = binary->info->mem_offsets.offsets.config->dmem.output.offset;
}
if (size) {
ia_css_output_config((struct sh_css_isp_output_isp_config *)
&binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset],
config_dmem, size); }
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_output() leave:\n");
}
/* Code generated by genparam/genconfig.c:gen_configure_function() */
#ifdef ISP2401
void
ia_css_configure_sc(
const struct ia_css_binary *binary,
const struct ia_css_sc_configuration *config_dmem)
{
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_sc() enter:\n");
{
unsigned offset = 0;
unsigned size = 0;
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.sc.size;
offset = binary->info->mem_offsets.offsets.config->dmem.sc.offset;
}
if (size) {
ia_css_sc_config((struct sh_css_isp_sc_isp_config *)
&binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset],
config_dmem, size); }
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_sc() leave:\n");
}
/* Code generated by genparam/genconfig.c:gen_configure_function() */
#endif
void
ia_css_configure_raw(
const struct ia_css_binary *binary,
const struct ia_css_raw_configuration *config_dmem)
{
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_raw() enter:\n");
{
unsigned offset = 0;
unsigned size = 0;
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.raw.size;
offset = binary->info->mem_offsets.offsets.config->dmem.raw.offset;
}
if (size) {
ia_css_raw_config((struct sh_css_isp_raw_isp_config *)
&binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset],
config_dmem, size); }
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_raw() leave:\n");
}
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_tnr(
const struct ia_css_binary *binary,
const struct ia_css_tnr_configuration *config_dmem)
{
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_tnr() enter:\n");
{
unsigned offset = 0;
unsigned size = 0;
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.tnr.size;
offset = binary->info->mem_offsets.offsets.config->dmem.tnr.offset;
}
if (size) {
ia_css_tnr_config((struct sh_css_isp_tnr_isp_config *)
&binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset],
config_dmem, size); }
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_tnr() leave:\n");
}
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_ref(
const struct ia_css_binary *binary,
const struct ia_css_ref_configuration *config_dmem)
{
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_ref() enter:\n");
{
unsigned offset = 0;
unsigned size = 0;
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.ref.size;
offset = binary->info->mem_offsets.offsets.config->dmem.ref.offset;
}
if (size) {
ia_css_ref_config((struct sh_css_isp_ref_isp_config *)
&binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset],
config_dmem, size); }
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_ref() leave:\n");
}
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_vf(
const struct ia_css_binary *binary,
const struct ia_css_vf_configuration *config_dmem)
{
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_vf() enter:\n");
{
unsigned offset = 0;
unsigned size = 0;
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.vf.size;
offset = binary->info->mem_offsets.offsets.config->dmem.vf.offset;
}
if (size) {
ia_css_vf_config((struct sh_css_isp_vf_isp_config *)
&binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset],
config_dmem, size); }
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_vf() leave:\n");
}

189
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hive_isp_css_2400_system_generated/ia_css_isp_configs.h
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@ -1,189 +0,0 @@
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifdef IA_CSS_INCLUDE_CONFIGURATIONS
#include "isp/kernels/crop/crop_1.0/ia_css_crop.host.h"
#include "isp/kernels/dvs/dvs_1.0/ia_css_dvs.host.h"
#include "isp/kernels/fpn/fpn_1.0/ia_css_fpn.host.h"
#include "isp/kernels/ob/ob_1.0/ia_css_ob.host.h"
#include "isp/kernels/output/output_1.0/ia_css_output.host.h"
#include "isp/kernels/qplane/qplane_2/ia_css_qplane.host.h"
#include "isp/kernels/raw/raw_1.0/ia_css_raw.host.h"
#include "isp/kernels/ref/ref_1.0/ia_css_ref.host.h"
#include "isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.h"
#ifdef ISP2401
#include "isp/kernels/sc/sc_1.0/ia_css_sc.host.h"
#endif
#include "isp/kernels/tnr/tnr_1.0/ia_css_tnr.host.h"
#include "isp/kernels/vf/vf_1.0/ia_css_vf.host.h"
#include "isp/kernels/iterator/iterator_1.0/ia_css_iterator.host.h"
#include "isp/kernels/copy_output/copy_output_1.0/ia_css_copy_output.host.h"
#endif /* IA_CSS_INCLUDE_CONFIGURATIONS */
/* Generated code: do not edit or commmit. */
#ifndef _IA_CSS_ISP_CONFIG_H
#define _IA_CSS_ISP_CONFIG_H
/* Code generated by genparam/gencode.c:gen_param_enum() */
enum ia_css_configuration_ids {
IA_CSS_ITERATOR_CONFIG_ID,
IA_CSS_COPY_OUTPUT_CONFIG_ID,
IA_CSS_CROP_CONFIG_ID,
IA_CSS_FPN_CONFIG_ID,
IA_CSS_DVS_CONFIG_ID,
IA_CSS_QPLANE_CONFIG_ID,
IA_CSS_OUTPUT0_CONFIG_ID,
IA_CSS_OUTPUT1_CONFIG_ID,
IA_CSS_OUTPUT_CONFIG_ID,
#ifdef ISP2401
IA_CSS_SC_CONFIG_ID,
#endif
IA_CSS_RAW_CONFIG_ID,
IA_CSS_TNR_CONFIG_ID,
IA_CSS_REF_CONFIG_ID,
IA_CSS_VF_CONFIG_ID,
IA_CSS_NUM_CONFIGURATION_IDS
};
/* Code generated by genparam/gencode.c:gen_param_offsets() */
struct ia_css_config_memory_offsets {
struct {
struct ia_css_isp_parameter iterator;
struct ia_css_isp_parameter copy_output;
struct ia_css_isp_parameter crop;
struct ia_css_isp_parameter fpn;
struct ia_css_isp_parameter dvs;
struct ia_css_isp_parameter qplane;
struct ia_css_isp_parameter output0;
struct ia_css_isp_parameter output1;
struct ia_css_isp_parameter output;
#ifdef ISP2401
struct ia_css_isp_parameter sc;
#endif
struct ia_css_isp_parameter raw;
struct ia_css_isp_parameter tnr;
struct ia_css_isp_parameter ref;
struct ia_css_isp_parameter vf;
} dmem;
};
#if defined(IA_CSS_INCLUDE_CONFIGURATIONS)
#include "ia_css_stream.h" /* struct ia_css_stream */
#include "ia_css_binary.h" /* struct ia_css_binary */
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_iterator(
const struct ia_css_binary *binary,
const struct ia_css_iterator_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_copy_output(
const struct ia_css_binary *binary,
const struct ia_css_copy_output_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_crop(
const struct ia_css_binary *binary,
const struct ia_css_crop_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_fpn(
const struct ia_css_binary *binary,
const struct ia_css_fpn_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_dvs(
const struct ia_css_binary *binary,
const struct ia_css_dvs_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_qplane(
const struct ia_css_binary *binary,
const struct ia_css_qplane_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_output0(
const struct ia_css_binary *binary,
const struct ia_css_output0_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_output1(
const struct ia_css_binary *binary,
const struct ia_css_output1_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_output(
const struct ia_css_binary *binary,
const struct ia_css_output_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
#ifdef ISP2401
void
ia_css_configure_sc(
const struct ia_css_binary *binary,
const struct ia_css_sc_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
#endif
void
ia_css_configure_raw(
const struct ia_css_binary *binary,
const struct ia_css_raw_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_tnr(
const struct ia_css_binary *binary,
const struct ia_css_tnr_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_ref(
const struct ia_css_binary *binary,
const struct ia_css_ref_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_vf(
const struct ia_css_binary *binary,
const struct ia_css_vf_configuration *config_dmem);
#endif /* IA_CSS_INCLUDE_CONFIGURATION */
#endif /* _IA_CSS_ISP_CONFIG_H */

3221
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hive_isp_css_2400_system_generated/ia_css_isp_params.c
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399
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hive_isp_css_2400_system_generated/ia_css_isp_params.h
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@ -1,399 +0,0 @@
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
/* Generated code: do not edit or commmit. */
#ifndef _IA_CSS_ISP_PARAM_H
#define _IA_CSS_ISP_PARAM_H
/* Code generated by genparam/gencode.c:gen_param_enum() */
enum ia_css_parameter_ids {
IA_CSS_AA_ID,
IA_CSS_ANR_ID,
IA_CSS_ANR2_ID,
IA_CSS_BH_ID,
IA_CSS_CNR_ID,
IA_CSS_CROP_ID,
IA_CSS_CSC_ID,
IA_CSS_DP_ID,
IA_CSS_BNR_ID,
IA_CSS_DE_ID,
IA_CSS_ECD_ID,
IA_CSS_FORMATS_ID,
IA_CSS_FPN_ID,
IA_CSS_GC_ID,
IA_CSS_CE_ID,
IA_CSS_YUV2RGB_ID,
IA_CSS_RGB2YUV_ID,
IA_CSS_R_GAMMA_ID,
IA_CSS_G_GAMMA_ID,
IA_CSS_B_GAMMA_ID,
IA_CSS_UDS_ID,
IA_CSS_RAA_ID,
IA_CSS_S3A_ID,
IA_CSS_OB_ID,
IA_CSS_OUTPUT_ID,
IA_CSS_SC_ID,
IA_CSS_BDS_ID,
IA_CSS_TNR_ID,
IA_CSS_MACC_ID,
IA_CSS_SDIS_HORICOEF_ID,
IA_CSS_SDIS_VERTCOEF_ID,
IA_CSS_SDIS_HORIPROJ_ID,
IA_CSS_SDIS_VERTPROJ_ID,
IA_CSS_SDIS2_HORICOEF_ID,
IA_CSS_SDIS2_VERTCOEF_ID,
IA_CSS_SDIS2_HORIPROJ_ID,
IA_CSS_SDIS2_VERTPROJ_ID,
IA_CSS_WB_ID,
IA_CSS_NR_ID,
IA_CSS_YEE_ID,
IA_CSS_YNR_ID,
IA_CSS_FC_ID,
IA_CSS_CTC_ID,
IA_CSS_XNR_TABLE_ID,
IA_CSS_XNR_ID,
IA_CSS_XNR3_ID,
IA_CSS_NUM_PARAMETER_IDS
};
/* Code generated by genparam/gencode.c:gen_param_offsets() */
struct ia_css_memory_offsets {
struct {
struct ia_css_isp_parameter aa;
struct ia_css_isp_parameter anr;
struct ia_css_isp_parameter bh;
struct ia_css_isp_parameter cnr;
struct ia_css_isp_parameter crop;
struct ia_css_isp_parameter csc;
struct ia_css_isp_parameter dp;
struct ia_css_isp_parameter bnr;
struct ia_css_isp_parameter de;
struct ia_css_isp_parameter ecd;
struct ia_css_isp_parameter formats;
struct ia_css_isp_parameter fpn;
struct ia_css_isp_parameter gc;
struct ia_css_isp_parameter ce;
struct ia_css_isp_parameter yuv2rgb;
struct ia_css_isp_parameter rgb2yuv;
struct ia_css_isp_parameter uds;
struct ia_css_isp_parameter raa;
struct ia_css_isp_parameter s3a;
struct ia_css_isp_parameter ob;
struct ia_css_isp_parameter output;
struct ia_css_isp_parameter sc;
struct ia_css_isp_parameter bds;
struct ia_css_isp_parameter tnr;
struct ia_css_isp_parameter macc;
struct ia_css_isp_parameter sdis_horiproj;
struct ia_css_isp_parameter sdis_vertproj;
struct ia_css_isp_parameter sdis2_horiproj;
struct ia_css_isp_parameter sdis2_vertproj;
struct ia_css_isp_parameter wb;
struct ia_css_isp_parameter nr;
struct ia_css_isp_parameter yee;
struct ia_css_isp_parameter ynr;
struct ia_css_isp_parameter fc;
struct ia_css_isp_parameter ctc;
struct ia_css_isp_parameter xnr;
struct ia_css_isp_parameter xnr3;
struct ia_css_isp_parameter get;
struct ia_css_isp_parameter put;
} dmem;
struct {
struct ia_css_isp_parameter anr2;
struct ia_css_isp_parameter ob;
struct ia_css_isp_parameter sdis_horicoef;
struct ia_css_isp_parameter sdis_vertcoef;
struct ia_css_isp_parameter sdis2_horicoef;
struct ia_css_isp_parameter sdis2_vertcoef;
#ifdef ISP2401
struct ia_css_isp_parameter xnr3;
#endif
} vmem;
struct {
struct ia_css_isp_parameter bh;
} hmem0;
struct {
struct ia_css_isp_parameter gc;
struct ia_css_isp_parameter g_gamma;
struct ia_css_isp_parameter xnr_table;
} vamem1;
struct {
struct ia_css_isp_parameter r_gamma;
struct ia_css_isp_parameter ctc;
} vamem0;
struct {
struct ia_css_isp_parameter b_gamma;
} vamem2;
};
#if defined(IA_CSS_INCLUDE_PARAMETERS)
#include "ia_css_stream.h" /* struct ia_css_stream */
#include "ia_css_binary.h" /* struct ia_css_binary */
/* Code generated by genparam/gencode.c:gen_param_process_table() */
struct ia_css_pipeline_stage; /* forward declaration */
extern void (* ia_css_kernel_process_param[IA_CSS_NUM_PARAMETER_IDS])(
unsigned pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_dp_config(struct ia_css_isp_parameters *params,
const struct ia_css_dp_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_wb_config(struct ia_css_isp_parameters *params,
const struct ia_css_wb_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_tnr_config(struct ia_css_isp_parameters *params,
const struct ia_css_tnr_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_ob_config(struct ia_css_isp_parameters *params,
const struct ia_css_ob_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_de_config(struct ia_css_isp_parameters *params,
const struct ia_css_de_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_anr_config(struct ia_css_isp_parameters *params,
const struct ia_css_anr_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_anr2_config(struct ia_css_isp_parameters *params,
const struct ia_css_anr_thres *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_ce_config(struct ia_css_isp_parameters *params,
const struct ia_css_ce_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_ecd_config(struct ia_css_isp_parameters *params,
const struct ia_css_ecd_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_ynr_config(struct ia_css_isp_parameters *params,
const struct ia_css_ynr_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_fc_config(struct ia_css_isp_parameters *params,
const struct ia_css_fc_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_cnr_config(struct ia_css_isp_parameters *params,
const struct ia_css_cnr_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_macc_config(struct ia_css_isp_parameters *params,
const struct ia_css_macc_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_ctc_config(struct ia_css_isp_parameters *params,
const struct ia_css_ctc_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_aa_config(struct ia_css_isp_parameters *params,
const struct ia_css_aa_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_yuv2rgb_config(struct ia_css_isp_parameters *params,
const struct ia_css_cc_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_rgb2yuv_config(struct ia_css_isp_parameters *params,
const struct ia_css_cc_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_csc_config(struct ia_css_isp_parameters *params,
const struct ia_css_cc_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_nr_config(struct ia_css_isp_parameters *params,
const struct ia_css_nr_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_gc_config(struct ia_css_isp_parameters *params,
const struct ia_css_gc_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_sdis_horicoef_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs_coefficients *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_sdis_vertcoef_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs_coefficients *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_sdis_horiproj_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs_coefficients *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_sdis_vertproj_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs_coefficients *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_sdis2_horicoef_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs2_coefficients *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_sdis2_vertcoef_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs2_coefficients *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_sdis2_horiproj_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs2_coefficients *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_sdis2_vertproj_config(struct ia_css_isp_parameters *params,
const struct ia_css_dvs2_coefficients *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_r_gamma_config(struct ia_css_isp_parameters *params,
const struct ia_css_rgb_gamma_table *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_g_gamma_config(struct ia_css_isp_parameters *params,
const struct ia_css_rgb_gamma_table *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_b_gamma_config(struct ia_css_isp_parameters *params,
const struct ia_css_rgb_gamma_table *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_xnr_table_config(struct ia_css_isp_parameters *params,
const struct ia_css_xnr_table *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_formats_config(struct ia_css_isp_parameters *params,
const struct ia_css_formats_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_xnr_config(struct ia_css_isp_parameters *params,
const struct ia_css_xnr_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_xnr3_config(struct ia_css_isp_parameters *params,
const struct ia_css_xnr3_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_s3a_config(struct ia_css_isp_parameters *params,
const struct ia_css_3a_config *config);
/* Code generated by genparam/gencode.c:gen_set_function() */
void
ia_css_set_output_config(struct ia_css_isp_parameters *params,
const struct ia_css_output_config *config);
/* Code generated by genparam/gencode.c:gen_global_access_function() */
void
ia_css_get_configs(struct ia_css_isp_parameters *params,
const struct ia_css_isp_config *config)
;
#ifdef ISP2401
#endif
/* Code generated by genparam/gencode.c:gen_global_access_function() */
void
ia_css_set_configs(struct ia_css_isp_parameters *params,
const struct ia_css_isp_config *config)
;
#ifdef ISP2401
#endif
#endif /* IA_CSS_INCLUDE_PARAMETER */
#endif /* _IA_CSS_ISP_PARAM_H */

214
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hive_isp_css_2400_system_generated/ia_css_isp_states.c
View File

@ -1,214 +0,0 @@
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
/* Generated code: do not edit or commmit. */
#include "ia_css_pipeline.h"
#include "ia_css_isp_states.h"
#include "ia_css_debug.h"
#include "assert_support.h"
/* Code generated by genparam/genstate.c:gen_init_function() */
static void
ia_css_initialize_aa_state(
const struct ia_css_binary *binary)
{
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_aa_state() enter:\n");
{
unsigned size = binary->info->mem_offsets.offsets.state->vmem.aa.size;
unsigned offset = binary->info->mem_offsets.offsets.state->vmem.aa.offset;
if (size)
memset(&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset], 0, size);
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_aa_state() leave:\n");
}
/* Code generated by genparam/genstate.c:gen_init_function() */
static void
ia_css_initialize_cnr_state(
const struct ia_css_binary *binary)
{
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_cnr_state() enter:\n");
{
unsigned size = binary->info->mem_offsets.offsets.state->vmem.cnr.size;
unsigned offset = binary->info->mem_offsets.offsets.state->vmem.cnr.offset;
if (size) {
ia_css_init_cnr_state(
&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset],
size);
}
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_cnr_state() leave:\n");
}
/* Code generated by genparam/genstate.c:gen_init_function() */
static void
ia_css_initialize_cnr2_state(
const struct ia_css_binary *binary)
{
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_cnr2_state() enter:\n");
{
unsigned size = binary->info->mem_offsets.offsets.state->vmem.cnr2.size;
unsigned offset = binary->info->mem_offsets.offsets.state->vmem.cnr2.offset;
if (size) {
ia_css_init_cnr2_state(
&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset],
size);
}
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_cnr2_state() leave:\n");
}
/* Code generated by genparam/genstate.c:gen_init_function() */
static void
ia_css_initialize_dp_state(
const struct ia_css_binary *binary)
{
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_dp_state() enter:\n");
{
unsigned size = binary->info->mem_offsets.offsets.state->vmem.dp.size;
unsigned offset = binary->info->mem_offsets.offsets.state->vmem.dp.offset;
if (size) {
ia_css_init_dp_state(
&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset],
size);
}
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_dp_state() leave:\n");
}
/* Code generated by genparam/genstate.c:gen_init_function() */
static void
ia_css_initialize_de_state(
const struct ia_css_binary *binary)
{
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_de_state() enter:\n");
{
unsigned size = binary->info->mem_offsets.offsets.state->vmem.de.size;
unsigned offset = binary->info->mem_offsets.offsets.state->vmem.de.offset;
if (size) {
ia_css_init_de_state(
&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset],
size);
}
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_de_state() leave:\n");
}
/* Code generated by genparam/genstate.c:gen_init_function() */
static void
ia_css_initialize_tnr_state(
const struct ia_css_binary *binary)
{
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_tnr_state() enter:\n");
{
unsigned size = binary->info->mem_offsets.offsets.state->dmem.tnr.size;
unsigned offset = binary->info->mem_offsets.offsets.state->dmem.tnr.offset;
if (size) {
ia_css_init_tnr_state((struct sh_css_isp_tnr_dmem_state *)
&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_DMEM].address[offset],
size);
}
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_tnr_state() leave:\n");
}
/* Code generated by genparam/genstate.c:gen_init_function() */
static void
ia_css_initialize_ref_state(
const struct ia_css_binary *binary)
{
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_ref_state() enter:\n");
{
unsigned size = binary->info->mem_offsets.offsets.state->dmem.ref.size;
unsigned offset = binary->info->mem_offsets.offsets.state->dmem.ref.offset;
if (size) {
ia_css_init_ref_state((struct sh_css_isp_ref_dmem_state *)
&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_DMEM].address[offset],
size);
}
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_ref_state() leave:\n");
}
/* Code generated by genparam/genstate.c:gen_init_function() */
static void
ia_css_initialize_ynr_state(
const struct ia_css_binary *binary)
{
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_ynr_state() enter:\n");
{
unsigned size = binary->info->mem_offsets.offsets.state->vmem.ynr.size;
unsigned offset = binary->info->mem_offsets.offsets.state->vmem.ynr.offset;
if (size) {
ia_css_init_ynr_state(
&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset],
size);
}
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_ynr_state() leave:\n");
}
/* Code generated by genparam/genstate.c:gen_state_init_table() */
void (* ia_css_kernel_init_state[IA_CSS_NUM_STATE_IDS])(const struct ia_css_binary *binary) = {
ia_css_initialize_aa_state,
ia_css_initialize_cnr_state,
ia_css_initialize_cnr2_state,
ia_css_initialize_dp_state,
ia_css_initialize_de_state,
ia_css_initialize_tnr_state,
ia_css_initialize_ref_state,
ia_css_initialize_ynr_state,
};

72
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hive_isp_css_2400_system_generated/ia_css_isp_states.h
View File

@ -1,72 +0,0 @@
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#define IA_CSS_INCLUDE_STATES
#include "isp/kernels/aa/aa_2/ia_css_aa2.host.h"
#include "isp/kernels/cnr/cnr_1.0/ia_css_cnr.host.h"
#include "isp/kernels/cnr/cnr_2/ia_css_cnr2.host.h"
#include "isp/kernels/de/de_1.0/ia_css_de.host.h"
#include "isp/kernels/dp/dp_1.0/ia_css_dp.host.h"
#include "isp/kernels/ref/ref_1.0/ia_css_ref.host.h"
#include "isp/kernels/tnr/tnr_1.0/ia_css_tnr.host.h"
#include "isp/kernels/ynr/ynr_1.0/ia_css_ynr.host.h"
#include "isp/kernels/dpc2/ia_css_dpc2.host.h"
#include "isp/kernels/eed1_8/ia_css_eed1_8.host.h"
/* Generated code: do not edit or commmit. */
#ifndef _IA_CSS_ISP_STATE_H
#define _IA_CSS_ISP_STATE_H
/* Code generated by genparam/gencode.c:gen_param_enum() */
enum ia_css_state_ids {
IA_CSS_AA_STATE_ID,
IA_CSS_CNR_STATE_ID,
IA_CSS_CNR2_STATE_ID,
IA_CSS_DP_STATE_ID,
IA_CSS_DE_STATE_ID,
IA_CSS_TNR_STATE_ID,
IA_CSS_REF_STATE_ID,
IA_CSS_YNR_STATE_ID,
IA_CSS_NUM_STATE_IDS
};
/* Code generated by genparam/gencode.c:gen_param_offsets() */
struct ia_css_state_memory_offsets {
struct {
struct ia_css_isp_parameter aa;
struct ia_css_isp_parameter cnr;
struct ia_css_isp_parameter cnr2;
struct ia_css_isp_parameter dp;
struct ia_css_isp_parameter de;
struct ia_css_isp_parameter ynr;
} vmem;
struct {
struct ia_css_isp_parameter tnr;
struct ia_css_isp_parameter ref;
} dmem;
};
#if defined(IA_CSS_INCLUDE_STATES)
#include "ia_css_stream.h" /* struct ia_css_stream */
#include "ia_css_binary.h" /* struct ia_css_binary */
/* Code generated by genparam/genstate.c:gen_state_init_table() */
extern void (* ia_css_kernel_init_state[IA_CSS_NUM_STATE_IDS])(const struct ia_css_binary *binary);
#endif /* IA_CSS_INCLUDE_STATE */
#endif /* _IA_CSS_ISP_STATE_H */

104
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/bits.h
View File

@ -1,104 +0,0 @@
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _HRT_BITS_H
#define _HRT_BITS_H
#include "defs.h"
#define _hrt_ones(n) HRTCAT(_hrt_ones_, n)
#define _hrt_ones_0x0 0x00000000U
#define _hrt_ones_0x1 0x00000001U
#define _hrt_ones_0x2 0x00000003U
#define _hrt_ones_0x3 0x00000007U
#define _hrt_ones_0x4 0x0000000FU
#define _hrt_ones_0x5 0x0000001FU
#define _hrt_ones_0x6 0x0000003FU
#define _hrt_ones_0x7 0x0000007FU
#define _hrt_ones_0x8 0x000000FFU
#define _hrt_ones_0x9 0x000001FFU
#define _hrt_ones_0xA 0x000003FFU
#define _hrt_ones_0xB 0x000007FFU
#define _hrt_ones_0xC 0x00000FFFU
#define _hrt_ones_0xD 0x00001FFFU
#define _hrt_ones_0xE 0x00003FFFU
#define _hrt_ones_0xF 0x00007FFFU
#define _hrt_ones_0x10 0x0000FFFFU
#define _hrt_ones_0x11 0x0001FFFFU
#define _hrt_ones_0x12 0x0003FFFFU
#define _hrt_ones_0x13 0x0007FFFFU
#define _hrt_ones_0x14 0x000FFFFFU
#define _hrt_ones_0x15 0x001FFFFFU
#define _hrt_ones_0x16 0x003FFFFFU
#define _hrt_ones_0x17 0x007FFFFFU
#define _hrt_ones_0x18 0x00FFFFFFU
#define _hrt_ones_0x19 0x01FFFFFFU
#define _hrt_ones_0x1A 0x03FFFFFFU
#define _hrt_ones_0x1B 0x07FFFFFFU
#define _hrt_ones_0x1C 0x0FFFFFFFU
#define _hrt_ones_0x1D 0x1FFFFFFFU
#define _hrt_ones_0x1E 0x3FFFFFFFU
#define _hrt_ones_0x1F 0x7FFFFFFFU
#define _hrt_ones_0x20 0xFFFFFFFFU
#define _hrt_ones_0 _hrt_ones_0x0
#define _hrt_ones_1 _hrt_ones_0x1
#define _hrt_ones_2 _hrt_ones_0x2
#define _hrt_ones_3 _hrt_ones_0x3
#define _hrt_ones_4 _hrt_ones_0x4
#define _hrt_ones_5 _hrt_ones_0x5
#define _hrt_ones_6 _hrt_ones_0x6
#define _hrt_ones_7 _hrt_ones_0x7
#define _hrt_ones_8 _hrt_ones_0x8
#define _hrt_ones_9 _hrt_ones_0x9
#define _hrt_ones_10 _hrt_ones_0xA
#define _hrt_ones_11 _hrt_ones_0xB
#define _hrt_ones_12 _hrt_ones_0xC
#define _hrt_ones_13 _hrt_ones_0xD
#define _hrt_ones_14 _hrt_ones_0xE
#define _hrt_ones_15 _hrt_ones_0xF
#define _hrt_ones_16 _hrt_ones_0x10
#define _hrt_ones_17 _hrt_ones_0x11
#define _hrt_ones_18 _hrt_ones_0x12
#define _hrt_ones_19 _hrt_ones_0x13
#define _hrt_ones_20 _hrt_ones_0x14
#define _hrt_ones_21 _hrt_ones_0x15
#define _hrt_ones_22 _hrt_ones_0x16
#define _hrt_ones_23 _hrt_ones_0x17
#define _hrt_ones_24 _hrt_ones_0x18
#define _hrt_ones_25 _hrt_ones_0x19
#define _hrt_ones_26 _hrt_ones_0x1A
#define _hrt_ones_27 _hrt_ones_0x1B
#define _hrt_ones_28 _hrt_ones_0x1C
#define _hrt_ones_29 _hrt_ones_0x1D
#define _hrt_ones_30 _hrt_ones_0x1E
#define _hrt_ones_31 _hrt_ones_0x1F
#define _hrt_ones_32 _hrt_ones_0x20
#define _hrt_mask(b, n) \
(_hrt_ones(n) << (b))
#define _hrt_get_bits(w, b, n) \
(((w) >> (b)) & _hrt_ones(n))
#define _hrt_set_bits(w, b, n, v) \
(((w) & ~_hrt_mask(b, n)) | (((v) & _hrt_ones(n)) << (b)))
#define _hrt_get_bit(w, b) \
(((w) >> (b)) & 1)
#define _hrt_set_bit(w, b, v) \
(((w) & (~(1 << (b)))) | (((v)&1) << (b)))
#define _hrt_set_lower_half(w, v) \
_hrt_set_bits(w, 0, 16, v)
#define _hrt_set_upper_half(w, v) \
_hrt_set_bits(w, 16, 16, v)
#endif /* _HRT_BITS_H */

42
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/cell_params.h
View File

@ -1,42 +0,0 @@
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _cell_params_h
#define _cell_params_h
#define SP_PMEM_LOG_WIDTH_BITS 6 /*Width of PC, 64 bits, 8 bytes*/
#define SP_ICACHE_TAG_BITS 4 /*size of tag*/
#define SP_ICACHE_SET_BITS 8 /* 256 sets*/
#define SP_ICACHE_BLOCKS_PER_SET_BITS 1 /* 2 way associative*/
#define SP_ICACHE_BLOCK_ADDRESS_BITS 11 /* 2048 lines capacity*/
#define SP_ICACHE_ADDRESS_BITS \
(SP_ICACHE_TAG_BITS+SP_ICACHE_BLOCK_ADDRESS_BITS)
#define SP_PMEM_DEPTH (1<<SP_ICACHE_ADDRESS_BITS)
#define SP_FIFO_0_DEPTH 0
#define SP_FIFO_1_DEPTH 0
#define SP_FIFO_2_DEPTH 0
#define SP_FIFO_3_DEPTH 0
#define SP_FIFO_4_DEPTH 0
#define SP_FIFO_5_DEPTH 0
#define SP_FIFO_6_DEPTH 0
#define SP_FIFO_7_DEPTH 0
#define SP_SLV_BUS_MAXBURSTSIZE 1
#endif /* _cell_params_h */

200
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/css_receiver_2400_common_defs.h
View File

@ -1,200 +0,0 @@
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _css_receiver_2400_common_defs_h_
#define _css_receiver_2400_common_defs_h_
#ifndef _mipi_backend_common_defs_h_
#define _mipi_backend_common_defs_h_
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_DATA_WIDTH 16
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_CH_ID_WIDTH 2
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_FMT_TYPE_WIDTH 3
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_REAL_WIDTH (_HRT_CSS_RECEIVER_2400_GEN_SHORT_DATA_WIDTH + _HRT_CSS_RECEIVER_2400_GEN_SHORT_CH_ID_WIDTH + _HRT_CSS_RECEIVER_2400_GEN_SHORT_FMT_TYPE_WIDTH)
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_WIDTH 32 /* use 32 to be compatibel with streaming monitor !, MSB's of interface are tied to '0' */
/* Definition of data format ID at the interface CSS_receiver capture/acquisition units */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8 24 /* 01 1000 YUV420 8-bit */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_10 25 /* 01 1001 YUV420 10-bit */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8L 26 /* 01 1010 YUV420 8-bit legacy */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV422_8 30 /* 01 1110 YUV422 8-bit */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV422_10 31 /* 01 1111 YUV422 10-bit */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB444 32 /* 10 0000 RGB444 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB555 33 /* 10 0001 RGB555 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB565 34 /* 10 0010 RGB565 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB666 35 /* 10 0011 RGB666 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB888 36 /* 10 0100 RGB888 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW6 40 /* 10 1000 RAW6 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW7 41 /* 10 1001 RAW7 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW8 42 /* 10 1010 RAW8 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW10 43 /* 10 1011 RAW10 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW12 44 /* 10 1100 RAW12 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW14 45 /* 10 1101 RAW14 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_1 48 /* 11 0000 JPEG [User Defined 8-bit Data Type 1] */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_2 49 /* 11 0001 User Defined 8-bit Data Type 2 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_3 50 /* 11 0010 User Defined 8-bit Data Type 3 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_4 51 /* 11 0011 User Defined 8-bit Data Type 4 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_5 52 /* 11 0100 User Defined 8-bit Data Type 5 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_6 53 /* 11 0101 User Defined 8-bit Data Type 6 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_7 54 /* 11 0110 User Defined 8-bit Data Type 7 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_8 55 /* 11 0111 User Defined 8-bit Data Type 8 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_Emb 18 /* 01 0010 embedded eight bit non image data */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_SOF 0 /* 00 0000 frame start */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_EOF 1 /* 00 0001 frame end */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_SOL 2 /* 00 0010 line start */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_EOL 3 /* 00 0011 line end */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH1 8 /* 00 1000 Generic Short Packet Code 1 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH2 9 /* 00 1001 Generic Short Packet Code 2 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH3 10 /* 00 1010 Generic Short Packet Code 3 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH4 11 /* 00 1011 Generic Short Packet Code 4 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH5 12 /* 00 1100 Generic Short Packet Code 5 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH6 13 /* 00 1101 Generic Short Packet Code 6 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH7 14 /* 00 1110 Generic Short Packet Code 7 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH8 15 /* 00 1111 Generic Short Packet Code 8 */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8_CSPS 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_10_CSPS 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */
/* used reseved mipi positions for these */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW16 46
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18 47
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18_2 37
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18_3 38
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_WIDTH 6
/* Definition of format_types at the interface CSS --> input_selector*/
/* !! Changes here should be copied to systems/isp/isp_css/bin/conv_transmitter_cmd.tcl !! */
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB888 0 // 36 'h24
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB555 1 // 33 'h
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB444 2 // 32
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB565 3 // 34
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB666 4 // 35
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW8 5 // 42
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW10 6 // 43
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW6 7 // 40
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW7 8 // 41
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW12 9 // 43
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW14 10 // 45
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_8 11 // 30
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_10 12 // 25
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV422_8 13 // 30
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV422_10 14 // 31
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_1 15 // 48
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_8L 16 // 26
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_Emb 17 // 18
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_2 18 // 49
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_3 19 // 50
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_4 20 // 51
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_5 21 // 52
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_6 22 // 53
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_7 23 // 54
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_8 24 // 55
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_8_CSPS 25 // 28
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_10_CSPS 26 // 29
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW16 27 // ?
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18 28 // ?
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18_2 29 // ? Option 2 for depacketiser
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18_3 30 // ? Option 3 for depacketiser
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_CUSTOM 31 // to signal custom decoding
/* definition for state machine of data FIFO for decode different type of data */
#define _HRT_CSS_RECEIVER_2400_YUV420_8_REPEAT_PTN 1
#define _HRT_CSS_RECEIVER_2400_YUV420_10_REPEAT_PTN 5
#define _HRT_CSS_RECEIVER_2400_YUV420_8L_REPEAT_PTN 1
#define _HRT_CSS_RECEIVER_2400_YUV422_8_REPEAT_PTN 1
#define _HRT_CSS_RECEIVER_2400_YUV422_10_REPEAT_PTN 5
#define _HRT_CSS_RECEIVER_2400_RGB444_REPEAT_PTN 2
#define _HRT_CSS_RECEIVER_2400_RGB555_REPEAT_PTN 2
#define _HRT_CSS_RECEIVER_2400_RGB565_REPEAT_PTN 2
#define _HRT_CSS_RECEIVER_2400_RGB666_REPEAT_PTN 9
#define _HRT_CSS_RECEIVER_2400_RGB888_REPEAT_PTN 3
#define _HRT_CSS_RECEIVER_2400_RAW6_REPEAT_PTN 3
#define _HRT_CSS_RECEIVER_2400_RAW7_REPEAT_PTN 7
#define _HRT_CSS_RECEIVER_2400_RAW8_REPEAT_PTN 1
#define _HRT_CSS_RECEIVER_2400_RAW10_REPEAT_PTN 5
#define _HRT_CSS_RECEIVER_2400_RAW12_REPEAT_PTN 3
#define _HRT_CSS_RECEIVER_2400_RAW14_REPEAT_PTN 7
#define _HRT_CSS_RECEIVER_2400_MAX_REPEAT_PTN _HRT_CSS_RECEIVER_2400_RGB666_REPEAT_PTN
#define _HRT_CSS_RECEIVER_2400_BE_COMP_FMT_IDX 0
#define _HRT_CSS_RECEIVER_2400_BE_COMP_FMT_WIDTH 3
#define _HRT_CSS_RECEIVER_2400_BE_COMP_PRED_IDX 3
#define _HRT_CSS_RECEIVER_2400_BE_COMP_PRED_WIDTH 1
#define _HRT_CSS_RECEIVER_2400_BE_COMP_USD_BITS 4 /* bits per USD type */
#define _HRT_CSS_RECEIVER_2400_BE_RAW16_DATAID_IDX 0
#define _HRT_CSS_RECEIVER_2400_BE_RAW16_EN_IDX 6
#define _HRT_CSS_RECEIVER_2400_BE_RAW18_DATAID_IDX 0
#define _HRT_CSS_RECEIVER_2400_BE_RAW18_OPTION_IDX 6
#define _HRT_CSS_RECEIVER_2400_BE_RAW18_EN_IDX 8
#define _HRT_CSS_RECEIVER_2400_BE_COMP_NO_COMP 0
#define _HRT_CSS_RECEIVER_2400_BE_COMP_10_6_10 1
#define _HRT_CSS_RECEIVER_2400_BE_COMP_10_7_10 2
#define _HRT_CSS_RECEIVER_2400_BE_COMP_10_8_10 3
#define _HRT_CSS_RECEIVER_2400_BE_COMP_12_6_12 4
#define _HRT_CSS_RECEIVER_2400_BE_COMP_12_7_12 5
#define _HRT_CSS_RECEIVER_2400_BE_COMP_12_8_12 6
/* packet bit definition */
#define _HRT_CSS_RECEIVER_2400_PKT_SOP_IDX 32
#define _HRT_CSS_RECEIVER_2400_PKT_SOP_BITS 1
#define _HRT_CSS_RECEIVER_2400_PKT_CH_ID_IDX 22
#define _HRT_CSS_RECEIVER_2400_PKT_CH_ID_BITS 2
#define _HRT_CSS_RECEIVER_2400_PKT_FMT_ID_IDX 16
#define _HRT_CSS_RECEIVER_2400_PKT_FMT_ID_BITS 6
#define _HRT_CSS_RECEIVER_2400_PH_DATA_FIELD_IDX 0
#define _HRT_CSS_RECEIVER_2400_PH_DATA_FIELD_BITS 16
#define _HRT_CSS_RECEIVER_2400_PKT_PAYLOAD_IDX 0
#define _HRT_CSS_RECEIVER_2400_PKT_PAYLOAD_BITS 32
/*************************************************************************************************/
/* Custom Decoding */
/* These Custom Defs are defined based on design-time config in "csi_be_pixel_formatter.chdl" !! */
/*************************************************************************************************/
#define BE_CUST_EN_IDX 0 /* 2bits */
#define BE_CUST_EN_DATAID_IDX 2 /* 6bits MIPI DATA ID */
#define BE_CUST_EN_WIDTH 8
#define BE_CUST_MODE_ALL 1 /* Enable Custom Decoding for all DATA IDs */
#define BE_CUST_MODE_ONE 3 /* Enable Custom Decoding for ONE DATA ID, programmed in CUST_EN_DATA_ID */
/* Data State config = {get_bits(6bits), valid(1bit)} */
#define BE_CUST_DATA_STATE_S0_IDX 0 /* 7bits */
#define BE_CUST_DATA_STATE_S1_IDX 7 /* 7bits */
#define BE_CUST_DATA_STATE_S2_IDX 14 /* 7bits */
#define BE_CUST_DATA_STATE_WIDTH 21
#define BE_CUST_DATA_STATE_VALID_IDX 0 /* 1bits */
#define BE_CUST_DATA_STATE_GETBITS_IDX 1 /* 6bits */
/* Pixel Extractor config */
#define BE_CUST_PIX_EXT_DATA_ALIGN_IDX 0 /* 5bits */
#define BE_CUST_PIX_EXT_PIX_ALIGN_IDX 5 /* 5bits */
#define BE_CUST_PIX_EXT_PIX_MASK_IDX 10 /* 18bits */
#define BE_CUST_PIX_EXT_PIX_EN_IDX 28 /* 1bits */
#define BE_CUST_PIX_EXT_WIDTH 29
/* Pixel Valid & EoP config = {[eop,valid](especial), [eop,valid](normal)} */
#define BE_CUST_PIX_VALID_EOP_P0_IDX 0 /* 4bits */
#define BE_CUST_PIX_VALID_EOP_P1_IDX 4 /* 4bits */
#define BE_CUST_PIX_VALID_EOP_P2_IDX 8 /* 4bits */
#define BE_CUST_PIX_VALID_EOP_P3_IDX 12 /* 4bits */
#define BE_CUST_PIX_VALID_EOP_WIDTH 16
#define BE_CUST_PIX_VALID_EOP_NOR_VALID_IDX 0 /* Normal (NO less get_bits case) Valid - 1bits */
#define BE_CUST_PIX_VALID_EOP_NOR_EOP_IDX 1 /* Normal (NO less get_bits case) EoP - 1bits */
#define BE_CUST_PIX_VALID_EOP_ESP_VALID_IDX 2 /* Especial (less get_bits case) Valid - 1bits */
#define BE_CUST_PIX_VALID_EOP_ESP_EOP_IDX 3 /* Especial (less get_bits case) EoP - 1bits */
#endif /* _mipi_backend_common_defs_h_ */
#endif /* _css_receiver_2400_common_defs_h_ */

258
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/css_receiver_2400_defs.h
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@ -1,258 +0,0 @@
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _css_receiver_2400_defs_h_
#define _css_receiver_2400_defs_h_
#include "css_receiver_2400_common_defs.h"
#define CSS_RECEIVER_DATA_WIDTH 8
#define CSS_RECEIVER_RX_TRIG 4
#define CSS_RECEIVER_RF_WORD 32
#define CSS_RECEIVER_IMG_PROC_RF_ADDR 10
#define CSS_RECEIVER_CSI_RF_ADDR 4
#define CSS_RECEIVER_DATA_OUT 12
#define CSS_RECEIVER_CHN_NO 2
#define CSS_RECEIVER_DWORD_CNT 11
#define CSS_RECEIVER_FORMAT_TYP 5
#define CSS_RECEIVER_HRESPONSE 2
#define CSS_RECEIVER_STATE_WIDTH 3
#define CSS_RECEIVER_FIFO_DAT 32
#define CSS_RECEIVER_CNT_VAL 2
#define CSS_RECEIVER_PRED10_VAL 10
#define CSS_RECEIVER_PRED12_VAL 12
#define CSS_RECEIVER_CNT_WIDTH 8
#define CSS_RECEIVER_WORD_CNT 16
#define CSS_RECEIVER_PIXEL_LEN 6
#define CSS_RECEIVER_PIXEL_CNT 5
#define CSS_RECEIVER_COMP_8_BIT 8
#define CSS_RECEIVER_COMP_7_BIT 7
#define CSS_RECEIVER_COMP_6_BIT 6
#define CSI_CONFIG_WIDTH 4
/* division of gen_short data, ch_id and fmt_type over streaming data interface */
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_DATA_BIT_LSB 0
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_LSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_DATA_BIT_LSB + _HRT_CSS_RECEIVER_2400_GEN_SHORT_DATA_WIDTH)
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_CH_ID_BIT_LSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_LSB + _HRT_CSS_RECEIVER_2400_GEN_SHORT_FMT_TYPE_WIDTH)
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_DATA_BIT_MSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_LSB - 1)
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_MSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_CH_ID_BIT_LSB - 1)
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_CH_ID_BIT_MSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_REAL_WIDTH - 1)
#define _HRT_CSS_RECEIVER_2400_REG_ALIGN 4
#define _HRT_CSS_RECEIVER_2400_BYTES_PER_PKT 4
#define hrt_css_receiver_2400_4_lane_port_offset 0x100
#define hrt_css_receiver_2400_1_lane_port_offset 0x200
#define hrt_css_receiver_2400_2_lane_port_offset 0x300
#define hrt_css_receiver_2400_backend_port_offset 0x100
#define _HRT_CSS_RECEIVER_2400_DEVICE_READY_REG_IDX 0
#define _HRT_CSS_RECEIVER_2400_IRQ_STATUS_REG_IDX 1
#define _HRT_CSS_RECEIVER_2400_IRQ_ENABLE_REG_IDX 2
#define _HRT_CSS_RECEIVER_2400_CSI2_FUNC_PROG_REG_IDX 3
#define _HRT_CSS_RECEIVER_2400_INIT_COUNT_REG_IDX 4
#define _HRT_CSS_RECEIVER_2400_FS_TO_LS_DELAY_REG_IDX 7
#define _HRT_CSS_RECEIVER_2400_LS_TO_DATA_DELAY_REG_IDX 8
#define _HRT_CSS_RECEIVER_2400_DATA_TO_LE_DELAY_REG_IDX 9
#define _HRT_CSS_RECEIVER_2400_LE_TO_FE_DELAY_REG_IDX 10
#define _HRT_CSS_RECEIVER_2400_FE_TO_FS_DELAY_REG_IDX 11
#define _HRT_CSS_RECEIVER_2400_LE_TO_LS_DELAY_REG_IDX 12
#define _HRT_CSS_RECEIVER_2400_TWO_PIXEL_EN_REG_IDX 13
#define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_REG_IDX 14
#define _HRT_CSS_RECEIVER_2400_SYNC_COUNT_REG_IDX 15
#define _HRT_CSS_RECEIVER_2400_RX_COUNT_REG_IDX 16
#define _HRT_CSS_RECEIVER_2400_BACKEND_RST_REG_IDX 17
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG0_IDX 18
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG1_IDX 19
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG0_IDX 20
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG1_IDX 21
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG0_IDX 22
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG1_IDX 23
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG0_IDX 24
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG1_IDX 25
#define _HRT_CSS_RECEIVER_2400_RAW18_REG_IDX 26
#define _HRT_CSS_RECEIVER_2400_FORCE_RAW8_REG_IDX 27
#define _HRT_CSS_RECEIVER_2400_RAW16_REG_IDX 28
/* Interrupt bits for IRQ_STATUS and IRQ_ENABLE registers */
#define _HRT_CSS_RECEIVER_2400_IRQ_OVERRUN_BIT 0
#define _HRT_CSS_RECEIVER_2400_IRQ_RESERVED_BIT 1
#define _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_ENTRY_BIT 2
#define _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_EXIT_BIT 3
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_HS_BIT 4
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_SYNC_HS_BIT 5
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_CONTROL_BIT 6
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_DOUBLE_BIT 7
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_CORRECTED_BIT 8
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_NO_CORRECTION_BIT 9
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_CRC_BIT 10
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ID_BIT 11
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_SYNC_BIT 12
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_DATA_BIT 13
#define _HRT_CSS_RECEIVER_2400_IRQ_DATA_TIMEOUT_BIT 14
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ESCAPE_BIT 15
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_LINE_SYNC_BIT 16
#define _HRT_CSS_RECEIVER_2400_IRQ_OVERRUN_CAUSE_ "Fifo Overrun"
#define _HRT_CSS_RECEIVER_2400_IRQ_RESERVED_CAUSE_ "Reserved"
#define _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_ENTRY_CAUSE_ "Sleep mode entry"
#define _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_EXIT_CAUSE_ "Sleep mode exit"
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_HS_CAUSE_ "Error high speed SOT"
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_SYNC_HS_CAUSE_ "Error high speed sync SOT"
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_CONTROL_CAUSE_ "Error control"
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_DOUBLE_CAUSE_ "Error correction double bit"
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_CORRECTED_CAUSE_ "Error correction single bit"
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_NO_CORRECTION_CAUSE_ "No error"
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_CRC_CAUSE_ "Error cyclic redundancy check"
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ID_CAUSE_ "Error id"
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_SYNC_CAUSE_ "Error frame sync"
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_DATA_CAUSE_ "Error frame data"
#define _HRT_CSS_RECEIVER_2400_IRQ_DATA_TIMEOUT_CAUSE_ "Data time-out"
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ESCAPE_CAUSE_ "Error escape"
#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_LINE_SYNC_CAUSE_ "Error line sync"
/* Bits for CSI2_DEVICE_READY register */
#define _HRT_CSS_RECEIVER_2400_CSI2_DEVICE_READY_IDX 0
#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_INIT_TIME_OUT_ERR_IDX 2
#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_OVER_RUN_ERR_IDX 3
#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_SOT_SYNC_ERR_IDX 4
#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_RECEIVE_DATA_TIME_OUT_ERR_IDX 5
#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_ECC_TWO_BIT_ERR_IDX 6
#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_DATA_ID_ERR_IDX 7
/* Bits for CSI2_FUNC_PROG register */
#define _HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_IDX 0
#define _HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_BITS 19
/* Bits for INIT_COUNT register */
#define _HRT_CSS_RECEIVER_2400_INIT_TIMER_IDX 0
#define _HRT_CSS_RECEIVER_2400_INIT_TIMER_BITS 16
/* Bits for COUNT registers */
#define _HRT_CSS_RECEIVER_2400_SYNC_COUNT_IDX 0
#define _HRT_CSS_RECEIVER_2400_SYNC_COUNT_BITS 8
#define _HRT_CSS_RECEIVER_2400_RX_COUNT_IDX 0
#define _HRT_CSS_RECEIVER_2400_RX_COUNT_BITS 8
/* Bits for RAW116_18_DATAID register */
#define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_RAW16_BITS_IDX 0
#define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_RAW16_BITS_BITS 6
#define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_RAW18_BITS_IDX 8
#define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_RAW18_BITS_BITS 6
/* Bits for COMP_FORMAT register, this selects the compression data format */
#define _HRT_CSS_RECEIVER_2400_COMP_RAW_BITS_IDX 0
#define _HRT_CSS_RECEIVER_2400_COMP_RAW_BITS_BITS 8
#define _HRT_CSS_RECEIVER_2400_COMP_NUM_BITS_IDX (_HRT_CSS_RECEIVER_2400_COMP_RAW_BITS_IDX + _HRT_CSS_RECEIVER_2400_COMP_RAW_BITS_BITS)
#define _HRT_CSS_RECEIVER_2400_COMP_NUM_BITS_BITS 8
/* Bits for COMP_PREDICT register, this selects the predictor algorithm */
#define _HRT_CSS_RECEIVER_2400_PREDICT_NO_COMP 0
#define _HRT_CSS_RECEIVER_2400_PREDICT_1 1
#define _HRT_CSS_RECEIVER_2400_PREDICT_2 2
/* Number of bits used for the delay registers */
#define _HRT_CSS_RECEIVER_2400_DELAY_BITS 8
/* Bits for COMP_SCHEME register, this selects the compression scheme for a VC */
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD1_BITS_IDX 0
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD2_BITS_IDX 5
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD3_BITS_IDX 10
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD4_BITS_IDX 15
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD5_BITS_IDX 20
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD6_BITS_IDX 25
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD7_BITS_IDX 0
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD8_BITS_IDX 5
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_BITS_BITS 5
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_FMT_BITS_IDX 0
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_FMT_BITS_BITS 3
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_PRED_BITS_IDX 3
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_PRED_BITS_BITS 2
/* BITS for backend RAW16 and RAW 18 registers */
#define _HRT_CSS_RECEIVER_2400_RAW18_DATAID_IDX 0
#define _HRT_CSS_RECEIVER_2400_RAW18_DATAID_BITS 6
#define _HRT_CSS_RECEIVER_2400_RAW18_OPTION_IDX 6
#define _HRT_CSS_RECEIVER_2400_RAW18_OPTION_BITS 2
#define _HRT_CSS_RECEIVER_2400_RAW18_EN_IDX 8
#define _HRT_CSS_RECEIVER_2400_RAW18_EN_BITS 1
#define _HRT_CSS_RECEIVER_2400_RAW16_DATAID_IDX 0
#define _HRT_CSS_RECEIVER_2400_RAW16_DATAID_BITS 6
#define _HRT_CSS_RECEIVER_2400_RAW16_OPTION_IDX 6
#define _HRT_CSS_RECEIVER_2400_RAW16_OPTION_BITS 2
#define _HRT_CSS_RECEIVER_2400_RAW16_EN_IDX 8
#define _HRT_CSS_RECEIVER_2400_RAW16_EN_BITS 1
/* These hsync and vsync values are for HSS simulation only */
#define _HRT_CSS_RECEIVER_2400_HSYNC_VAL (1<<16)
#define _HRT_CSS_RECEIVER_2400_VSYNC_VAL (1<<17)
#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_WIDTH 28
#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_LSB 0
#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_MSB (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_LSB + CSS_RECEIVER_DATA_OUT - 1)
#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_VAL_BIT (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_MSB + 1)
#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_LSB (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_VAL_BIT + 1)
#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_MSB (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_LSB + CSS_RECEIVER_DATA_OUT - 1)
#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_VAL_BIT (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_MSB + 1)
#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_SOP_BIT (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_VAL_BIT + 1)
#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_EOP_BIT (_HRT_CSS_RECEIVER_2400_BE_STREAMING_SOP_BIT + 1)
// SH Backend Register IDs
#define _HRT_CSS_RECEIVER_2400_BE_GSP_ACC_OVL_REG_IDX 0
#define _HRT_CSS_RECEIVER_2400_BE_SRST_REG_IDX 1
#define _HRT_CSS_RECEIVER_2400_BE_TWO_PPC_REG_IDX 2
#define _HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG0_IDX 3
#define _HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG1_IDX 4
#define _HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG2_IDX 5
#define _HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG3_IDX 6
#define _HRT_CSS_RECEIVER_2400_BE_SEL_REG_IDX 7
#define _HRT_CSS_RECEIVER_2400_BE_RAW16_CONFIG_REG_IDX 8
#define _HRT_CSS_RECEIVER_2400_BE_RAW18_CONFIG_REG_IDX 9
#define _HRT_CSS_RECEIVER_2400_BE_FORCE_RAW8_REG_IDX 10
#define _HRT_CSS_RECEIVER_2400_BE_IRQ_STATUS_REG_IDX 11
#define _HRT_CSS_RECEIVER_2400_BE_IRQ_CLEAR_REG_IDX 12
#define _HRT_CSS_RECEIVER_2400_BE_CUST_EN_REG_IDX 13
#define _HRT_CSS_RECEIVER_2400_BE_CUST_DATA_STATE_REG_IDX 14 /* Data State 0,1,2 config */
#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S0P0_REG_IDX 15 /* Pixel Extractor config for Data State 0 & Pix 0 */
#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S0P1_REG_IDX 16 /* Pixel Extractor config for Data State 0 & Pix 1 */
#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S0P2_REG_IDX 17 /* Pixel Extractor config for Data State 0 & Pix 2 */
#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S0P3_REG_IDX 18 /* Pixel Extractor config for Data State 0 & Pix 3 */
#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S1P0_REG_IDX 19 /* Pixel Extractor config for Data State 1 & Pix 0 */
#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S1P1_REG_IDX 20 /* Pixel Extractor config for Data State 1 & Pix 1 */
#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S1P2_REG_IDX 21 /* Pixel Extractor config for Data State 1 & Pix 2 */
#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S1P3_REG_IDX 22 /* Pixel Extractor config for Data State 1 & Pix 3 */
#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S2P0_REG_IDX 23 /* Pixel Extractor config for Data State 2 & Pix 0 */
#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S2P1_REG_IDX 24 /* Pixel Extractor config for Data State 2 & Pix 1 */
#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S2P2_REG_IDX 25 /* Pixel Extractor config for Data State 2 & Pix 2 */
#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S2P3_REG_IDX 26 /* Pixel Extractor config for Data State 2 & Pix 3 */
#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_VALID_EOP_REG_IDX 27 /* Pixel Valid & EoP config for Pix 0,1,2,3 */
#define _HRT_CSS_RECEIVER_2400_BE_NOF_REGISTERS 28
#define _HRT_CSS_RECEIVER_2400_BE_SRST_HE 0
#define _HRT_CSS_RECEIVER_2400_BE_SRST_RCF 1
#define _HRT_CSS_RECEIVER_2400_BE_SRST_PF 2
#define _HRT_CSS_RECEIVER_2400_BE_SRST_SM 3
#define _HRT_CSS_RECEIVER_2400_BE_SRST_PD 4
#define _HRT_CSS_RECEIVER_2400_BE_SRST_SD 5
#define _HRT_CSS_RECEIVER_2400_BE_SRST_OT 6
#define _HRT_CSS_RECEIVER_2400_BE_SRST_BC 7
#define _HRT_CSS_RECEIVER_2400_BE_SRST_WIDTH 8
#endif /* _css_receiver_2400_defs_h_ */

36
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/defs.h
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@ -1,36 +0,0 @@
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _HRT_DEFS_H_
#define _HRT_DEFS_H_
#ifndef HRTCAT
#define _HRTCAT(m, n) m##n
#define HRTCAT(m, n) _HRTCAT(m, n)
#endif
#ifndef HRTSTR
#define _HRTSTR(x) #x
#define HRTSTR(x) _HRTSTR(x)
#endif
#ifndef HRTMIN
#define HRTMIN(a, b) (((a) < (b)) ? (a) : (b))
#endif
#ifndef HRTMAX
#define HRTMAX(a, b) (((a) > (b)) ? (a) : (b))
#endif
#endif /* _HRT_DEFS_H_ */

199
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/dma_v2_defs.h
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@ -1,199 +0,0 @@
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _dma_v2_defs_h
#define _dma_v2_defs_h
#define _DMA_V2_NUM_CHANNELS_ID MaxNumChannels
#define _DMA_V2_CONNECTIONS_ID Connections
#define _DMA_V2_DEV_ELEM_WIDTHS_ID DevElemWidths
#define _DMA_V2_DEV_FIFO_DEPTH_ID DevFifoDepth
#define _DMA_V2_DEV_FIFO_RD_LAT_ID DevFifoRdLat
#define _DMA_V2_DEV_FIFO_LAT_BYPASS_ID DevFifoRdLatBypass
#define _DMA_V2_DEV_NO_BURST_ID DevNoBurst
#define _DMA_V2_DEV_RD_ACCEPT_ID DevRdAccept
#define _DMA_V2_DEV_SRMD_ID DevSRMD
#define _DMA_V2_DEV_HAS_CRUN_ID CRunMasters
#define _DMA_V2_CTRL_ACK_FIFO_DEPTH_ID CtrlAckFifoDepth
#define _DMA_V2_CMD_FIFO_DEPTH_ID CommandFifoDepth
#define _DMA_V2_CMD_FIFO_RD_LAT_ID CommandFifoRdLat
#define _DMA_V2_CMD_FIFO_LAT_BYPASS_ID CommandFifoRdLatBypass
#define _DMA_V2_NO_PACK_ID has_no_pack
#define _DMA_V2_REG_ALIGN 4
#define _DMA_V2_REG_ADDR_BITS 2
/* Command word */
#define _DMA_V2_CMD_IDX 0
#define _DMA_V2_CMD_BITS 6
#define _DMA_V2_CHANNEL_IDX (_DMA_V2_CMD_IDX + _DMA_V2_CMD_BITS)
#define _DMA_V2_CHANNEL_BITS 5
/* The command to set a parameter contains the PARAM field next */
#define _DMA_V2_PARAM_IDX (_DMA_V2_CHANNEL_IDX + _DMA_V2_CHANNEL_BITS)
#define _DMA_V2_PARAM_BITS 4
/* Commands to read, write or init specific blocks contain these
three values */
#define _DMA_V2_SPEC_DEV_A_XB_IDX (_DMA_V2_CHANNEL_IDX + _DMA_V2_CHANNEL_BITS)
#define _DMA_V2_SPEC_DEV_A_XB_BITS 8
#define _DMA_V2_SPEC_DEV_B_XB_IDX (_DMA_V2_SPEC_DEV_A_XB_IDX + _DMA_V2_SPEC_DEV_A_XB_BITS)
#define _DMA_V2_SPEC_DEV_B_XB_BITS 8
#define _DMA_V2_SPEC_YB_IDX (_DMA_V2_SPEC_DEV_B_XB_IDX + _DMA_V2_SPEC_DEV_B_XB_BITS)
#define _DMA_V2_SPEC_YB_BITS (32-_DMA_V2_SPEC_DEV_B_XB_BITS-_DMA_V2_SPEC_DEV_A_XB_BITS-_DMA_V2_CMD_BITS-_DMA_V2_CHANNEL_BITS)
/* */
#define _DMA_V2_CMD_CTRL_IDX 4
#define _DMA_V2_CMD_CTRL_BITS 4
/* Packing setup word */
#define _DMA_V2_CONNECTION_IDX 0
#define _DMA_V2_CONNECTION_BITS 4
#define _DMA_V2_EXTENSION_IDX (_DMA_V2_CONNECTION_IDX + _DMA_V2_CONNECTION_BITS)
#define _DMA_V2_EXTENSION_BITS 1
/* Elements packing word */
#define _DMA_V2_ELEMENTS_IDX 0
#define _DMA_V2_ELEMENTS_BITS 8
#define _DMA_V2_LEFT_CROPPING_IDX (_DMA_V2_ELEMENTS_IDX + _DMA_V2_ELEMENTS_BITS)
#define _DMA_V2_LEFT_CROPPING_BITS 8
#define _DMA_V2_WIDTH_IDX 0
#define _DMA_V2_WIDTH_BITS 16
#define _DMA_V2_HEIGHT_IDX 0
#define _DMA_V2_HEIGHT_BITS 16
#define _DMA_V2_STRIDE_IDX 0
#define _DMA_V2_STRIDE_BITS 32
/* Command IDs */
#define _DMA_V2_MOVE_B2A_COMMAND 0
#define _DMA_V2_MOVE_B2A_BLOCK_COMMAND 1
#define _DMA_V2_MOVE_B2A_NO_SYNC_CHK_COMMAND 2
#define _DMA_V2_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND 3
#define _DMA_V2_MOVE_A2B_COMMAND 4
#define _DMA_V2_MOVE_A2B_BLOCK_COMMAND 5
#define _DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND 6
#define _DMA_V2_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND 7
#define _DMA_V2_INIT_A_COMMAND 8
#define _DMA_V2_INIT_A_BLOCK_COMMAND 9
#define _DMA_V2_INIT_A_NO_SYNC_CHK_COMMAND 10
#define _DMA_V2_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND 11
#define _DMA_V2_INIT_B_COMMAND 12
#define _DMA_V2_INIT_B_BLOCK_COMMAND 13
#define _DMA_V2_INIT_B_NO_SYNC_CHK_COMMAND 14
#define _DMA_V2_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND 15
#define _DMA_V2_NO_ACK_MOVE_B2A_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_B2A_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_MOVE_A2B_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_INIT_A_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_A_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_INIT_B_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_B_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_CONFIG_CHANNEL_COMMAND 32
#define _DMA_V2_SET_CHANNEL_PARAM_COMMAND 33
#define _DMA_V2_SET_CRUN_COMMAND 62
/* Channel Parameter IDs */
#define _DMA_V2_PACKING_SETUP_PARAM 0
#define _DMA_V2_STRIDE_A_PARAM 1
#define _DMA_V2_ELEM_CROPPING_A_PARAM 2
#define _DMA_V2_WIDTH_A_PARAM 3
#define _DMA_V2_STRIDE_B_PARAM 4
#define _DMA_V2_ELEM_CROPPING_B_PARAM 5
#define _DMA_V2_WIDTH_B_PARAM 6
#define _DMA_V2_HEIGHT_PARAM 7
#define _DMA_V2_QUEUED_CMDS 8
/* Parameter Constants */
#define _DMA_V2_ZERO_EXTEND 0
#define _DMA_V2_SIGN_EXTEND 1
/* SLAVE address map */
#define _DMA_V2_SEL_FSM_CMD 0
#define _DMA_V2_SEL_CH_REG 1
#define _DMA_V2_SEL_CONN_GROUP 2
#define _DMA_V2_SEL_DEV_INTERF 3
#define _DMA_V2_ADDR_SEL_COMP_IDX 12
#define _DMA_V2_ADDR_SEL_COMP_BITS 4
#define _DMA_V2_ADDR_SEL_CH_REG_IDX 2
#define _DMA_V2_ADDR_SEL_CH_REG_BITS 6
#define _DMA_V2_ADDR_SEL_PARAM_IDX (_DMA_V2_ADDR_SEL_CH_REG_BITS+_DMA_V2_ADDR_SEL_CH_REG_IDX)
#define _DMA_V2_ADDR_SEL_PARAM_BITS 4
#define _DMA_V2_ADDR_SEL_GROUP_COMP_IDX 2
#define _DMA_V2_ADDR_SEL_GROUP_COMP_BITS 6
#define _DMA_V2_ADDR_SEL_GROUP_COMP_INFO_IDX (_DMA_V2_ADDR_SEL_GROUP_COMP_BITS + _DMA_V2_ADDR_SEL_GROUP_COMP_IDX)
#define _DMA_V2_ADDR_SEL_GROUP_COMP_INFO_BITS 4
#define _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_IDX 2
#define _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_BITS 6
#define _DMA_V2_ADDR_SEL_DEV_INTERF_INFO_IDX (_DMA_V2_ADDR_SEL_DEV_INTERF_IDX_IDX+_DMA_V2_ADDR_SEL_DEV_INTERF_IDX_BITS)
#define _DMA_V2_ADDR_SEL_DEV_INTERF_INFO_BITS 4
#define _DMA_V2_FSM_GROUP_CMD_IDX 0
#define _DMA_V2_FSM_GROUP_ADDR_SRC_IDX 1
#define _DMA_V2_FSM_GROUP_ADDR_DEST_IDX 2
#define _DMA_V2_FSM_GROUP_CMD_CTRL_IDX 3
#define _DMA_V2_FSM_GROUP_FSM_CTRL_IDX 4
#define _DMA_V2_FSM_GROUP_FSM_PACK_IDX 5
#define _DMA_V2_FSM_GROUP_FSM_REQ_IDX 6
#define _DMA_V2_FSM_GROUP_FSM_WR_IDX 7
#define _DMA_V2_FSM_GROUP_FSM_CTRL_STATE_IDX 0
#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_DEV_IDX 1
#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_ADDR_IDX 2
#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_STRIDE_IDX 3
#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_XB_IDX 4
#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_YB_IDX 5
#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_REQ_DEV_IDX 6
#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_DEV_IDX 7
#define _DMA_V2_FSM_GROUP_FSM_CTRL_WR_ADDR_IDX 8
#define _DMA_V2_FSM_GROUP_FSM_CTRL_WR_STRIDE_IDX 9
#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_REQ_XB_IDX 10
#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_YB_IDX 11
#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_XB_IDX 12
#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_ELEM_REQ_IDX 13
#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_ELEM_WR_IDX 14
#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_S_Z_IDX 15
#define _DMA_V2_FSM_GROUP_FSM_CTRL_CMD_CTRL_IDX 15
#define _DMA_V2_FSM_GROUP_FSM_PACK_STATE_IDX 0
#define _DMA_V2_FSM_GROUP_FSM_PACK_CNT_YB_IDX 1
#define _DMA_V2_FSM_GROUP_FSM_PACK_CNT_XB_REQ_IDX 2
#define _DMA_V2_FSM_GROUP_FSM_PACK_CNT_XB_WR_IDX 3
#define _DMA_V2_FSM_GROUP_FSM_REQ_STATE_IDX 0
#define _DMA_V2_FSM_GROUP_FSM_REQ_CNT_YB_IDX 1
#define _DMA_V2_FSM_GROUP_FSM_REQ_CNT_XB_IDX 2
#define _DMA_V2_FSM_GROUP_FSM_REQ_XB_REMAINING_IDX 3
#define _DMA_V2_FSM_GROUP_FSM_REQ_CNT_BURST_IDX 4
#define _DMA_V2_FSM_GROUP_FSM_WR_STATE_IDX 0
#define _DMA_V2_FSM_GROUP_FSM_WR_CNT_YB_IDX 1
#define _DMA_V2_FSM_GROUP_FSM_WR_CNT_XB_IDX 2
#define _DMA_V2_FSM_GROUP_FSM_WR_XB_REMAINING_IDX 3
#define _DMA_V2_FSM_GROUP_FSM_WR_CNT_BURST_IDX 4
#define _DMA_V2_DEV_INTERF_REQ_SIDE_STATUS_IDX 0
#define _DMA_V2_DEV_INTERF_SEND_SIDE_STATUS_IDX 1
#define _DMA_V2_DEV_INTERF_FIFO_STATUS_IDX 2
#define _DMA_V2_DEV_INTERF_REQ_ONLY_COMPLETE_BURST_IDX 3
#define _DMA_V2_DEV_INTERF_MAX_BURST_IDX 4
#define _DMA_V2_DEV_INTERF_CHK_ADDR_ALIGN 5
#endif /* _dma_v2_defs_h */

170
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/gdc_v2_defs.h
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/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef HRT_GDC_v2_defs_h_
#define HRT_GDC_v2_defs_h_
#define HRT_GDC_IS_V2
#define HRT_GDC_N 1024 /* Top-level design constant, equal to the number of entries in the LUT */
#define HRT_GDC_FRAC_BITS 10 /* Number of fractional bits in the GDC block, driven by the size of the LUT */
#define HRT_GDC_BLI_FRAC_BITS 4 /* Number of fractional bits for the bi-linear interpolation type */
#define HRT_GDC_BLI_COEF_ONE (1 << HRT_GDC_BLI_FRAC_BITS)
#define HRT_GDC_BCI_COEF_BITS 14 /* 14 bits per coefficient */
#define HRT_GDC_BCI_COEF_ONE (1 << (HRT_GDC_BCI_COEF_BITS-2)) /* We represent signed 10 bit coefficients. */
/* The supported range is [-256, .., +256] */
/* in 14-bit signed notation, */
/* We need all ten bits (MSB must be zero). */
/* -s is inserted to solve this issue, and */
/* therefore "1" is equal to +256. */
#define HRT_GDC_BCI_COEF_MASK ((1 << HRT_GDC_BCI_COEF_BITS) - 1)
#define HRT_GDC_LUT_BYTES (HRT_GDC_N*4*2) /* 1024 addresses, 4 coefficients per address, */
/* 2 bytes per coefficient */
#define _HRT_GDC_REG_ALIGN 4
// 31 30 29 25 24 0
// |-----|---|--------|------------------------|
// | CMD | C | Reg_ID | Value |
// There are just two commands possible for the GDC block:
// 1 - Configure reg
// 0 - Data token
// C - Reserved bit
// Used in protocol to indicate whether it is C-run or other type of runs
// In case of C-run, this bit has a value of 1, for all the other runs, it is 0.
// Reg_ID - Address of the register to be configured
// Value - Value to store to the addressed register, maximum of 24 bits
// Configure reg command is not followed by any other token.
// The address of the register and the data to be filled in is contained in the same token
// When the first data token is received, it must be:
// 1. FRX and FRY (device configured in one of the scaling modes) ***DEFAULT MODE***, or,
// 2. P0'X (device configured in one of the tetragon modes)
// After the first data token is received, pre-defined number of tokens with the following meaning follow:
// 1. two tokens: SRC address ; DST address
// 2. nine tokens: P0'Y, .., P3'Y ; SRC address ; DST address
#define HRT_GDC_CONFIG_CMD 1
#define HRT_GDC_DATA_CMD 0
#define HRT_GDC_CMD_POS 31
#define HRT_GDC_CMD_BITS 1
#define HRT_GDC_CRUN_POS 30
#define HRT_GDC_REG_ID_POS 25
#define HRT_GDC_REG_ID_BITS 5
#define HRT_GDC_DATA_POS 0
#define HRT_GDC_DATA_BITS 25
#define HRT_GDC_FRYIPXFRX_BITS 26
#define HRT_GDC_P0X_BITS 23
#define HRT_GDC_MAX_OXDIM (8192-64)
#define HRT_GDC_MAX_OYDIM 4095
#define HRT_GDC_MAX_IXDIM (8192-64)
#define HRT_GDC_MAX_IYDIM 4095
#define HRT_GDC_MAX_DS_FAC 16
#define HRT_GDC_MAX_DX (HRT_GDC_MAX_DS_FAC*HRT_GDC_N - 1)
#define HRT_GDC_MAX_DY HRT_GDC_MAX_DX
/* GDC lookup tables entries are 10 bits values, but they're
stored 2 by 2 as 32 bit values, yielding 16 bits per entry.
A GDC lookup table contains 64 * 4 elements */
#define HRT_GDC_PERF_1_1_pix 0
#define HRT_GDC_PERF_2_1_pix 1
#define HRT_GDC_PERF_1_2_pix 2
#define HRT_GDC_PERF_2_2_pix 3
#define HRT_GDC_NND_MODE 0
#define HRT_GDC_BLI_MODE 1
#define HRT_GDC_BCI_MODE 2
#define HRT_GDC_LUT_MODE 3
#define HRT_GDC_SCAN_STB 0
#define HRT_GDC_SCAN_STR 1
#define HRT_GDC_MODE_SCALING 0
#define HRT_GDC_MODE_TETRAGON 1
#define HRT_GDC_LUT_COEFF_OFFSET 16
#define HRT_GDC_FRY_BIT_OFFSET 16
// FRYIPXFRX is the only register where we store two values in one field,
// to save one token in the scaling protocol.
// Like this, we have three tokens in the scaling protocol,
// Otherwise, we would have had four.
// The register bit-map is:
// 31 26 25 16 15 10 9 0
// |------|----------|------|----------|
// | XXXX | FRY | IPX | FRX |
#define HRT_GDC_CE_FSM0_POS 0
#define HRT_GDC_CE_FSM0_LEN 2
#define HRT_GDC_CE_OPY_POS 2
#define HRT_GDC_CE_OPY_LEN 14
#define HRT_GDC_CE_OPX_POS 16
#define HRT_GDC_CE_OPX_LEN 16
// CHK_ENGINE register bit-map:
// 31 16 15 2 1 0
// |----------------|-----------|----|
// | OPX | OPY |FSM0|
// However, for the time being at least,
// this implementation is meaningless in hss model,
// So, we just return 0
#define HRT_GDC_CHK_ENGINE_IDX 0
#define HRT_GDC_WOIX_IDX 1
#define HRT_GDC_WOIY_IDX 2
#define HRT_GDC_BPP_IDX 3
#define HRT_GDC_FRYIPXFRX_IDX 4
#define HRT_GDC_OXDIM_IDX 5
#define HRT_GDC_OYDIM_IDX 6
#define HRT_GDC_SRC_ADDR_IDX 7
#define HRT_GDC_SRC_END_ADDR_IDX 8
#define HRT_GDC_SRC_WRAP_ADDR_IDX 9
#define HRT_GDC_SRC_STRIDE_IDX 10
#define HRT_GDC_DST_ADDR_IDX 11
#define HRT_GDC_DST_STRIDE_IDX 12
#define HRT_GDC_DX_IDX 13
#define HRT_GDC_DY_IDX 14
#define HRT_GDC_P0X_IDX 15
#define HRT_GDC_P0Y_IDX 16
#define HRT_GDC_P1X_IDX 17
#define HRT_GDC_P1Y_IDX 18
#define HRT_GDC_P2X_IDX 19
#define HRT_GDC_P2Y_IDX 20
#define HRT_GDC_P3X_IDX 21
#define HRT_GDC_P3Y_IDX 22
#define HRT_GDC_PERF_POINT_IDX 23 // 1x1 ; 1x2 ; 2x1 ; 2x2 pixels per cc
#define HRT_GDC_INTERP_TYPE_IDX 24 // NND ; BLI ; BCI ; LUT
#define HRT_GDC_SCAN_IDX 25 // 0 = STB (Slide To Bottom) ; 1 = STR (Slide To Right)
#define HRT_GDC_PROC_MODE_IDX 26 // 0 = Scaling ; 1 = Tetragon
#define HRT_GDC_LUT_IDX 32
#endif /* HRT_GDC_v2_defs_h_ */

36
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/gp_timer_defs.h
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@ -1,36 +0,0 @@
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _gp_timer_defs_h
#define _gp_timer_defs_h
#define _HRT_GP_TIMER_REG_ALIGN 4
#define HIVE_GP_TIMER_RESET_REG_IDX 0
#define HIVE_GP_TIMER_OVERALL_ENABLE_REG_IDX 1
#define HIVE_GP_TIMER_ENABLE_REG_IDX(timer) (HIVE_GP_TIMER_OVERALL_ENABLE_REG_IDX + 1 + timer)
#define HIVE_GP_TIMER_VALUE_REG_IDX(timer,timers) (HIVE_GP_TIMER_ENABLE_REG_IDX(timers) + timer)
#define HIVE_GP_TIMER_COUNT_TYPE_REG_IDX(timer,timers) (HIVE_GP_TIMER_VALUE_REG_IDX(timers, timers) + timer)
#define HIVE_GP_TIMER_SIGNAL_SELECT_REG_IDX(timer,timers) (HIVE_GP_TIMER_COUNT_TYPE_REG_IDX(timers, timers) + timer)
#define HIVE_GP_TIMER_IRQ_TRIGGER_VALUE_REG_IDX(irq,timers) (HIVE_GP_TIMER_SIGNAL_SELECT_REG_IDX(timers, timers) + irq)
#define HIVE_GP_TIMER_IRQ_TIMER_SELECT_REG_IDX(irq,timers,irqs) (HIVE_GP_TIMER_IRQ_TRIGGER_VALUE_REG_IDX(irqs, timers) + irq)
#define HIVE_GP_TIMER_IRQ_ENABLE_REG_IDX(irq,timers,irqs) (HIVE_GP_TIMER_IRQ_TIMER_SELECT_REG_IDX(irqs, timers, irqs) + irq)
#define HIVE_GP_TIMER_COUNT_TYPE_HIGH 0
#define HIVE_GP_TIMER_COUNT_TYPE_LOW 1
#define HIVE_GP_TIMER_COUNT_TYPE_POSEDGE 2
#define HIVE_GP_TIMER_COUNT_TYPE_NEGEDGE 3
#define HIVE_GP_TIMER_COUNT_TYPES 4
#endif /* _gp_timer_defs_h */

42
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/gpio_block_defs.h
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@ -1,42 +0,0 @@
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _gpio_block_defs_h_
#define _gpio_block_defs_h_
#define _HRT_GPIO_BLOCK_REG_ALIGN 4
/* R/W registers */
#define _gpio_block_reg_do_e 0
#define _gpio_block_reg_do_select 1
#define _gpio_block_reg_do_0 2
#define _gpio_block_reg_do_1 3
#define _gpio_block_reg_do_pwm_cnt_0 4
#define _gpio_block_reg_do_pwm_cnt_1 5
#define _gpio_block_reg_do_pwm_cnt_2 6
#define _gpio_block_reg_do_pwm_cnt_3 7
#define _gpio_block_reg_do_pwm_main_cnt 8
#define _gpio_block_reg_do_pwm_enable 9
#define _gpio_block_reg_di_debounce_sel 10
#define _gpio_block_reg_di_debounce_cnt_0 11
#define _gpio_block_reg_di_debounce_cnt_1 12
#define _gpio_block_reg_di_debounce_cnt_2 13
#define _gpio_block_reg_di_debounce_cnt_3 14
#define _gpio_block_reg_di_active_level 15
/* read-only registers */
#define _gpio_block_reg_di 16
#endif /* _gpio_block_defs_h_ */

416
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/hive_isp_css_defs.h
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@ -1,416 +0,0 @@
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _hive_isp_css_defs_h__
#define _hive_isp_css_defs_h__
#define HIVE_ISP_CSS_IS_2400B0_SYSTEM
#define HIVE_ISP_CTRL_DATA_WIDTH 32
#define HIVE_ISP_CTRL_ADDRESS_WIDTH 32
#define HIVE_ISP_CTRL_MAX_BURST_SIZE 1
#define HIVE_ISP_DDR_ADDRESS_WIDTH 36
#define HIVE_ISP_HOST_MAX_BURST_SIZE 8 /* host supports bursts in order to prevent repeating DDRAM accesses */
#define HIVE_ISP_NUM_GPIO_PINS 12
/* This list of vector num_elems/elem_bits pairs is valid both in C as initializer
and in the DMA parameter list */
#define HIVE_ISP_DDR_DMA_SPECS {{32, 8}, {16, 16}, {18, 14}, {25, 10}, {21, 12}}
#define HIVE_ISP_DDR_WORD_BITS 256
#define HIVE_ISP_DDR_WORD_BYTES (HIVE_ISP_DDR_WORD_BITS/8)
#define HIVE_ISP_DDR_BYTES (512 * 1024 * 1024) /* hss only */
#define HIVE_ISP_DDR_BYTES_RTL (127 * 1024 * 1024) /* RTL only */
#define HIVE_ISP_DDR_SMALL_BYTES (128 * 256 / 8)
#define HIVE_ISP_PAGE_SHIFT 12
#define HIVE_ISP_PAGE_SIZE (1<<HIVE_ISP_PAGE_SHIFT)
#define CSS_DDR_WORD_BITS HIVE_ISP_DDR_WORD_BITS
#define CSS_DDR_WORD_BYTES HIVE_ISP_DDR_WORD_BYTES
/* If HIVE_ISP_DDR_BASE_OFFSET is set to a non-zero value, the wide bus just before the DDRAM gets an extra dummy port where */
/* address range 0 .. HIVE_ISP_DDR_BASE_OFFSET-1 maps onto. This effectively creates an offset for the DDRAM from system perspective */
#define HIVE_ISP_DDR_BASE_OFFSET 0x120000000 /* 0x200000 */
#define HIVE_DMA_ISP_BUS_CONN 0
#define HIVE_DMA_ISP_DDR_CONN 1
#define HIVE_DMA_BUS_DDR_CONN 2
#define HIVE_DMA_ISP_MASTER master_port0
#define HIVE_DMA_BUS_MASTER master_port1
#define HIVE_DMA_DDR_MASTER master_port2
#define HIVE_DMA_NUM_CHANNELS 32 /* old value was 8 */
#define HIVE_DMA_CMD_FIFO_DEPTH 24 /* old value was 12 */
#define HIVE_IF_PIXEL_WIDTH 12
#define HIVE_MMU_TLB_SETS 8
#define HIVE_MMU_TLB_SET_BLOCKS 8
#define HIVE_MMU_TLB_BLOCK_ELEMENTS 8
#define HIVE_MMU_PAGE_TABLE_LEVELS 2
#define HIVE_MMU_PAGE_BYTES HIVE_ISP_PAGE_SIZE
#define HIVE_ISP_CH_ID_BITS 2
#define HIVE_ISP_FMT_TYPE_BITS 5
#define HIVE_ISP_ISEL_SEL_BITS 2
#define HIVE_GP_REGS_SDRAM_WAKEUP_IDX 0
#define HIVE_GP_REGS_IDLE_IDX 1
#define HIVE_GP_REGS_IRQ_0_IDX 2
#define HIVE_GP_REGS_IRQ_1_IDX 3
#define HIVE_GP_REGS_SP_STREAM_STAT_IDX 4
#define HIVE_GP_REGS_SP_STREAM_STAT_B_IDX 5
#define HIVE_GP_REGS_ISP_STREAM_STAT_IDX 6
#define HIVE_GP_REGS_MOD_STREAM_STAT_IDX 7
#define HIVE_GP_REGS_SP_STREAM_STAT_IRQ_COND_IDX 8
#define HIVE_GP_REGS_SP_STREAM_STAT_B_IRQ_COND_IDX 9
#define HIVE_GP_REGS_ISP_STREAM_STAT_IRQ_COND_IDX 10
#define HIVE_GP_REGS_MOD_STREAM_STAT_IRQ_COND_IDX 11
#define HIVE_GP_REGS_SP_STREAM_STAT_IRQ_ENABLE_IDX 12
#define HIVE_GP_REGS_SP_STREAM_STAT_B_IRQ_ENABLE_IDX 13
#define HIVE_GP_REGS_ISP_STREAM_STAT_IRQ_ENABLE_IDX 14
#define HIVE_GP_REGS_MOD_STREAM_STAT_IRQ_ENABLE_IDX 15
#define HIVE_GP_REGS_SWITCH_PRIM_IF_IDX 16
#define HIVE_GP_REGS_SWITCH_GDC1_IDX 17
#define HIVE_GP_REGS_SWITCH_GDC2_IDX 18
#define HIVE_GP_REGS_SRST_IDX 19
#define HIVE_GP_REGS_SLV_REG_SRST_IDX 20
#define HIVE_GP_REGS_VISA_REG_IDX 21
/* Bit numbers of the soft reset register */
#define HIVE_GP_REGS_SRST_ISYS_CBUS 0
#define HIVE_GP_REGS_SRST_ISEL_CBUS 1
#define HIVE_GP_REGS_SRST_IFMT_CBUS 2
#define HIVE_GP_REGS_SRST_GPDEV_CBUS 3
#define HIVE_GP_REGS_SRST_GPIO 4
#define HIVE_GP_REGS_SRST_TC 5
#define HIVE_GP_REGS_SRST_GPTIMER 6
#define HIVE_GP_REGS_SRST_FACELLFIFOS 7
#define HIVE_GP_REGS_SRST_D_OSYS 8
#define HIVE_GP_REGS_SRST_IFT_SEC_PIPE 9
#define HIVE_GP_REGS_SRST_GDC1 10
#define HIVE_GP_REGS_SRST_GDC2 11
#define HIVE_GP_REGS_SRST_VEC_BUS 12
#define HIVE_GP_REGS_SRST_ISP 13
#define HIVE_GP_REGS_SRST_SLV_GRP_BUS 14
#define HIVE_GP_REGS_SRST_DMA 15
#define HIVE_GP_REGS_SRST_SF_ISP_SP 16
#define HIVE_GP_REGS_SRST_SF_PIF_CELLS 17
#define HIVE_GP_REGS_SRST_SF_SIF_SP 18
#define HIVE_GP_REGS_SRST_SF_MC_SP 19
#define HIVE_GP_REGS_SRST_SF_ISYS_SP 20
#define HIVE_GP_REGS_SRST_SF_DMA_CELLS 21
#define HIVE_GP_REGS_SRST_SF_GDC1_CELLS 22
#define HIVE_GP_REGS_SRST_SF_GDC2_CELLS 23
#define HIVE_GP_REGS_SRST_SP 24
#define HIVE_GP_REGS_SRST_OCP2CIO 25
#define HIVE_GP_REGS_SRST_NBUS 26
#define HIVE_GP_REGS_SRST_HOST12BUS 27
#define HIVE_GP_REGS_SRST_WBUS 28
#define HIVE_GP_REGS_SRST_IC_OSYS 29
#define HIVE_GP_REGS_SRST_WBUS_IC 30
/* Bit numbers of the slave register soft reset register */
#define HIVE_GP_REGS_SLV_REG_SRST_DMA 0
#define HIVE_GP_REGS_SLV_REG_SRST_GDC1 1
#define HIVE_GP_REGS_SLV_REG_SRST_GDC2 2
/* order of the input bits for the irq controller */
#define HIVE_GP_DEV_IRQ_GPIO_PIN_0_BIT_ID 0
#define HIVE_GP_DEV_IRQ_GPIO_PIN_1_BIT_ID 1
#define HIVE_GP_DEV_IRQ_GPIO_PIN_2_BIT_ID 2
#define HIVE_GP_DEV_IRQ_GPIO_PIN_3_BIT_ID 3
#define HIVE_GP_DEV_IRQ_GPIO_PIN_4_BIT_ID 4
#define HIVE_GP_DEV_IRQ_GPIO_PIN_5_BIT_ID 5
#define HIVE_GP_DEV_IRQ_GPIO_PIN_6_BIT_ID 6
#define HIVE_GP_DEV_IRQ_GPIO_PIN_7_BIT_ID 7
#define HIVE_GP_DEV_IRQ_GPIO_PIN_8_BIT_ID 8
#define HIVE_GP_DEV_IRQ_GPIO_PIN_9_BIT_ID 9
#define HIVE_GP_DEV_IRQ_GPIO_PIN_10_BIT_ID 10
#define HIVE_GP_DEV_IRQ_GPIO_PIN_11_BIT_ID 11
#define HIVE_GP_DEV_IRQ_SP_BIT_ID 12
#define HIVE_GP_DEV_IRQ_ISP_BIT_ID 13
#define HIVE_GP_DEV_IRQ_ISYS_BIT_ID 14
#define HIVE_GP_DEV_IRQ_ISEL_BIT_ID 15
#define HIVE_GP_DEV_IRQ_IFMT_BIT_ID 16
#define HIVE_GP_DEV_IRQ_SP_STREAM_MON_BIT_ID 17
#define HIVE_GP_DEV_IRQ_ISP_STREAM_MON_BIT_ID 18
#define HIVE_GP_DEV_IRQ_MOD_STREAM_MON_BIT_ID 19
#define HIVE_GP_DEV_IRQ_ISP_PMEM_ERROR_BIT_ID 20
#define HIVE_GP_DEV_IRQ_ISP_BAMEM_ERROR_BIT_ID 21
#define HIVE_GP_DEV_IRQ_ISP_DMEM_ERROR_BIT_ID 22
#define HIVE_GP_DEV_IRQ_SP_ICACHE_MEM_ERROR_BIT_ID 23
#define HIVE_GP_DEV_IRQ_SP_DMEM_ERROR_BIT_ID 24
#define HIVE_GP_DEV_IRQ_MMU_CACHE_MEM_ERROR_BIT_ID 25
#define HIVE_GP_DEV_IRQ_GP_TIMER_0_BIT_ID 26
#define HIVE_GP_DEV_IRQ_GP_TIMER_1_BIT_ID 27
#define HIVE_GP_DEV_IRQ_SW_PIN_0_BIT_ID 28
#define HIVE_GP_DEV_IRQ_SW_PIN_1_BIT_ID 29
#define HIVE_GP_DEV_IRQ_DMA_BIT_ID 30
#define HIVE_GP_DEV_IRQ_SP_STREAM_MON_B_BIT_ID 31
#define HIVE_GP_REGS_NUM_SW_IRQ_REGS 2
/* order of the input bits for the timed controller */
#define HIVE_GP_DEV_TC_GPIO_PIN_0_BIT_ID 0
#define HIVE_GP_DEV_TC_GPIO_PIN_1_BIT_ID 1
#define HIVE_GP_DEV_TC_GPIO_PIN_2_BIT_ID 2
#define HIVE_GP_DEV_TC_GPIO_PIN_3_BIT_ID 3
#define HIVE_GP_DEV_TC_GPIO_PIN_4_BIT_ID 4
#define HIVE_GP_DEV_TC_GPIO_PIN_5_BIT_ID 5
#define HIVE_GP_DEV_TC_GPIO_PIN_6_BIT_ID 6
#define HIVE_GP_DEV_TC_GPIO_PIN_7_BIT_ID 7
#define HIVE_GP_DEV_TC_GPIO_PIN_8_BIT_ID 8
#define HIVE_GP_DEV_TC_GPIO_PIN_9_BIT_ID 9
#define HIVE_GP_DEV_TC_GPIO_PIN_10_BIT_ID 10
#define HIVE_GP_DEV_TC_GPIO_PIN_11_BIT_ID 11
#define HIVE_GP_DEV_TC_SP_BIT_ID 12
#define HIVE_GP_DEV_TC_ISP_BIT_ID 13
#define HIVE_GP_DEV_TC_ISYS_BIT_ID 14
#define HIVE_GP_DEV_TC_ISEL_BIT_ID 15
#define HIVE_GP_DEV_TC_IFMT_BIT_ID 16
#define HIVE_GP_DEV_TC_GP_TIMER_0_BIT_ID 17
#define HIVE_GP_DEV_TC_GP_TIMER_1_BIT_ID 18
#define HIVE_GP_DEV_TC_MIPI_SOL_BIT_ID 19
#define HIVE_GP_DEV_TC_MIPI_EOL_BIT_ID 20
#define HIVE_GP_DEV_TC_MIPI_SOF_BIT_ID 21
#define HIVE_GP_DEV_TC_MIPI_EOF_BIT_ID 22
#define HIVE_GP_DEV_TC_INPSYS_SM 23
/* definitions for the gp_timer block */
#define HIVE_GP_TIMER_0 0
#define HIVE_GP_TIMER_1 1
#define HIVE_GP_TIMER_2 2
#define HIVE_GP_TIMER_3 3
#define HIVE_GP_TIMER_4 4
#define HIVE_GP_TIMER_5 5
#define HIVE_GP_TIMER_6 6
#define HIVE_GP_TIMER_7 7
#define HIVE_GP_TIMER_NUM_COUNTERS 8
#define HIVE_GP_TIMER_IRQ_0 0
#define HIVE_GP_TIMER_IRQ_1 1
#define HIVE_GP_TIMER_NUM_IRQS 2
#define HIVE_GP_TIMER_GPIO_0_BIT_ID 0
#define HIVE_GP_TIMER_GPIO_1_BIT_ID 1
#define HIVE_GP_TIMER_GPIO_2_BIT_ID 2
#define HIVE_GP_TIMER_GPIO_3_BIT_ID 3
#define HIVE_GP_TIMER_GPIO_4_BIT_ID 4
#define HIVE_GP_TIMER_GPIO_5_BIT_ID 5
#define HIVE_GP_TIMER_GPIO_6_BIT_ID 6
#define HIVE_GP_TIMER_GPIO_7_BIT_ID 7
#define HIVE_GP_TIMER_GPIO_8_BIT_ID 8
#define HIVE_GP_TIMER_GPIO_9_BIT_ID 9
#define HIVE_GP_TIMER_GPIO_10_BIT_ID 10
#define HIVE_GP_TIMER_GPIO_11_BIT_ID 11
#define HIVE_GP_TIMER_INP_SYS_IRQ 12
#define HIVE_GP_TIMER_ISEL_IRQ 13
#define HIVE_GP_TIMER_IFMT_IRQ 14
#define HIVE_GP_TIMER_SP_STRMON_IRQ 15
#define HIVE_GP_TIMER_SP_B_STRMON_IRQ 16
#define HIVE_GP_TIMER_ISP_STRMON_IRQ 17
#define HIVE_GP_TIMER_MOD_STRMON_IRQ 18
#define HIVE_GP_TIMER_ISP_PMEM_ERROR_IRQ 19
#define HIVE_GP_TIMER_ISP_BAMEM_ERROR_IRQ 20
#define HIVE_GP_TIMER_ISP_DMEM_ERROR_IRQ 21
#define HIVE_GP_TIMER_SP_ICACHE_MEM_ERROR_IRQ 22
#define HIVE_GP_TIMER_SP_DMEM_ERROR_IRQ 23
#define HIVE_GP_TIMER_SP_OUT_RUN_DP 24
#define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I0 25
#define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I1 26
#define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I2 27
#define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I3 28
#define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I4 29
#define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I5 30
#define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I6 31
#define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I7 32
#define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I8 33
#define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I9 34
#define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I10 35
#define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I1_I0 36
#define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I2_I0 37
#define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I3_I0 38
#define HIVE_GP_TIMER_ISP_OUT_RUN_DP 39
#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I0_I0 40
#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I0_I1 41
#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I1_I0 42
#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I2_I0 43
#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I2_I1 44
#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I2_I2 45
#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I2_I3 46
#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I2_I4 47
#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I2_I5 48
#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I2_I6 49
#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I3_I0 50
#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I4_I0 51
#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I5_I0 52
#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I6_I0 53
#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I7_I0 54
#define HIVE_GP_TIMER_MIPI_SOL_BIT_ID 55
#define HIVE_GP_TIMER_MIPI_EOL_BIT_ID 56
#define HIVE_GP_TIMER_MIPI_SOF_BIT_ID 57
#define HIVE_GP_TIMER_MIPI_EOF_BIT_ID 58
#define HIVE_GP_TIMER_INPSYS_SM 59
/* port definitions for the streaming monitors */
/* port definititions SP streaming monitor, monitors the status of streaming ports at the SP side of the streaming FIFO's */
#define SP_STR_MON_PORT_SP2SIF 0
#define SP_STR_MON_PORT_SIF2SP 1
#define SP_STR_MON_PORT_SP2MC 2
#define SP_STR_MON_PORT_MC2SP 3
#define SP_STR_MON_PORT_SP2DMA 4
#define SP_STR_MON_PORT_DMA2SP 5
#define SP_STR_MON_PORT_SP2ISP 6
#define SP_STR_MON_PORT_ISP2SP 7
#define SP_STR_MON_PORT_SP2GPD 8
#define SP_STR_MON_PORT_FA2SP 9
#define SP_STR_MON_PORT_SP2ISYS 10
#define SP_STR_MON_PORT_ISYS2SP 11
#define SP_STR_MON_PORT_SP2PIFA 12
#define SP_STR_MON_PORT_PIFA2SP 13
#define SP_STR_MON_PORT_SP2PIFB 14
#define SP_STR_MON_PORT_PIFB2SP 15
#define SP_STR_MON_PORT_B_SP2GDC1 0
#define SP_STR_MON_PORT_B_GDC12SP 1
#define SP_STR_MON_PORT_B_SP2GDC2 2
#define SP_STR_MON_PORT_B_GDC22SP 3
/* previously used SP streaming monitor port identifiers, kept for backward compatibility */
#define SP_STR_MON_PORT_SND_SIF SP_STR_MON_PORT_SP2SIF
#define SP_STR_MON_PORT_RCV_SIF SP_STR_MON_PORT_SIF2SP
#define SP_STR_MON_PORT_SND_MC SP_STR_MON_PORT_SP2MC
#define SP_STR_MON_PORT_RCV_MC SP_STR_MON_PORT_MC2SP
#define SP_STR_MON_PORT_SND_DMA SP_STR_MON_PORT_SP2DMA
#define SP_STR_MON_PORT_RCV_DMA SP_STR_MON_PORT_DMA2SP
#define SP_STR_MON_PORT_SND_ISP SP_STR_MON_PORT_SP2ISP
#define SP_STR_MON_PORT_RCV_ISP SP_STR_MON_PORT_ISP2SP
#define SP_STR_MON_PORT_SND_GPD SP_STR_MON_PORT_SP2GPD
#define SP_STR_MON_PORT_RCV_GPD SP_STR_MON_PORT_FA2SP
/* Deprecated */
#define SP_STR_MON_PORT_SND_PIF SP_STR_MON_PORT_SP2PIFA
#define SP_STR_MON_PORT_RCV_PIF SP_STR_MON_PORT_PIFA2SP
#define SP_STR_MON_PORT_SND_PIFB SP_STR_MON_PORT_SP2PIFB
#define SP_STR_MON_PORT_RCV_PIFB SP_STR_MON_PORT_PIFB2SP
#define SP_STR_MON_PORT_SND_PIF_A SP_STR_MON_PORT_SP2PIFA
#define SP_STR_MON_PORT_RCV_PIF_A SP_STR_MON_PORT_PIFA2SP
#define SP_STR_MON_PORT_SND_PIF_B SP_STR_MON_PORT_SP2PIFB
#define SP_STR_MON_PORT_RCV_PIF_B SP_STR_MON_PORT_PIFB2SP
/* port definititions ISP streaming monitor, monitors the status of streaming ports at the ISP side of the streaming FIFO's */
#define ISP_STR_MON_PORT_ISP2PIFA 0
#define ISP_STR_MON_PORT_PIFA2ISP 1
#define ISP_STR_MON_PORT_ISP2PIFB 2
#define ISP_STR_MON_PORT_PIFB2ISP 3
#define ISP_STR_MON_PORT_ISP2DMA 4
#define ISP_STR_MON_PORT_DMA2ISP 5
#define ISP_STR_MON_PORT_ISP2GDC1 6
#define ISP_STR_MON_PORT_GDC12ISP 7
#define ISP_STR_MON_PORT_ISP2GDC2 8
#define ISP_STR_MON_PORT_GDC22ISP 9
#define ISP_STR_MON_PORT_ISP2GPD 10
#define ISP_STR_MON_PORT_FA2ISP 11
#define ISP_STR_MON_PORT_ISP2SP 12
#define ISP_STR_MON_PORT_SP2ISP 13
/* previously used ISP streaming monitor port identifiers, kept for backward compatibility */
#define ISP_STR_MON_PORT_SND_PIF_A ISP_STR_MON_PORT_ISP2PIFA
#define ISP_STR_MON_PORT_RCV_PIF_A ISP_STR_MON_PORT_PIFA2ISP
#define ISP_STR_MON_PORT_SND_PIF_B ISP_STR_MON_PORT_ISP2PIFB
#define ISP_STR_MON_PORT_RCV_PIF_B ISP_STR_MON_PORT_PIFB2ISP
#define ISP_STR_MON_PORT_SND_DMA ISP_STR_MON_PORT_ISP2DMA
#define ISP_STR_MON_PORT_RCV_DMA ISP_STR_MON_PORT_DMA2ISP
#define ISP_STR_MON_PORT_SND_GDC ISP_STR_MON_PORT_ISP2GDC1
#define ISP_STR_MON_PORT_RCV_GDC ISP_STR_MON_PORT_GDC12ISP
#define ISP_STR_MON_PORT_SND_GPD ISP_STR_MON_PORT_ISP2GPD
#define ISP_STR_MON_PORT_RCV_GPD ISP_STR_MON_PORT_FA2ISP
#define ISP_STR_MON_PORT_SND_SP ISP_STR_MON_PORT_ISP2SP
#define ISP_STR_MON_PORT_RCV_SP ISP_STR_MON_PORT_SP2ISP
/* port definititions MOD streaming monitor, monitors the status of streaming ports at the module side of the streaming FIFO's */
#define MOD_STR_MON_PORT_PIFA2CELLS 0
#define MOD_STR_MON_PORT_CELLS2PIFA 1
#define MOD_STR_MON_PORT_PIFB2CELLS 2
#define MOD_STR_MON_PORT_CELLS2PIFB 3
#define MOD_STR_MON_PORT_SIF2SP 4
#define MOD_STR_MON_PORT_SP2SIF 5
#define MOD_STR_MON_PORT_MC2SP 6
#define MOD_STR_MON_PORT_SP2MC 7
#define MOD_STR_MON_PORT_DMA2ISP 8
#define MOD_STR_MON_PORT_ISP2DMA 9
#define MOD_STR_MON_PORT_DMA2SP 10
#define MOD_STR_MON_PORT_SP2DMA 11
#define MOD_STR_MON_PORT_GDC12CELLS 12
#define MOD_STR_MON_PORT_CELLS2GDC1 13
#define MOD_STR_MON_PORT_GDC22CELLS 14
#define MOD_STR_MON_PORT_CELLS2GDC2 15
#define MOD_STR_MON_PORT_SND_PIF_A 0
#define MOD_STR_MON_PORT_RCV_PIF_A 1
#define MOD_STR_MON_PORT_SND_PIF_B 2
#define MOD_STR_MON_PORT_RCV_PIF_B 3
#define MOD_STR_MON_PORT_SND_SIF 4
#define MOD_STR_MON_PORT_RCV_SIF 5
#define MOD_STR_MON_PORT_SND_MC 6
#define MOD_STR_MON_PORT_RCV_MC 7
#define MOD_STR_MON_PORT_SND_DMA2ISP 8
#define MOD_STR_MON_PORT_RCV_DMA_FR_ISP 9
#define MOD_STR_MON_PORT_SND_DMA2SP 10
#define MOD_STR_MON_PORT_RCV_DMA_FR_SP 11
#define MOD_STR_MON_PORT_SND_GDC 12
#define MOD_STR_MON_PORT_RCV_GDC 13
/* testbench signals: */
/* testbench GP adapter register ids */
#define HIVE_TESTBENCH_GPIO_DATA_OUT_REG_IDX 0
#define HIVE_TESTBENCH_GPIO_DIR_OUT_REG_IDX 1
#define HIVE_TESTBENCH_IRQ_REG_IDX 2
#define HIVE_TESTBENCH_SDRAM_WAKEUP_REG_IDX 3
#define HIVE_TESTBENCH_IDLE_REG_IDX 4
#define HIVE_TESTBENCH_GPIO_DATA_IN_REG_IDX 5
#define HIVE_TESTBENCH_MIPI_BFM_EN_REG_IDX 6
#define HIVE_TESTBENCH_CSI_CONFIG_REG_IDX 7
#define HIVE_TESTBENCH_DDR_STALL_EN_REG_IDX 8
#define HIVE_TESTBENCH_ISP_PMEM_ERROR_IRQ_REG_IDX 9
#define HIVE_TESTBENCH_ISP_BAMEM_ERROR_IRQ_REG_IDX 10
#define HIVE_TESTBENCH_ISP_DMEM_ERROR_IRQ_REG_IDX 11
#define HIVE_TESTBENCH_SP_ICACHE_MEM_ERROR_IRQ_REG_IDX 12
#define HIVE_TESTBENCH_SP_DMEM_ERROR_IRQ_REG_IDX 13
/* Signal monitor input bit ids */
#define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_O_BIT_ID 0
#define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_1_BIT_ID 1
#define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_2_BIT_ID 2
#define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_3_BIT_ID 3
#define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_4_BIT_ID 4
#define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_5_BIT_ID 5
#define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_6_BIT_ID 6
#define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_7_BIT_ID 7
#define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_8_BIT_ID 8
#define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_9_BIT_ID 9
#define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_10_BIT_ID 10
#define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_11_BIT_ID 11
#define HIVE_TESTBENCH_SIG_MON_IRQ_PIN_BIT_ID 12
#define HIVE_TESTBENCH_SIG_MON_SDRAM_WAKEUP_PIN_BIT_ID 13
#define HIVE_TESTBENCH_SIG_MON_IDLE_PIN_BIT_ID 14
#define ISP2400_DEBUG_NETWORK 1
#endif /* _hive_isp_css_defs_h__ */

84
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/hive_isp_css_host_ids_hrt.h
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@ -1,84 +0,0 @@
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _hive_isp_css_host_ids_hrt_h_
#define _hive_isp_css_host_ids_hrt_h_
/* ISP_CSS identifiers */
#define INP_SYS testbench_isp_inp_sys
#define ISYS_GP_REGS testbench_isp_inp_sys_gpreg
#define ISYS_IRQ_CTRL testbench_isp_inp_sys_irq_ctrl
#define ISYS_CAP_A testbench_isp_inp_sys_capt_unit_a
#define ISYS_CAP_B testbench_isp_inp_sys_capt_unit_b
#define ISYS_CAP_C testbench_isp_inp_sys_capt_unit_c
#define ISYS_INP_BUF testbench_isp_inp_sys_input_buffer
#define ISYS_INP_CTRL testbench_isp_inp_sys_inp_ctrl
#define ISYS_ACQ testbench_isp_inp_sys_acq_unit
#define ISP testbench_isp_isp
#define SP testbench_isp_scp
#define IF_PRIM testbench_isp_ifmt_ift_prim
#define IF_PRIM_B testbench_isp_ifmt_ift_prim_b
#define IF_SEC testbench_isp_ifmt_ift_sec
#define IF_SEC_MASTER testbench_isp_ifmt_ift_sec_mt_out
#define STR_TO_MEM testbench_isp_ifmt_mem_cpy
#define IFMT_GP_REGS testbench_isp_ifmt_gp_reg
#define IFMT_IRQ_CTRL testbench_isp_ifmt_irq_ctrl
#define CSS_RECEIVER testbench_isp_inp_sys_csi_receiver
#define TC testbench_isp_gpd_tc
#define GPTIMER testbench_isp_gpd_gptimer
#define DMA testbench_isp_isp_dma
#define GDC testbench_isp_gdc1
#define GDC2 testbench_isp_gdc2
#define IRQ_CTRL testbench_isp_gpd_irq_ctrl
#define GPIO testbench_isp_gpd_c_gpio
#define GP_REGS testbench_isp_gpd_gp_reg
#define ISEL_GP_REGS testbench_isp_isel_gpr
#define ISEL_IRQ_CTRL testbench_isp_isel_irq_ctrl
#define DATA_MMU testbench_isp_data_out_sys_c_mmu
#define ICACHE_MMU testbench_isp_icache_out_sys_c_mmu
/* next is actually not FIFO but FIFO adapter, or slave to streaming adapter */
#define ISP_SP_FIFO testbench_isp_fa_sp_isp
#define ISEL_FIFO testbench_isp_isel_sf_fa_in
#define FIFO_GPF_SP testbench_isp_sf_fa2sp_in
#define FIFO_GPF_ISP testbench_isp_sf_fa2isp_in
#define FIFO_SP_GPF testbench_isp_sf_sp2fa_in
#define FIFO_ISP_GPF testbench_isp_sf_isp2fa_in
#define DATA_OCP_MASTER testbench_isp_data_out_sys_cio2ocp_wide_data_out_mt
#define ICACHE_OCP_MASTER testbench_isp_icache_out_sys_cio2ocp_wide_data_out_mt
#define SP_IN_FIFO testbench_isp_sf_fa2sp_in
#define SP_OUT_FIFO testbench_isp_sf_sp2fa_out
#define ISP_IN_FIFO testbench_isp_sf_fa2isp_in
#define ISP_OUT_FIFO testbench_isp_sf_isp2fa_out
#define GEN_SHORT_PACK_PORT testbench_isp_inp_sys_csi_str_mon_fa_gensh_out
#define ISYS_GP_REGS testbench_isp_inp_sys_gpreg
/* Testbench identifiers */
#define DDR testbench_ddram
#define DDR_SMALL testbench_ddram_small
#define XMEM DDR
#define GPIO_ADAPTER testbench_gp_adapter
#define SIG_MONITOR testbench_sig_mon
#define DDR_SLAVE testbench_ddram_ip0
#define DDR_SMALL_SLAVE testbench_ddram_small_ip0
#define HOST_MASTER host_op0
#endif /* _hive_isp_css_host_ids_hrt_h_ */

72
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/hive_isp_css_irq_types_hrt.h
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@ -1,72 +0,0 @@
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _HIVE_ISP_CSS_IRQ_TYPES_HRT_H_
#define _HIVE_ISP_CSS_IRQ_TYPES_HRT_H_
/*
* These are the indices of each interrupt in the interrupt
* controller's registers. these can be used as the irq_id
* argument to the hrt functions irq_controller.h.
*
* The definitions are taken from <system>_defs.h
*/
typedef enum hrt_isp_css_irq {
hrt_isp_css_irq_gpio_pin_0 = HIVE_GP_DEV_IRQ_GPIO_PIN_0_BIT_ID ,
hrt_isp_css_irq_gpio_pin_1 = HIVE_GP_DEV_IRQ_GPIO_PIN_1_BIT_ID ,
hrt_isp_css_irq_gpio_pin_2 = HIVE_GP_DEV_IRQ_GPIO_PIN_2_BIT_ID ,
hrt_isp_css_irq_gpio_pin_3 = HIVE_GP_DEV_IRQ_GPIO_PIN_3_BIT_ID ,
hrt_isp_css_irq_gpio_pin_4 = HIVE_GP_DEV_IRQ_GPIO_PIN_4_BIT_ID ,
hrt_isp_css_irq_gpio_pin_5 = HIVE_GP_DEV_IRQ_GPIO_PIN_5_BIT_ID ,
hrt_isp_css_irq_gpio_pin_6 = HIVE_GP_DEV_IRQ_GPIO_PIN_6_BIT_ID ,
hrt_isp_css_irq_gpio_pin_7 = HIVE_GP_DEV_IRQ_GPIO_PIN_7_BIT_ID ,
hrt_isp_css_irq_gpio_pin_8 = HIVE_GP_DEV_IRQ_GPIO_PIN_8_BIT_ID ,
hrt_isp_css_irq_gpio_pin_9 = HIVE_GP_DEV_IRQ_GPIO_PIN_9_BIT_ID ,
hrt_isp_css_irq_gpio_pin_10 = HIVE_GP_DEV_IRQ_GPIO_PIN_10_BIT_ID ,
hrt_isp_css_irq_gpio_pin_11 = HIVE_GP_DEV_IRQ_GPIO_PIN_11_BIT_ID ,
hrt_isp_css_irq_sp = HIVE_GP_DEV_IRQ_SP_BIT_ID ,
hrt_isp_css_irq_isp = HIVE_GP_DEV_IRQ_ISP_BIT_ID ,
hrt_isp_css_irq_isys = HIVE_GP_DEV_IRQ_ISYS_BIT_ID ,
hrt_isp_css_irq_isel = HIVE_GP_DEV_IRQ_ISEL_BIT_ID ,
hrt_isp_css_irq_ifmt = HIVE_GP_DEV_IRQ_IFMT_BIT_ID ,
hrt_isp_css_irq_sp_stream_mon = HIVE_GP_DEV_IRQ_SP_STREAM_MON_BIT_ID ,
hrt_isp_css_irq_isp_stream_mon = HIVE_GP_DEV_IRQ_ISP_STREAM_MON_BIT_ID ,
hrt_isp_css_irq_mod_stream_mon = HIVE_GP_DEV_IRQ_MOD_STREAM_MON_BIT_ID ,
#ifdef _HIVE_ISP_CSS_2401_SYSTEM
hrt_isp_css_irq_is2401 = HIVE_GP_DEV_IRQ_IS2401_BIT_ID ,
#else
hrt_isp_css_irq_isp_pmem_error = HIVE_GP_DEV_IRQ_ISP_PMEM_ERROR_BIT_ID ,
#endif
hrt_isp_css_irq_isp_bamem_error = HIVE_GP_DEV_IRQ_ISP_BAMEM_ERROR_BIT_ID ,
hrt_isp_css_irq_isp_dmem_error = HIVE_GP_DEV_IRQ_ISP_DMEM_ERROR_BIT_ID ,
hrt_isp_css_irq_sp_icache_mem_error = HIVE_GP_DEV_IRQ_SP_ICACHE_MEM_ERROR_BIT_ID ,
hrt_isp_css_irq_sp_dmem_error = HIVE_GP_DEV_IRQ_SP_DMEM_ERROR_BIT_ID ,
hrt_isp_css_irq_mmu_cache_mem_error = HIVE_GP_DEV_IRQ_MMU_CACHE_MEM_ERROR_BIT_ID ,
hrt_isp_css_irq_gp_timer_0 = HIVE_GP_DEV_IRQ_GP_TIMER_0_BIT_ID ,
hrt_isp_css_irq_gp_timer_1 = HIVE_GP_DEV_IRQ_GP_TIMER_1_BIT_ID ,
hrt_isp_css_irq_sw_pin_0 = HIVE_GP_DEV_IRQ_SW_PIN_0_BIT_ID ,
hrt_isp_css_irq_sw_pin_1 = HIVE_GP_DEV_IRQ_SW_PIN_1_BIT_ID ,
hrt_isp_css_irq_dma = HIVE_GP_DEV_IRQ_DMA_BIT_ID ,
hrt_isp_css_irq_sp_stream_mon_b = HIVE_GP_DEV_IRQ_SP_STREAM_MON_B_BIT_ID ,
/* this must (obviously) be the last on in the enum */
hrt_isp_css_irq_num_irqs
} hrt_isp_css_irq_t;
typedef enum hrt_isp_css_irq_status {
hrt_isp_css_irq_status_error,
hrt_isp_css_irq_status_more_irqs,
hrt_isp_css_irq_status_success
} hrt_isp_css_irq_status_t;
#endif /* _HIVE_ISP_CSS_IRQ_TYPES_HRT_H_ */

26
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/hive_isp_css_streaming_to_mipi_types_hrt.h
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@ -1,26 +0,0 @@
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _hive_isp_css_streaming_to_mipi_types_hrt_h_
#define _hive_isp_css_streaming_to_mipi_types_hrt_h_
#include <streaming_to_mipi_defs.h>
#define _HIVE_ISP_CH_ID_MASK ((1U << HIVE_ISP_CH_ID_BITS)-1)
#define _HIVE_ISP_FMT_TYPE_MASK ((1U << HIVE_ISP_FMT_TYPE_BITS)-1)
#define _HIVE_STR_TO_MIPI_FMT_TYPE_LSB (HIVE_STR_TO_MIPI_CH_ID_LSB + HIVE_ISP_CH_ID_BITS)
#define _HIVE_STR_TO_MIPI_DATA_B_LSB (HIVE_STR_TO_MIPI_DATA_A_LSB + HIVE_IF_PIXEL_WIDTH)
#endif /* _hive_isp_css_streaming_to_mipi_types_hrt_h_ */

128
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/hive_types.h
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@ -1,128 +0,0 @@
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _HRT_HIVE_TYPES_H
#define _HRT_HIVE_TYPES_H
#include "version.h"
#include "defs.h"
#ifndef HRTCAT3
#define _HRTCAT3(m,n,o) m##n##o
#define HRTCAT3(m,n,o) _HRTCAT3(m,n,o)
#endif
#ifndef HRTCAT4
#define _HRTCAT4(m,n,o,p) m##n##o##p
#define HRTCAT4(m,n,o,p) _HRTCAT4(m,n,o,p)
#endif
#ifndef HRTMIN
#define HRTMIN(a,b) (((a)<(b))?(a):(b))
#endif
#ifndef HRTMAX
#define HRTMAX(a,b) (((a)>(b))?(a):(b))
#endif
/* boolean data type */
typedef unsigned int hive_bool;
#define hive_false 0
#define hive_true 1
typedef char hive_int8;
typedef short hive_int16;
typedef int hive_int32;
typedef long long hive_int64;
typedef unsigned char hive_uint8;
typedef unsigned short hive_uint16;
typedef unsigned int hive_uint32;
typedef unsigned long long hive_uint64;
/* by default assume 32 bit master port (both data and address) */
#ifndef HRT_DATA_WIDTH
#define HRT_DATA_WIDTH 32
#endif
#ifndef HRT_ADDRESS_WIDTH
#define HRT_ADDRESS_WIDTH 32
#endif
#define HRT_DATA_BYTES (HRT_DATA_WIDTH/8)
#define HRT_ADDRESS_BYTES (HRT_ADDRESS_WIDTH/8)
#if HRT_DATA_WIDTH == 64
typedef hive_uint64 hrt_data;
#elif HRT_DATA_WIDTH == 32
typedef hive_uint32 hrt_data;
#else
#error data width not supported
#endif
#if HRT_ADDRESS_WIDTH == 64
typedef hive_uint64 hrt_address;
#elif HRT_ADDRESS_WIDTH == 32
typedef hive_uint32 hrt_address;
#else
#error adddres width not supported
#endif
/* The SP side representation of an HMM virtual address */
typedef hive_uint32 hrt_vaddress;
/* use 64 bit addresses in simulation, where possible */
typedef hive_uint64 hive_sim_address;
/* below is for csim, not for hrt, rename and move this elsewhere */
typedef unsigned int hive_uint;
typedef hive_uint32 hive_address;
typedef hive_address hive_slave_address;
typedef hive_address hive_mem_address;
/* MMIO devices */
typedef hive_uint hive_mmio_id;
typedef hive_mmio_id hive_slave_id;
typedef hive_mmio_id hive_port_id;
typedef hive_mmio_id hive_master_id;
typedef hive_mmio_id hive_mem_id;
typedef hive_mmio_id hive_dev_id;
typedef hive_mmio_id hive_fifo_id;
typedef hive_uint hive_hier_id;
typedef hive_hier_id hive_device_id;
typedef hive_device_id hive_proc_id;
typedef hive_device_id hive_cell_id;
typedef hive_device_id hive_host_id;
typedef hive_device_id hive_bus_id;
typedef hive_device_id hive_bridge_id;
typedef hive_device_id hive_fifo_adapter_id;
typedef hive_device_id hive_custom_device_id;
typedef hive_uint hive_slot_id;
typedef hive_uint hive_fu_id;
typedef hive_uint hive_reg_file_id;
typedef hive_uint hive_reg_id;
/* Streaming devices */
typedef hive_uint hive_outport_id;
typedef hive_uint hive_inport_id;
typedef hive_uint hive_msink_id;
/* HRT specific */
typedef char* hive_program;
typedef char* hive_function;
#endif /* _HRT_HIVE_TYPES_H */

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