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mmc: tegra: Program pad autocal offsets from dt
Parse the pad drive strength calibration offsets from the device tree. Program the calibration offsets in accordance with the current signaling mode. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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887bda8f21
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@ -50,6 +50,7 @@
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#define SDHCI_TEGRA_AUTO_CAL_CONFIG 0x1e4
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#define SDHCI_AUTO_CAL_START BIT(31)
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#define SDHCI_AUTO_CAL_ENABLE BIT(29)
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#define SDHCI_AUTO_CAL_PDPU_OFFSET_MASK 0x0000ffff
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#define SDHCI_TEGRA_SDMEM_COMP_PADCTRL 0x1e0
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#define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK 0x0000000f
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@ -73,6 +74,22 @@ struct sdhci_tegra_soc_data {
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u32 nvquirks;
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};
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/* Magic pull up and pull down pad calibration offsets */
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struct sdhci_tegra_autocal_offsets {
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u32 pull_up_3v3;
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u32 pull_down_3v3;
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u32 pull_up_3v3_timeout;
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u32 pull_down_3v3_timeout;
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u32 pull_up_1v8;
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u32 pull_down_1v8;
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u32 pull_up_1v8_timeout;
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u32 pull_down_1v8_timeout;
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u32 pull_up_sdr104;
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u32 pull_down_sdr104;
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u32 pull_up_hs400;
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u32 pull_down_hs400;
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};
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struct sdhci_tegra {
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const struct sdhci_tegra_soc_data *soc_data;
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struct gpio_desc *power_gpio;
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@ -84,6 +101,8 @@ struct sdhci_tegra {
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struct pinctrl *pinctrl_sdmmc;
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struct pinctrl_state *pinctrl_state_3v3;
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struct pinctrl_state *pinctrl_state_1v8;
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struct sdhci_tegra_autocal_offsets autocal_offsets;
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};
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static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
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@ -281,12 +300,45 @@ static bool tegra_sdhci_configure_card_clk(struct sdhci_host *host, bool enable)
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return status;
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}
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static void tegra_sdhci_set_pad_autocal_offset(struct sdhci_host *host,
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u16 pdpu)
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{
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u32 reg;
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reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);
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reg &= ~SDHCI_AUTO_CAL_PDPU_OFFSET_MASK;
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reg |= pdpu;
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sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG);
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}
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static void tegra_sdhci_pad_autocalib(struct sdhci_host *host)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
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struct sdhci_tegra_autocal_offsets offsets =
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tegra_host->autocal_offsets;
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struct mmc_ios *ios = &host->mmc->ios;
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bool card_clk_enabled;
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u16 pdpu;
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u32 reg;
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int ret;
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switch (ios->timing) {
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case MMC_TIMING_UHS_SDR104:
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pdpu = offsets.pull_down_sdr104 << 8 | offsets.pull_up_sdr104;
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break;
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case MMC_TIMING_MMC_HS400:
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pdpu = offsets.pull_down_hs400 << 8 | offsets.pull_up_hs400;
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break;
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default:
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if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
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pdpu = offsets.pull_down_1v8 << 8 | offsets.pull_up_1v8;
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else
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pdpu = offsets.pull_down_3v3 << 8 | offsets.pull_up_3v3;
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}
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tegra_sdhci_set_pad_autocal_offset(host, pdpu);
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card_clk_enabled = tegra_sdhci_configure_card_clk(host, false);
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tegra_sdhci_configure_cal_pad(host, true);
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@ -305,8 +357,104 @@ static void tegra_sdhci_pad_autocalib(struct sdhci_host *host)
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tegra_sdhci_configure_card_clk(host, card_clk_enabled);
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if (ret)
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if (ret) {
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dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n");
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if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
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pdpu = offsets.pull_down_1v8_timeout << 8 |
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offsets.pull_up_1v8_timeout;
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else
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pdpu = offsets.pull_down_3v3_timeout << 8 |
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offsets.pull_up_3v3_timeout;
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/* Disable automatic calibration and use fixed offsets */
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reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);
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reg &= ~SDHCI_AUTO_CAL_ENABLE;
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sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG);
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tegra_sdhci_set_pad_autocal_offset(host, pdpu);
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}
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}
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static void tegra_sdhci_parse_pad_autocal_dt(struct sdhci_host *host)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
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struct sdhci_tegra_autocal_offsets *autocal =
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&tegra_host->autocal_offsets;
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int err;
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err = device_property_read_u32(host->mmc->parent,
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"nvidia,pad-autocal-pull-up-offset-3v3",
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&autocal->pull_up_3v3);
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if (err)
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autocal->pull_up_3v3 = 0;
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err = device_property_read_u32(host->mmc->parent,
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"nvidia,pad-autocal-pull-down-offset-3v3",
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&autocal->pull_down_3v3);
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if (err)
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autocal->pull_down_3v3 = 0;
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err = device_property_read_u32(host->mmc->parent,
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"nvidia,pad-autocal-pull-up-offset-1v8",
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&autocal->pull_up_1v8);
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if (err)
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autocal->pull_up_1v8 = 0;
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err = device_property_read_u32(host->mmc->parent,
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"nvidia,pad-autocal-pull-down-offset-1v8",
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&autocal->pull_down_1v8);
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if (err)
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autocal->pull_down_1v8 = 0;
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err = device_property_read_u32(host->mmc->parent,
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"nvidia,pad-autocal-pull-up-offset-3v3-timeout",
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&autocal->pull_up_3v3);
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if (err)
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autocal->pull_up_3v3_timeout = 0;
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err = device_property_read_u32(host->mmc->parent,
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"nvidia,pad-autocal-pull-down-offset-3v3-timeout",
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&autocal->pull_down_3v3);
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if (err)
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autocal->pull_down_3v3_timeout = 0;
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err = device_property_read_u32(host->mmc->parent,
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"nvidia,pad-autocal-pull-up-offset-1v8-timeout",
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&autocal->pull_up_1v8);
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if (err)
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autocal->pull_up_1v8_timeout = 0;
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err = device_property_read_u32(host->mmc->parent,
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"nvidia,pad-autocal-pull-down-offset-1v8-timeout",
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&autocal->pull_down_1v8);
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if (err)
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autocal->pull_down_1v8_timeout = 0;
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err = device_property_read_u32(host->mmc->parent,
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"nvidia,pad-autocal-pull-up-offset-sdr104",
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&autocal->pull_up_sdr104);
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if (err)
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autocal->pull_up_sdr104 = autocal->pull_up_1v8;
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err = device_property_read_u32(host->mmc->parent,
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"nvidia,pad-autocal-pull-down-offset-sdr104",
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&autocal->pull_down_sdr104);
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if (err)
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autocal->pull_down_sdr104 = autocal->pull_down_1v8;
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err = device_property_read_u32(host->mmc->parent,
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"nvidia,pad-autocal-pull-up-offset-hs400",
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&autocal->pull_up_hs400);
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if (err)
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autocal->pull_up_hs400 = autocal->pull_up_1v8;
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err = device_property_read_u32(host->mmc->parent,
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"nvidia,pad-autocal-pull-down-offset-hs400",
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&autocal->pull_down_hs400);
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if (err)
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autocal->pull_down_hs400 = autocal->pull_down_1v8;
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}
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static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
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@ -698,6 +846,8 @@ static int sdhci_tegra_probe(struct platform_device *pdev)
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if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50)
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host->mmc->caps |= MMC_CAP_1_8V_DDR;
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tegra_sdhci_parse_pad_autocal_dt(host);
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tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power",
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GPIOD_OUT_HIGH);
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if (IS_ERR(tegra_host->power_gpio)) {
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