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MIPS: Octeon: Move some platform device registration to its own file.
There is a bunch of platform device registration in arch/mips/cavium-octeon/setup.c. We move it to its own file in preparation for adding more platform devices. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
David Daney
Ralf Baechle
parent
2ca2ebfd95
commit
512254ba83
@ -6,10 +6,10 @@
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# License. See the file "COPYING" in the main directory of this archive
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# for more details.
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#
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# Copyright (C) 2005-2008 Cavium Networks
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# Copyright (C) 2005-2009 Cavium Networks
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#
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obj-y := setup.o serial.o octeon-irq.o csrc-octeon.o
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obj-y := setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o
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obj-y += dma-octeon.o flash_setup.o
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obj-y += octeon-memcpy.o
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164
arch/mips/cavium-octeon/octeon-platform.c
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164
arch/mips/cavium-octeon/octeon-platform.c
Normal file
@ -0,0 +1,164 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2004-2009 Cavium Networks
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* Copyright (C) 2008 Wind River Systems
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*/
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <asm/octeon/octeon.h>
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#include <asm/octeon/cvmx-rnm-defs.h>
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static struct octeon_cf_data octeon_cf_data;
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static int __init octeon_cf_device_init(void)
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{
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union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
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unsigned long base_ptr, region_base, region_size;
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struct platform_device *pd;
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struct resource cf_resources[3];
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unsigned int num_resources;
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int i;
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int ret = 0;
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/* Setup octeon-cf platform device if present. */
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base_ptr = 0;
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if (octeon_bootinfo->major_version == 1
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&& octeon_bootinfo->minor_version >= 1) {
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if (octeon_bootinfo->compact_flash_common_base_addr)
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base_ptr =
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octeon_bootinfo->compact_flash_common_base_addr;
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} else {
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base_ptr = 0x1d000800;
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}
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if (!base_ptr)
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return ret;
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/* Find CS0 region. */
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for (i = 0; i < 8; i++) {
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mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i));
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region_base = mio_boot_reg_cfg.s.base << 16;
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region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
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if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
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&& base_ptr < region_base + region_size)
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break;
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}
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if (i >= 7) {
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/* i and i + 1 are CS0 and CS1, both must be less than 8. */
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goto out;
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}
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octeon_cf_data.base_region = i;
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octeon_cf_data.is16bit = mio_boot_reg_cfg.s.width;
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octeon_cf_data.base_region_bias = base_ptr - region_base;
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memset(cf_resources, 0, sizeof(cf_resources));
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num_resources = 0;
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cf_resources[num_resources].flags = IORESOURCE_MEM;
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cf_resources[num_resources].start = region_base;
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cf_resources[num_resources].end = region_base + region_size - 1;
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num_resources++;
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if (!(base_ptr & 0xfffful)) {
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/*
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* Boot loader signals availability of DMA (true_ide
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* mode) by setting low order bits of base_ptr to
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* zero.
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*/
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/* Asume that CS1 immediately follows. */
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mio_boot_reg_cfg.u64 =
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cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i + 1));
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region_base = mio_boot_reg_cfg.s.base << 16;
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region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
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if (!mio_boot_reg_cfg.s.en)
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goto out;
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cf_resources[num_resources].flags = IORESOURCE_MEM;
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cf_resources[num_resources].start = region_base;
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cf_resources[num_resources].end = region_base + region_size - 1;
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num_resources++;
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octeon_cf_data.dma_engine = 0;
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cf_resources[num_resources].flags = IORESOURCE_IRQ;
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cf_resources[num_resources].start = OCTEON_IRQ_BOOTDMA;
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cf_resources[num_resources].end = OCTEON_IRQ_BOOTDMA;
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num_resources++;
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} else {
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octeon_cf_data.dma_engine = -1;
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}
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pd = platform_device_alloc("pata_octeon_cf", -1);
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if (!pd) {
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ret = -ENOMEM;
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goto out;
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}
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pd->dev.platform_data = &octeon_cf_data;
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ret = platform_device_add_resources(pd, cf_resources, num_resources);
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if (ret)
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goto fail;
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ret = platform_device_add(pd);
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if (ret)
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goto fail;
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return ret;
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fail:
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platform_device_put(pd);
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out:
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return ret;
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}
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device_initcall(octeon_cf_device_init);
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/* Octeon Random Number Generator. */
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static int __init octeon_rng_device_init(void)
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{
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struct platform_device *pd;
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int ret = 0;
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struct resource rng_resources[] = {
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{
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.flags = IORESOURCE_MEM,
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.start = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS),
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.end = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf
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}, {
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.flags = IORESOURCE_MEM,
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.start = cvmx_build_io_address(8, 0),
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.end = cvmx_build_io_address(8, 0) + 0x7
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}
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};
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pd = platform_device_alloc("octeon_rng", -1);
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if (!pd) {
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ret = -ENOMEM;
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goto out;
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}
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ret = platform_device_add_resources(pd, rng_resources,
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ARRAY_SIZE(rng_resources));
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if (ret)
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goto fail;
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ret = platform_device_add(pd);
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if (ret)
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goto fail;
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return ret;
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fail:
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platform_device_put(pd);
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out:
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return ret;
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}
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device_initcall(octeon_rng_device_init);
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MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>");
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("Platform driver for Octeon SOC");
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@ -11,7 +11,6 @@
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/serial.h>
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#include <linux/smp.h>
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#include <linux/types.h>
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@ -33,7 +32,6 @@
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#include <asm/time.h>
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#include <asm/octeon/octeon.h>
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#include <asm/octeon/cvmx-rnm-defs.h>
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#ifdef CONFIG_CAVIUM_DECODE_RSL
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extern void cvmx_interrupt_rsl_decode(void);
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@ -825,147 +823,3 @@ void prom_free_prom_memory(void)
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CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB option is set */
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octeon_hal_setup_reserved32();
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}
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static struct octeon_cf_data octeon_cf_data;
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static int __init octeon_cf_device_init(void)
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{
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union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
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unsigned long base_ptr, region_base, region_size;
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struct platform_device *pd;
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struct resource cf_resources[3];
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unsigned int num_resources;
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int i;
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int ret = 0;
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/* Setup octeon-cf platform device if present. */
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base_ptr = 0;
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if (octeon_bootinfo->major_version == 1
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&& octeon_bootinfo->minor_version >= 1) {
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if (octeon_bootinfo->compact_flash_common_base_addr)
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base_ptr =
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octeon_bootinfo->compact_flash_common_base_addr;
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} else {
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base_ptr = 0x1d000800;
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}
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if (!base_ptr)
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return ret;
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/* Find CS0 region. */
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for (i = 0; i < 8; i++) {
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mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i));
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region_base = mio_boot_reg_cfg.s.base << 16;
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region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
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if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
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&& base_ptr < region_base + region_size)
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break;
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}
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if (i >= 7) {
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/* i and i + 1 are CS0 and CS1, both must be less than 8. */
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goto out;
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}
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octeon_cf_data.base_region = i;
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octeon_cf_data.is16bit = mio_boot_reg_cfg.s.width;
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octeon_cf_data.base_region_bias = base_ptr - region_base;
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memset(cf_resources, 0, sizeof(cf_resources));
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num_resources = 0;
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cf_resources[num_resources].flags = IORESOURCE_MEM;
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cf_resources[num_resources].start = region_base;
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cf_resources[num_resources].end = region_base + region_size - 1;
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num_resources++;
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if (!(base_ptr & 0xfffful)) {
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/*
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* Boot loader signals availability of DMA (true_ide
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* mode) by setting low order bits of base_ptr to
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* zero.
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*/
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/* Asume that CS1 immediately follows. */
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mio_boot_reg_cfg.u64 =
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cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i + 1));
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region_base = mio_boot_reg_cfg.s.base << 16;
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region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
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if (!mio_boot_reg_cfg.s.en)
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goto out;
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cf_resources[num_resources].flags = IORESOURCE_MEM;
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cf_resources[num_resources].start = region_base;
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cf_resources[num_resources].end = region_base + region_size - 1;
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num_resources++;
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octeon_cf_data.dma_engine = 0;
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cf_resources[num_resources].flags = IORESOURCE_IRQ;
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cf_resources[num_resources].start = OCTEON_IRQ_BOOTDMA;
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cf_resources[num_resources].end = OCTEON_IRQ_BOOTDMA;
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num_resources++;
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} else {
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octeon_cf_data.dma_engine = -1;
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}
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pd = platform_device_alloc("pata_octeon_cf", -1);
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if (!pd) {
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ret = -ENOMEM;
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goto out;
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}
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pd->dev.platform_data = &octeon_cf_data;
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ret = platform_device_add_resources(pd, cf_resources, num_resources);
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if (ret)
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goto fail;
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ret = platform_device_add(pd);
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if (ret)
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goto fail;
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return ret;
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fail:
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platform_device_put(pd);
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out:
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return ret;
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}
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device_initcall(octeon_cf_device_init);
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/* Octeon Random Number Generator. */
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static int __init octeon_rng_device_init(void)
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{
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struct platform_device *pd;
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int ret = 0;
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struct resource rng_resources[] = {
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{
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.flags = IORESOURCE_MEM,
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.start = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS),
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.end = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf
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}, {
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.flags = IORESOURCE_MEM,
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.start = cvmx_build_io_address(8, 0),
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.end = cvmx_build_io_address(8, 0) + 0x7
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}
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};
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pd = platform_device_alloc("octeon_rng", -1);
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if (!pd) {
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ret = -ENOMEM;
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goto out;
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}
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ret = platform_device_add_resources(pd, rng_resources,
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ARRAY_SIZE(rng_resources));
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if (ret)
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goto fail;
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ret = platform_device_add(pd);
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if (ret)
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goto fail;
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return ret;
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fail:
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platform_device_put(pd);
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out:
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return ret;
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}
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device_initcall(octeon_rng_device_init);
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