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OMAP3: hwmod: add I2C hwmods for OMAP3430
Add hwmod structures for I2C controllers on OMAP3430. This patch was developed in collaboration with Paul Walmsley <paul@pwsan.com>. OMAP3 fixes for correct IDLEST bit monitoring from G, Manjunath Kondaiah <manjugk@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: G, Manjunath Kondaiah <manjugk@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This commit is contained in:
Rajendra Nayak
Kevin Hilman
parent
2004290f55
commit
4fe20e97c8
@ -18,6 +18,9 @@
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#include <plat/cpu.h>
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#include <plat/dma.h>
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#include <plat/serial.h>
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#include <plat/l4_3xxx.h>
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#include <plat/i2c.h>
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#include <plat/omap34xx.h>
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#include "omap_hwmod_common_data.h"
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@ -39,6 +42,9 @@ static struct omap_hwmod omap3xxx_l3_main_hwmod;
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static struct omap_hwmod omap3xxx_l4_core_hwmod;
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static struct omap_hwmod omap3xxx_l4_per_hwmod;
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static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
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static struct omap_hwmod omap3xxx_i2c1_hwmod;
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static struct omap_hwmod omap3xxx_i2c2_hwmod;
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static struct omap_hwmod omap3xxx_i2c3_hwmod;
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/* L3 -> L4_CORE interface */
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static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
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@ -169,6 +175,84 @@ static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* I2C IP block address space length (in bytes) */
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#define OMAP2_I2C_AS_LEN 128
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/* L4 CORE -> I2C1 interface */
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static struct omap_hwmod_addr_space omap3xxx_i2c1_addr_space[] = {
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{
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.pa_start = 0x48070000,
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.pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
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.flags = ADDR_TYPE_RT,
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},
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};
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static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
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.master = &omap3xxx_l4_core_hwmod,
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.slave = &omap3xxx_i2c1_hwmod,
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.clk = "i2c1_ick",
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.addr = omap3xxx_i2c1_addr_space,
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.addr_cnt = ARRAY_SIZE(omap3xxx_i2c1_addr_space),
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.fw = {
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.omap2 = {
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.l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
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.l4_prot_group = 7,
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.flags = OMAP_FIREWALL_L4,
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}
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},
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* L4 CORE -> I2C2 interface */
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static struct omap_hwmod_addr_space omap3xxx_i2c2_addr_space[] = {
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{
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.pa_start = 0x48072000,
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.pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
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.flags = ADDR_TYPE_RT,
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},
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};
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static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
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.master = &omap3xxx_l4_core_hwmod,
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.slave = &omap3xxx_i2c2_hwmod,
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.clk = "i2c2_ick",
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.addr = omap3xxx_i2c2_addr_space,
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.addr_cnt = ARRAY_SIZE(omap3xxx_i2c2_addr_space),
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.fw = {
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.omap2 = {
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.l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
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.l4_prot_group = 7,
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.flags = OMAP_FIREWALL_L4,
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}
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},
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* L4 CORE -> I2C3 interface */
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static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
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{
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.pa_start = 0x48060000,
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.pa_end = 0x48060000 + OMAP2_I2C_AS_LEN - 1,
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.flags = ADDR_TYPE_RT,
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},
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};
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static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
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.master = &omap3xxx_l4_core_hwmod,
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.slave = &omap3xxx_i2c3_hwmod,
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.clk = "i2c3_ick",
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.addr = omap3xxx_i2c3_addr_space,
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.addr_cnt = ARRAY_SIZE(omap3xxx_i2c3_addr_space),
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.fw = {
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.omap2 = {
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.l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
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.l4_prot_group = 7,
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.flags = OMAP_FIREWALL_L4,
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}
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},
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* Slave interfaces on the L4_CORE interconnect */
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static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
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&omap3xxx_l3_main__l4_core,
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@ -179,6 +263,9 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = {
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&omap3xxx_l4_core__l4_wkup,
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&omap3_l4_core__uart1,
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&omap3_l4_core__uart2,
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&omap3_l4_core__i2c1,
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&omap3_l4_core__i2c2,
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&omap3_l4_core__i2c3,
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};
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/* L4 CORE */
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@ -315,6 +402,18 @@ static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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/* I2C common */
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static struct omap_hwmod_class_sysconfig i2c_sysc = {
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.rev_offs = 0x00,
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.sysc_offs = 0x20,
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.syss_offs = 0x10,
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.sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
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SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
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SYSC_HAS_AUTOIDLE),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
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.name = "wd_timer",
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.sysc = &omap3xxx_wd_timer_sysc,
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@ -509,6 +608,137 @@ static struct omap_hwmod omap3xxx_uart4_hwmod = {
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
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};
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static struct omap_hwmod_class i2c_class = {
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.name = "i2c",
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.sysc = &i2c_sysc,
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};
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/* I2C1 */
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static struct omap_i2c_dev_attr i2c1_dev_attr = {
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.fifo_depth = 8, /* bytes */
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};
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static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
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{ .irq = INT_24XX_I2C1_IRQ, },
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};
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static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
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{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
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{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
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};
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static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
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&omap3_l4_core__i2c1,
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};
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static struct omap_hwmod omap3xxx_i2c1_hwmod = {
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.name = "i2c1",
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.mpu_irqs = i2c1_mpu_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs),
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.sdma_reqs = i2c1_sdma_reqs,
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.sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
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.main_clk = "i2c1_fck",
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.prcm = {
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.omap2 = {
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.module_offs = CORE_MOD,
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.prcm_reg_id = 1,
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.module_bit = OMAP3430_EN_I2C1_SHIFT,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
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},
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},
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.slaves = omap3xxx_i2c1_slaves,
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.slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves),
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.class = &i2c_class,
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.dev_attr = &i2c1_dev_attr,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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};
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/* I2C2 */
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static struct omap_i2c_dev_attr i2c2_dev_attr = {
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.fifo_depth = 8, /* bytes */
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};
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static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
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{ .irq = INT_24XX_I2C2_IRQ, },
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};
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static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
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{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
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{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
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};
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static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
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&omap3_l4_core__i2c2,
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};
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static struct omap_hwmod omap3xxx_i2c2_hwmod = {
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.name = "i2c2",
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.mpu_irqs = i2c2_mpu_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs),
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.sdma_reqs = i2c2_sdma_reqs,
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.sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
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.main_clk = "i2c2_fck",
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.prcm = {
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.omap2 = {
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.module_offs = CORE_MOD,
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.prcm_reg_id = 1,
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.module_bit = OMAP3430_EN_I2C2_SHIFT,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
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},
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},
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.slaves = omap3xxx_i2c2_slaves,
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.slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves),
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.class = &i2c_class,
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.dev_attr = &i2c2_dev_attr,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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};
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/* I2C3 */
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static struct omap_i2c_dev_attr i2c3_dev_attr = {
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.fifo_depth = 64, /* bytes */
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};
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static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
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{ .irq = INT_34XX_I2C3_IRQ, },
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};
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static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
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{ .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
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{ .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
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};
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static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
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&omap3_l4_core__i2c3,
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};
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static struct omap_hwmod omap3xxx_i2c3_hwmod = {
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.name = "i2c3",
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.mpu_irqs = i2c3_mpu_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(i2c3_mpu_irqs),
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.sdma_reqs = i2c3_sdma_reqs,
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.sdma_reqs_cnt = ARRAY_SIZE(i2c3_sdma_reqs),
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.main_clk = "i2c3_fck",
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.prcm = {
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.omap2 = {
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.module_offs = CORE_MOD,
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.prcm_reg_id = 1,
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.module_bit = OMAP3430_EN_I2C3_SHIFT,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
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},
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},
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.slaves = omap3xxx_i2c3_slaves,
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.slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves),
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.class = &i2c_class,
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.dev_attr = &i2c3_dev_attr,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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};
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static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
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&omap3xxx_l3_main_hwmod,
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&omap3xxx_l4_core_hwmod,
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@ -521,6 +751,9 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
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&omap3xxx_uart2_hwmod,
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&omap3xxx_uart3_hwmod,
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&omap3xxx_uart4_hwmod,
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&omap3xxx_i2c1_hwmod,
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&omap3xxx_i2c2_hwmod,
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&omap3xxx_i2c3_hwmod,
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NULL,
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};
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@ -101,8 +101,11 @@
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#define OMAP3430_GRPSEL_MCSPI3_MASK (1 << 20)
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#define OMAP3430_GRPSEL_MCSPI2_MASK (1 << 19)
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#define OMAP3430_GRPSEL_MCSPI1_MASK (1 << 18)
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#define OMAP3430_GRPSEL_I2C3_SHIFT 17
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#define OMAP3430_GRPSEL_I2C3_MASK (1 << 17)
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#define OMAP3430_GRPSEL_I2C2_SHIFT 16
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#define OMAP3430_GRPSEL_I2C2_MASK (1 << 16)
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#define OMAP3430_GRPSEL_I2C1_SHIFT 15
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#define OMAP3430_GRPSEL_I2C1_MASK (1 << 15)
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#define OMAP3430_GRPSEL_UART2_MASK (1 << 14)
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#define OMAP3430_GRPSEL_UART1_MASK (1 << 13)
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@ -36,6 +36,19 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
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}
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#endif
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/**
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* i2c_dev_attr - OMAP I2C controller device attributes for omap_hwmod
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* @fifo_depth: total controller FIFO size (in bytes)
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* @flags: differences in hardware support capability
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*
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* @fifo_depth represents what exists on the hardware, not what is
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* actually configured at runtime by the device driver.
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*/
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struct omap_i2c_dev_attr {
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u8 fifo_depth;
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u8 flags;
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};
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void __init omap1_i2c_mux_pins(int bus_id);
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void __init omap2_i2c_mux_pins(int bus_id);
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24
arch/arm/plat-omap/include/plat/l4_3xxx.h
Normal file
24
arch/arm/plat-omap/include/plat/l4_3xxx.h
Normal file
@ -0,0 +1,24 @@
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/*
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* arch/arm/plat-omap/include/mach/l4_3xxx.h - L4 firewall definitions
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*
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* Copyright (C) 2009 Nokia Corporation
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_L4_3XXX_H
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#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_L4_3XXX_H
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/* L4 CORE */
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#define OMAP3_L4_CORE_FW_I2C1_REGION 21
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#define OMAP3_L4_CORE_FW_I2C1_TA_REGION 22
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#define OMAP3_L4_CORE_FW_I2C2_REGION 23
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#define OMAP3_L4_CORE_FW_I2C2_TA_REGION 24
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#define OMAP3_L4_CORE_FW_I2C3_REGION 73
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#define OMAP3_L4_CORE_FW_I2C3_TA_REGION 74
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#endif
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