renegade-project/linux-next
2
0
Fork 0
mirror of https://github.com/edk2-porting/linux-next.git synced 2024-12-24 21:24:00 +08:00
Code

riscv: add support for MMIO access to the timer registers

Browse Source 
When running in M-mode we can't use the SBI to set the timer, and
don't have access to the time CSR as that usually is emulated by
M-mode.  Instead provide code that directly accesses the MMIO for
the timer.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
Acked-by: Thomas Gleixner <tglx@linutronix.de> # for drivers/clocksource
[paul.walmsley@sifive.com: updated to apply; fixed checkpatch
 issue; timex.h now includes asm/mmio.h to resolve header file
 problems]
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
This commit is contained in:
Christoph Hellwig 2019-10-28 13:10:37 +01:00 committed by Paul Walmsley
parent 8bf90f320d
commit 4f9bbcefa1
3 changed files with 38 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/riscv/include/asm/sbi.h
View File

@ -95,7 +95,8 @@ static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
SBI_CALL_4(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask, start, size, asid);
}
#else /* CONFIG_RISCV_SBI */
/* stub for code that is only reachable under IS_ENABLED(CONFIG_RISCV_SBI): */
/* stubs for code that is only reachable under IS_ENABLED(CONFIG_RISCV_SBI): */
void sbi_set_timer(uint64_t stime_value);
void sbi_remote_fence_i(const unsigned long *hart_mask);
#endif /* CONFIG_RISCV_SBI */
#endif /* _ASM_RISCV_SBI_H */

19
arch/riscv/include/asm/timex.h
View File

@ -7,12 +7,25 @@
#define _ASM_RISCV_TIMEX_H
#include <asm/csr.h>
#include <asm/mmio.h>
typedef unsigned long cycles_t;
extern u64 __iomem *riscv_time_val;
extern u64 __iomem *riscv_time_cmp;
#ifdef CONFIG_64BIT
#define mmio_get_cycles() readq_relaxed(riscv_time_val)
#else
#define mmio_get_cycles() readl_relaxed(riscv_time_val)
#define mmio_get_cycles_hi() readl_relaxed(((u32 *)riscv_time_val) + 1)
#endif
static inline cycles_t get_cycles(void)
{
return csr_read(CSR_TIME);
if (IS_ENABLED(CONFIG_RISCV_SBI))
return csr_read(CSR_TIME);
return mmio_get_cycles();
}
#define get_cycles get_cycles
@ -24,7 +37,9 @@ static inline u64 get_cycles64(void)
#else /* CONFIG_64BIT */
static inline u32 get_cycles_hi(void)
{
return csr_read(CSR_TIMEH);
if (IS_ENABLED(CONFIG_RISCV_SBI))
return csr_read(CSR_TIMEH);
return mmio_get_cycles_hi();
}
static inline u64 get_cycles64(void)

23
drivers/clocksource/timer-riscv.c
View File

@ -3,9 +3,9 @@
* Copyright (C) 2012 Regents of the University of California
* Copyright (C) 2017 SiFive
*
* All RISC-V systems have a timer attached to every hart. These timers can be
* read from the "time" and "timeh" CSRs, and can use the SBI to setup
* events.
* All RISC-V systems have a timer attached to every hart. These timers can
* either be read from the "time" and "timeh" CSRs, and can use the SBI to
* setup events, or directly accessed using MMIO registers.
*/
#include <linux/clocksource.h>
#include <linux/clockchips.h>
@ -13,14 +13,29 @@
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/sched_clock.h>
#include <linux/io-64-nonatomic-lo-hi.h>
#include <asm/smp.h>
#include <asm/sbi.h>
u64 __iomem *riscv_time_cmp;
u64 __iomem *riscv_time_val;
static inline void mmio_set_timer(u64 val)
{
void __iomem *r;
r = riscv_time_cmp + cpuid_to_hartid_map(smp_processor_id());
writeq_relaxed(val, r);
}
static int riscv_clock_next_event(unsigned long delta,
struct clock_event_device *ce)
{
csr_set(CSR_IE, IE_TIE);
sbi_set_timer(get_cycles64() + delta);
if (IS_ENABLED(CONFIG_RISCV_SBI))
sbi_set_timer(get_cycles64() + delta);
else
mmio_set_timer(get_cycles64() + delta);
return 0;
}