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ath9k: Update AR955x initvals
This patch disables HW peak detect calibration for AR955x, since it is problematic on a few boards. Instead, manual calibration will be done in the driver. Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
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@ -63,7 +63,7 @@ static const u32 ar955x_1p0_baseband_postamble[][5] = {
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{0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
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{0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
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{0x00009e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021},
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{0x00009e3c, 0xcfa10820, 0xcfa10820, 0xcfa10822, 0xcfa10822},
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{0x00009e3c, 0xcfa10820, 0xcfa10820, 0xcfa10820, 0xcfa10820},
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{0x00009e44, 0xfe321e27, 0xfe321e27, 0xfe291e27, 0xfe291e27},
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{0x00009e48, 0x5030201a, 0x5030201a, 0x50302012, 0x50302012},
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{0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
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@ -83,7 +83,7 @@ static const u32 ar955x_1p0_baseband_postamble[][5] = {
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{0x0000a284, 0x00000000, 0x00000000, 0x00000010, 0x00000010},
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{0x0000a288, 0x00000110, 0x00000110, 0x00000110, 0x00000110},
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{0x0000a28c, 0x00022222, 0x00022222, 0x00022222, 0x00022222},
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{0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
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{0x0000a2c4, 0x00158d18, 0x00158d18, 0x00058d18, 0x00058d18},
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{0x0000a2cc, 0x18c50033, 0x18c43433, 0x18c41033, 0x18c44c33},
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{0x0000a2d0, 0x00041982, 0x00041982, 0x00041982, 0x00041982},
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{0x0000a2d8, 0x7999a83b, 0x7999a83b, 0x7999a83b, 0x7999a83b},
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