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PCI: altera: Simplify TLP_CFG_DW1 usage
TLP_CFG_DW1() was only used with altera->root_bus_nr and RP_DEVFN, so encode that directly into the macro so we don't have to clutter the uses with the TLP_REQ_ID() usage. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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@ -55,18 +55,19 @@
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#define TLP_PAYLOAD_SIZE 0x01
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#define TLP_READ_TAG 0x1d
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#define TLP_WRITE_TAG 0x10
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#define RP_DEVFN 0
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#define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))
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#define TLP_CFG_DW0(pcie, bus) \
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((((bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGRD0 \
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: TLP_FMTTYPE_CFGRD1) << 24) | \
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TLP_PAYLOAD_SIZE)
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#define TLP_CFG_DW1(reqid, tag, be) (((reqid) << 16) | (tag << 8) | (be))
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#define TLP_CFG_DW1(pcie, tag, be) \
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(((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
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#define TLP_CFG_DW2(bus, devfn, offset) \
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(((bus) << 24) | ((devfn) << 16) | (offset))
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#define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))
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#define TLP_COMP_STATUS(s) (((s) >> 12) & 7)
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#define TLP_HDR_SIZE 3
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#define TLP_LOOP 500
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#define RP_DEVFN 0
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#define LINK_UP_TIMEOUT HZ
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#define LINK_RETRAIN_TIMEOUT HZ
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@ -222,8 +223,7 @@ static int tlp_cfg_dword_read(struct altera_pcie *pcie, u8 bus, u32 devfn,
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u32 headers[TLP_HDR_SIZE];
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headers[0] = TLP_CFG_DW0(pcie, bus);
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headers[1] = TLP_CFG_DW1(TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN),
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TLP_READ_TAG, byte_en);
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headers[1] = TLP_CFG_DW1(pcie, TLP_READ_TAG, byte_en);
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headers[2] = TLP_CFG_DW2(bus, devfn, where);
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tlp_write_packet(pcie, headers, 0, false);
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@ -238,8 +238,7 @@ static int tlp_cfg_dword_write(struct altera_pcie *pcie, u8 bus, u32 devfn,
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int ret;
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headers[0] = TLP_CFG_DW0(pcie, bus);
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headers[1] = TLP_CFG_DW1(TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN),
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TLP_WRITE_TAG, byte_en);
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headers[1] = TLP_CFG_DW1(pcie, TLP_WRITE_TAG, byte_en);
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headers[2] = TLP_CFG_DW2(bus, devfn, where);
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/* check alignment to Qword */
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