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pinctrl: pinctrl-single: enhance to configure multiple pins of different modules
Add support to configure multiple pins in each register, existing
implementation added by [1] does not support full fledge multiple pin
configuration in single register, reports a pin clash when different
modules configure different bits of same register. The issue reported
and discussed here
http://www.spinics.net/lists/arm-kernel/msg235213.html
With pinctrl-single,bits-per-mux property specified, use function-mask
property to find out number pins to configure. Allocate and register
pin control functions based sub mask.
Tested on da850/omap-l138 EVM.
does not support variable submask for pins.
does not support pinconf.
[1] "pinctrl: pinctrl-single: Add pinctrl-single,bits type of mux"
(9e605cb68a),
Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com>
Reported-by: Lad, Prabhakar <prabhakar.csengg@gmail.com>
Tested-by: Lad, Prabhakar <prabhakar.csengg@gmail.com>
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Manjunathappa, Prakash
Linus Walleij
parent
ac844b6271
commit
4e7e8017a8
@ -18,7 +18,8 @@ Optional properties:
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pin functions is ignored
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- pinctrl-single,bit-per-mux : boolean to indicate that one register controls
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more than one pin
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more than one pin, for which "pinctrl-single,function-mask" property specifies
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position mask of pin.
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- pinctrl-single,drive-strength : array of value that are used to configure
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drive strength in the pinmux register. They're value of drive strength
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@ -163,6 +163,7 @@ struct pcs_name {
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* @foff: value to turn mux off
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* @fmax: max number of functions in fmask
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* @is_pinconf: whether supports pinconf
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* @bits_per_pin:number of bits per pin
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* @names: array of register names for pins
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* @pins: physical pins on the SoC
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* @pgtree: pingroup index radix tree
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@ -190,6 +191,7 @@ struct pcs_device {
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unsigned fmax;
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bool bits_per_mux;
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bool is_pinconf;
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unsigned bits_per_pin;
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struct pcs_name *names;
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struct pcs_data pins;
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struct radix_tree_root pgtree;
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@ -431,10 +433,11 @@ static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector,
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vals = &func->vals[i];
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val = pcs->read(vals->reg);
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if (!vals->mask)
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mask = pcs->fmask;
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if (pcs->bits_per_mux)
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mask = vals->mask;
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else
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mask = pcs->fmask & vals->mask;
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mask = pcs->fmask;
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val &= ~mask;
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val |= (vals->val & mask);
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@ -779,7 +782,13 @@ static int pcs_allocate_pin_table(struct pcs_device *pcs)
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int mux_bytes, nr_pins, i;
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mux_bytes = pcs->width / BITS_PER_BYTE;
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nr_pins = pcs->size / mux_bytes;
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if (pcs->bits_per_mux) {
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pcs->bits_per_pin = fls(pcs->fmask);
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nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin;
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} else {
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nr_pins = pcs->size / mux_bytes;
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}
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dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins);
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pcs->pins.pa = devm_kzalloc(pcs->dev,
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@ -800,8 +809,14 @@ static int pcs_allocate_pin_table(struct pcs_device *pcs)
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for (i = 0; i < pcs->desc.npins; i++) {
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unsigned offset;
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int res;
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int byte_num;
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offset = i * mux_bytes;
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if (pcs->bits_per_mux) {
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byte_num = (pcs->bits_per_pin * i) / BITS_PER_BYTE;
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offset = (byte_num / mux_bytes) * mux_bytes;
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} else {
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offset = i * mux_bytes;
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}
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res = pcs_add_pin(pcs, offset);
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if (res < 0) {
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dev_err(pcs->dev, "error adding pins: %i\n", res);
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@ -919,7 +934,10 @@ static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
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return -EINVAL;
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}
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index = offset / (pcs->width / BITS_PER_BYTE);
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if (pcs->bits_per_mux)
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index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin;
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else
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index = offset / (pcs->width / BITS_PER_BYTE);
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return index;
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}
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@ -1097,29 +1115,18 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
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{
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struct pcs_func_vals *vals;
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const __be32 *mux;
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int size, params, rows, *pins, index = 0, found = 0, res = -ENOMEM;
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int size, rows, *pins, index = 0, found = 0, res = -ENOMEM;
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struct pcs_function *function;
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if (pcs->bits_per_mux) {
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params = 3;
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mux = of_get_property(np, PCS_MUX_BITS_NAME, &size);
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} else {
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params = 2;
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mux = of_get_property(np, PCS_MUX_PINS_NAME, &size);
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}
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if (!mux) {
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dev_err(pcs->dev, "no valid property for %s\n", np->name);
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return -EINVAL;
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}
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if (size < (sizeof(*mux) * params)) {
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dev_err(pcs->dev, "bad data for %s\n", np->name);
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mux = of_get_property(np, PCS_MUX_PINS_NAME, &size);
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if ((!mux) || (size < sizeof(*mux) * 2)) {
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dev_err(pcs->dev, "bad data for mux %s\n",
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np->name);
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return -EINVAL;
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}
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size /= sizeof(*mux); /* Number of elements in array */
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rows = size / params;
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rows = size / 2;
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vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows, GFP_KERNEL);
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if (!vals)
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@ -1137,10 +1144,6 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
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val = be32_to_cpup(mux + index++);
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vals[found].reg = pcs->base + offset;
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vals[found].val = val;
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if (params == 3) {
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val = be32_to_cpup(mux + index++);
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vals[found].mask = val;
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}
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pin = pcs_get_pin_by_offset(pcs, offset);
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if (pin < 0) {
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@ -1184,6 +1187,125 @@ free_function:
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free_pins:
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devm_kfree(pcs->dev, pins);
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free_vals:
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devm_kfree(pcs->dev, vals);
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return res;
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}
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#define PARAMS_FOR_BITS_PER_MUX 3
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static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
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struct device_node *np,
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struct pinctrl_map **map,
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unsigned *num_maps,
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const char **pgnames)
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{
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struct pcs_func_vals *vals;
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const __be32 *mux;
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int size, rows, *pins, index = 0, found = 0, res = -ENOMEM;
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int npins_in_row;
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struct pcs_function *function;
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mux = of_get_property(np, PCS_MUX_BITS_NAME, &size);
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if (!mux) {
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dev_err(pcs->dev, "no valid property for %s\n", np->name);
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return -EINVAL;
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}
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if (size < (sizeof(*mux) * PARAMS_FOR_BITS_PER_MUX)) {
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dev_err(pcs->dev, "bad data for %s\n", np->name);
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return -EINVAL;
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}
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/* Number of elements in array */
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size /= sizeof(*mux);
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rows = size / PARAMS_FOR_BITS_PER_MUX;
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npins_in_row = pcs->width / pcs->bits_per_pin;
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vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows * npins_in_row,
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GFP_KERNEL);
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if (!vals)
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return -ENOMEM;
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pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows * npins_in_row,
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GFP_KERNEL);
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if (!pins)
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goto free_vals;
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while (index < size) {
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unsigned offset, val;
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unsigned mask, bit_pos, val_pos, mask_pos, submask;
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unsigned pin_num_from_lsb;
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int pin;
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offset = be32_to_cpup(mux + index++);
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val = be32_to_cpup(mux + index++);
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mask = be32_to_cpup(mux + index++);
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/* Parse pins in each row from LSB */
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while (mask) {
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bit_pos = ffs(mask);
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pin_num_from_lsb = bit_pos / pcs->bits_per_pin;
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mask_pos = ((pcs->fmask) << (bit_pos - 1));
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val_pos = val & mask_pos;
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submask = mask & mask_pos;
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mask &= ~mask_pos;
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if (submask != mask_pos) {
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dev_warn(pcs->dev,
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"Invalid submask 0x%x for %s at 0x%x\n",
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submask, np->name, offset);
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continue;
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}
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vals[found].mask = submask;
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vals[found].reg = pcs->base + offset;
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vals[found].val = val_pos;
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pin = pcs_get_pin_by_offset(pcs, offset);
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if (pin < 0) {
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dev_err(pcs->dev,
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"could not add functions for %s %ux\n",
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np->name, offset);
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break;
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}
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pins[found++] = pin + pin_num_from_lsb;
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}
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}
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pgnames[0] = np->name;
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function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1);
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if (!function)
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goto free_pins;
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res = pcs_add_pingroup(pcs, np, np->name, pins, found);
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if (res < 0)
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goto free_function;
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(*map)->type = PIN_MAP_TYPE_MUX_GROUP;
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(*map)->data.mux.group = np->name;
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(*map)->data.mux.function = np->name;
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if (pcs->is_pinconf) {
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dev_err(pcs->dev, "pinconf not supported\n");
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goto free_pingroups;
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}
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*num_maps = 1;
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return 0;
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free_pingroups:
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pcs_free_pingroups(pcs);
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*num_maps = 1;
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free_function:
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pcs_remove_function(pcs, function);
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free_pins:
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devm_kfree(pcs->dev, pins);
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free_vals:
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devm_kfree(pcs->dev, vals);
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@ -1219,12 +1341,22 @@ static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
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goto free_map;
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}
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ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map, num_maps,
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pgnames);
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if (ret < 0) {
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dev_err(pcs->dev, "no pins entries for %s\n",
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np_config->name);
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goto free_pgnames;
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if (pcs->bits_per_mux) {
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ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map,
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num_maps, pgnames);
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if (ret < 0) {
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dev_err(pcs->dev, "no pins entries for %s\n",
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np_config->name);
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goto free_pgnames;
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}
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} else {
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ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map,
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num_maps, pgnames);
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if (ret < 0) {
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dev_err(pcs->dev, "no pins entries for %s\n",
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np_config->name);
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goto free_pgnames;
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}
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}
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return 0;
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