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Merge branch 'i2c-embedded/for-current' of git://git.pengutronix.de/git/wsa/linux
Pull i2c embedded fixes from Wolfram Sang: "Here are some typical i2c driver bugfixes for 3.4. Missed clock handling, improper timeout fixes, hardware wrokarounds... All patches have been in linux-next for a few days, too." * 'i2c-embedded/for-current' of git://git.pengutronix.de/git/wsa/linux: i2c: mxs: disable QUEUE when sending is done i2c: mxs: handle spurious interrupt i2c-eg20t: Modify MODULE_AUTHOR's email address i2c-eg20t: change timeout value 50msec to 1000msec i2c: tegra: Add delay before resetting the controller after NACK i2c: pnx: Disable clk in suspend
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commit
4e78f00261
@ -324,7 +324,7 @@ static s32 pch_i2c_wait_for_xfer_complete(struct i2c_algo_pch_data *adap)
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{
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long ret;
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ret = wait_event_timeout(pch_event,
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(adap->pch_event_flag != 0), msecs_to_jiffies(50));
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(adap->pch_event_flag != 0), msecs_to_jiffies(1000));
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if (ret == 0) {
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pch_err(adap, "timeout: %x\n", adap->pch_event_flag);
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@ -1063,6 +1063,6 @@ module_exit(pch_pci_exit);
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MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semico ML7213/ML7223/ML7831 IOH I2C");
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Tomoya MORINAGA. <tomoya-linux@dsn.lapis-semi.com>");
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MODULE_AUTHOR("Tomoya MORINAGA. <tomoya.rohm@gmail.com>");
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module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR));
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module_param(pch_clk, int, (S_IRUSR | S_IWUSR));
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@ -227,6 +227,7 @@ static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg,
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return -EINVAL;
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init_completion(&i2c->cmd_complete);
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i2c->cmd_err = 0;
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flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0;
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@ -252,6 +253,9 @@ static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg,
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if (i2c->cmd_err == -ENXIO)
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mxs_i2c_reset(i2c);
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else
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writel(MXS_I2C_QUEUECTRL_QUEUE_RUN,
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i2c->regs + MXS_I2C_QUEUECTRL_CLR);
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dev_dbg(i2c->dev, "Done with err=%d\n", i2c->cmd_err);
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@ -299,8 +303,6 @@ static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id)
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MXS_I2C_CTRL1_SLAVE_STOP_IRQ | MXS_I2C_CTRL1_SLAVE_IRQ))
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/* MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ is only for slaves */
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i2c->cmd_err = -EIO;
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else
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i2c->cmd_err = 0;
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is_last_cmd = (readl(i2c->regs + MXS_I2C_QUEUESTAT) &
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MXS_I2C_QUEUESTAT_WRITE_QUEUE_CNT_MASK) == 0;
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@ -384,8 +386,6 @@ static int __devexit mxs_i2c_remove(struct platform_device *pdev)
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if (ret)
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return -EBUSY;
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writel(MXS_I2C_QUEUECTRL_QUEUE_RUN,
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i2c->regs + MXS_I2C_QUEUECTRL_CLR);
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writel(MXS_I2C_CTRL0_SFTRST, i2c->regs + MXS_I2C_CTRL0_SET);
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platform_set_drvdata(pdev, NULL);
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@ -546,8 +546,7 @@ static int i2c_pnx_controller_suspend(struct platform_device *pdev,
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{
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struct i2c_pnx_algo_data *alg_data = platform_get_drvdata(pdev);
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/* FIXME: shouldn't this be clk_disable? */
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clk_enable(alg_data->clk);
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clk_disable(alg_data->clk);
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return 0;
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}
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@ -516,6 +516,14 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
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if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
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return 0;
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/*
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* NACK interrupt is generated before the I2C controller generates the
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* STOP condition on the bus. So wait for 2 clock periods before resetting
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* the controller so that STOP condition has been delivered properly.
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*/
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if (i2c_dev->msg_err == I2C_ERR_NO_ACK)
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udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
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tegra_i2c_init(i2c_dev);
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if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
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if (msg->flags & I2C_M_IGNORE_NAK)
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