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drm/amdgpu: Add a kernel parameter for specifying the asic type

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As more and more new asics start to reuse the old device IDs before
launch, there is a need to quickly override the existing asic type
corresponding to the reused device ID through a kernel parameter. With
this, engineers no longer need to rely on local hack patches,
facilitating cooperation across teams.

Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Yong Zhao 2019-08-30 18:09:10 -04:00 committed by Alex Deucher
parent bb42eda284
commit 4e66d7d215
4 changed files with 45 additions and 28 deletions
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1
drivers/gpu/drm/amd/amdgpu/amdgpu.h
View File

@ -168,6 +168,7 @@ extern int amdgpu_mcbp;
extern int amdgpu_discovery;
extern int amdgpu_mes;
extern int amdgpu_noretry;
extern int amdgpu_force_asic_type;
#ifdef CONFIG_DRM_AMDGPU_SI
extern int amdgpu_si_support;

7
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
View File

@ -2585,7 +2585,12 @@ int amdgpu_device_init(struct amdgpu_device *adev,
adev->ddev = ddev;
adev->pdev = pdev;
adev->flags = flags;
adev->asic_type = flags & AMD_ASIC_MASK;
if (amdgpu_force_asic_type >= 0 && amdgpu_force_asic_type < CHIP_LAST)
adev->asic_type = amdgpu_force_asic_type;
else
adev->asic_type = flags & AMD_ASIC_MASK;
adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
if (amdgpu_emu_mode == 1)
adev->usec_timeout *= 2;

11
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
View File

@ -146,6 +146,7 @@ int amdgpu_mcbp = 0;
int amdgpu_discovery = -1;
int amdgpu_mes = 0;
int amdgpu_noretry = 1;
int amdgpu_force_asic_type = -1;
struct amdgpu_mgpu_info mgpu_info = {
.mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
@ -616,6 +617,16 @@ MODULE_PARM_DESC(noretry,
"Disable retry faults (0 = retry enabled, 1 = retry disabled (default))");
module_param_named(noretry, amdgpu_noretry, int, 0644);
/**
* DOC: force_asic_type (int)
* A non negative value used to specify the asic type for all supported GPUs.
*/
MODULE_PARM_DESC(force_asic_type,
"A non negative value used to specify the asic type for all supported GPUs");
module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444);
#ifdef CONFIG_HSA_AMD
/**
* DOC: sched_policy (int)

54
include/drm/amd_asic_type.h
View File

@ -27,33 +27,33 @@
*/
enum amd_asic_type {
CHIP_TAHITI = 0,
CHIP_PITCAIRN,
CHIP_VERDE,
CHIP_OLAND,
CHIP_HAINAN,
CHIP_BONAIRE,
CHIP_KAVERI,
CHIP_KABINI,
CHIP_HAWAII,
CHIP_MULLINS,
CHIP_TOPAZ,
CHIP_TONGA,
CHIP_FIJI,
CHIP_CARRIZO,
CHIP_STONEY,
CHIP_POLARIS10,
CHIP_POLARIS11,
CHIP_POLARIS12,
CHIP_VEGAM,
CHIP_VEGA10,
CHIP_VEGA12,
CHIP_VEGA20,
CHIP_RAVEN,
CHIP_ARCTURUS,
CHIP_RENOIR,
CHIP_NAVI10,
CHIP_NAVI14,
CHIP_NAVI12,
CHIP_PITCAIRN, /* 1 */
CHIP_VERDE, /* 2 */
CHIP_OLAND, /* 3 */
CHIP_HAINAN, /* 4 */
CHIP_BONAIRE, /* 5 */
CHIP_KAVERI, /* 6 */
CHIP_KABINI, /* 7 */
CHIP_HAWAII, /* 8 */
CHIP_MULLINS, /* 9 */
CHIP_TOPAZ, /* 10 */
CHIP_TONGA, /* 11 */
CHIP_FIJI, /* 12 */
CHIP_CARRIZO, /* 13 */
CHIP_STONEY, /* 14 */
CHIP_POLARIS10, /* 15 */
CHIP_POLARIS11, /* 16 */
CHIP_POLARIS12, /* 17 */
CHIP_VEGAM, /* 18 */
CHIP_VEGA10, /* 19 */
CHIP_VEGA12, /* 20 */
CHIP_VEGA20, /* 21 */
CHIP_RAVEN, /* 22 */
CHIP_ARCTURUS, /* 23 */
CHIP_RENOIR, /* 24 */
CHIP_NAVI10, /* 25 */
CHIP_NAVI14, /* 26 */
CHIP_NAVI12, /* 27 */
CHIP_LAST,
};