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ARM: exynos4: convert to CONFIG_MULTI_IRQ_HANDLER
Convert the Exynos4 platforms to be using the gic_handle_irq function as their primary interrupt handler. Cc: Ben Dooks <ben-linux@fluff.org> Cc: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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@ -854,6 +854,7 @@ config ARCH_EXYNOS
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select HAVE_S3C2410_I2C if I2C
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select HAVE_S3C2410_WATCHDOG if WATCHDOG
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select NEED_MACH_MEMORY_H
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select MULTI_IRQ_HANDLER
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help
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Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
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@ -15,6 +15,7 @@
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#include <asm/mach/irq.h>
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#include <asm/proc-fns.h>
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#include <asm/exception.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/hardware/gic.h>
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@ -33,8 +34,6 @@
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#include <mach/regs-irq.h>
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#include <mach/regs-pmu.h>
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unsigned int gic_bank_offset __read_mostly;
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extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
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unsigned int irq_start);
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extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
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@ -210,6 +209,7 @@ void __init exynos4_init_clocks(int xtal)
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void __init exynos4_init_irq(void)
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{
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int irq;
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unsigned int bank_offset;
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gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
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@ -9,83 +9,8 @@
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* warranty of any kind, whether express or implied.
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*/
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#include <mach/hardware.h>
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#include <mach/map.h>
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#include <asm/hardware/gic.h>
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.macro disable_fiq
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.endm
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.macro get_irqnr_preamble, base, tmp
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mov \tmp, #0
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mrc p15, 0, \base, c0, c0, 5
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and \base, \base, #3
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cmp \base, #0
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beq 1f
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ldr \tmp, =gic_bank_offset
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ldr \tmp, [\tmp]
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cmp \base, #1
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beq 1f
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cmp \base, #2
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addeq \tmp, \tmp, \tmp
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addne \tmp, \tmp, \tmp, LSL #1
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1: ldr \base, =gic_cpu_base_addr
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ldr \base, [\base]
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add \base, \base, \tmp
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.endm
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.macro arch_ret_to_user, tmp1, tmp2
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.endm
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/*
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* The interrupt numbering scheme is defined in the
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* interrupt controller spec. To wit:
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*
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* Interrupts 0-15 are IPI
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* 16-28 are reserved
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* 29-31 are local. We allow 30 to be used for the watchdog.
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* 32-1020 are global
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* 1021-1022 are reserved
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* 1023 is "spurious" (no interrupt)
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*
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* For now, we ignore all local interrupts so only return an interrupt if it's
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* between 30 and 1020. The test_for_ipi routine below will pick up on IPIs.
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*
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* A simple read from the controller will tell us the number of the highest
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* priority enabled interrupt. We then just need to check whether it is in the
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* valid range for an IRQ (30-1020 inclusive).
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*/
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
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ldr \tmp, =1021
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bic \irqnr, \irqstat, #0x1c00
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cmp \irqnr, #15
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cmpcc \irqnr, \irqnr
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cmpne \irqnr, \tmp
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cmpcs \irqnr, \irqnr
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addne \irqnr, \irqnr, #32
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.endm
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/* We assume that irqstat (the raw value of the IRQ acknowledge
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* register) is preserved from the macro above.
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* If there is an IPI, we immediately signal end of interrupt on the
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* controller, since this requires the original irqstat value which
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* we won't easily be able to recreate later.
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*/
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.macro test_for_ipi, irqnr, irqstat, base, tmp
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bic \irqnr, \irqstat, #0x1c00
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cmp \irqnr, #16
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strcc \irqstat, [\base, #GIC_CPU_EOI]
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cmpcs \irqnr, \irqnr
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.endm
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@ -16,6 +16,7 @@
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#include <linux/smsc911x.h>
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#include <asm/mach/arch.h>
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#include <asm/hardware/gic.h>
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#include <asm/mach-types.h>
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#include <plat/cpu.h>
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@ -210,6 +211,7 @@ MACHINE_START(ARMLEX4210, "ARMLEX4210")
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.atag_offset = 0x100,
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.init_irq = exynos4_init_irq,
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.map_io = armlex4210_map_io,
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.handle_irq = gic_handle_irq,
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.init_machine = armlex4210_machine_init,
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.timer = &exynos4_timer,
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MACHINE_END
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@ -32,6 +32,7 @@
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#include <media/v4l2-mediabus.h>
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#include <asm/mach/arch.h>
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#include <asm/hardware/gic.h>
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#include <asm/mach-types.h>
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#include <plat/adc.h>
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@ -1333,6 +1334,7 @@ MACHINE_START(NURI, "NURI")
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.atag_offset = 0x100,
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.init_irq = exynos4_init_irq,
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.map_io = nuri_map_io,
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.handle_irq = gic_handle_irq,
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.init_machine = nuri_machine_init,
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.timer = &exynos4_timer,
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.reserve = &nuri_reserve,
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@ -22,6 +22,7 @@
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#include <linux/lcd.h>
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#include <asm/mach/arch.h>
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#include <asm/hardware/gic.h>
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#include <asm/mach-types.h>
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#include <video/platform_lcd.h>
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@ -694,6 +695,7 @@ MACHINE_START(ORIGEN, "ORIGEN")
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.atag_offset = 0x100,
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.init_irq = exynos4_init_irq,
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.map_io = origen_map_io,
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.handle_irq = gic_handle_irq,
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.init_machine = origen_machine_init,
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.timer = &exynos4_timer,
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.reserve = &origen_reserve,
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@ -21,6 +21,7 @@
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#include <linux/serial_core.h>
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#include <asm/mach/arch.h>
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#include <asm/hardware/gic.h>
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#include <asm/mach-types.h>
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#include <plat/backlight.h>
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@ -287,6 +288,7 @@ MACHINE_START(SMDK4212, "SMDK4212")
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.atag_offset = 0x100,
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.init_irq = exynos4_init_irq,
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.map_io = smdk4x12_map_io,
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.handle_irq = gic_handle_irq,
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.init_machine = smdk4x12_machine_init,
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.timer = &exynos4_timer,
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MACHINE_END
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@ -297,6 +299,7 @@ MACHINE_START(SMDK4412, "SMDK4412")
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.atag_offset = 0x100,
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.init_irq = exynos4_init_irq,
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.map_io = smdk4x12_map_io,
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.handle_irq = gic_handle_irq,
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.init_machine = smdk4x12_machine_init,
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.timer = &exynos4_timer,
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MACHINE_END
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@ -21,6 +21,7 @@
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#include <linux/pwm_backlight.h>
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#include <asm/mach/arch.h>
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#include <asm/hardware/gic.h>
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#include <asm/mach-types.h>
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#include <video/platform_lcd.h>
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@ -375,6 +376,7 @@ MACHINE_START(SMDKV310, "SMDKV310")
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.atag_offset = 0x100,
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.init_irq = exynos4_init_irq,
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.map_io = smdkv310_map_io,
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.handle_irq = gic_handle_irq,
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.init_machine = smdkv310_machine_init,
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.timer = &exynos4_timer,
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.reserve = &smdkv310_reserve,
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@ -385,6 +387,7 @@ MACHINE_START(SMDKC210, "SMDKC210")
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.atag_offset = 0x100,
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.init_irq = exynos4_init_irq,
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.map_io = smdkv310_map_io,
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.handle_irq = gic_handle_irq,
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.init_machine = smdkv310_machine_init,
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.timer = &exynos4_timer,
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MACHINE_END
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@ -21,9 +21,10 @@
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#include <linux/mmc/host.h>
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#include <linux/i2c-gpio.h>
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#include <linux/i2c/mcs.h>
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#include <linux/i2c/atmel_mxt_ts.h>
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<linux/i2c/atmel_mxt_ts.h>
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#include <asm/mach/arch.h>
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#include <asm/hardware/gic.h>
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#include <asm/mach-types.h>
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#include <plat/regs-serial.h>
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@ -1058,6 +1059,7 @@ MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
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.atag_offset = 0x100,
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.init_irq = exynos4_init_irq,
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.map_io = universal_map_io,
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.handle_irq = gic_handle_irq,
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.init_machine = universal_machine_init,
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.timer = &exynos4_timer,
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.reserve = &universal_reserve,
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