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clk: renesas: Updates for v4.13

Browse Source 
- Add more module clocks for R-Car H3 ES2.0 and M3-W,
   - Add CPG/MSSR drivers for all supported R-Car Gen2 SoCs, enabling support
     for module resets, which are not supported by the existing driver,
   - Rework Kconfig and Makefile logic,
   - Small fixes and cleanups.
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Merge tag 'clk-renesas-for-v4.13-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next

clk: renesas: Updates for v4.13

  - Add more module clocks for R-Car H3 ES2.0 and M3-W,
  - Add CPG/MSSR drivers for all supported R-Car Gen2 SoCs, enabling support
    for module resets, which are not supported by the existing driver,
  - Rework Kconfig and Makefile logic,
  - Small fixes and cleanups.
This commit is contained in:
Michael Turquette 2017-06-02 14:03:59 +09:00
commit 4e19dcd93b
20 changed files with 1565 additions and 74 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
View File

@ -15,6 +15,11 @@ Required Properties:
- compatible: Must be one of:
- "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M)
- "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E)
- "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2)
- "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W)
- "renesas,r8a7792-cpg-mssr" for the r8a7792 SoC (R-Car V2H)
- "renesas,r8a7793-cpg-mssr" for the r8a7793 SoC (R-Car M2-N)
- "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2)
- "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
- "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
@ -24,9 +29,10 @@ Required Properties:
- clocks: References to external parent clocks, one entry for each entry in
clock-names
- clock-names: List of external parent clock names. Valid names are:
- "extal" (r8a7743, r8a7745, r8a7795, r8a7796)
- "extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,
r8a7795, r8a7796)
- "extalr" (r8a7795, r8a7796)
- "usb_extal" (r8a7743, r8a7745)
- "usb_extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7793, r8a7794)
- #clock-cells: Must be 2
- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"

2
drivers/clk/Makefile
View File

@ -75,7 +75,7 @@ obj-$(CONFIG_COMMON_CLK_NXP) += nxp/
obj-$(CONFIG_MACH_PISTACHIO) += pistachio/
obj-$(CONFIG_COMMON_CLK_PXA) += pxa/
obj-$(CONFIG_COMMON_CLK_QCOM) += qcom/
obj-$(CONFIG_ARCH_RENESAS) += renesas/
obj-y += renesas/
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/
obj-$(CONFIG_ARCH_SIRF) += sirf/

139
drivers/clk/renesas/Kconfig
View File

@ -1,20 +1,129 @@
config CLK_RENESAS
bool "Renesas SoC clock support" if COMPILE_TEST && !ARCH_RENESAS
default y if ARCH_RENESAS
select CLK_EMEV2 if ARCH_EMEV2
select CLK_RZA1 if ARCH_R7S72100
select CLK_R8A73A4 if ARCH_R8A73A4
select CLK_R8A7740 if ARCH_R8A7740
select CLK_R8A7743 if ARCH_R8A7743
select CLK_R8A7745 if ARCH_R8A7745
select CLK_R8A7778 if ARCH_R8A7778
select CLK_R8A7779 if ARCH_R8A7779
select CLK_R8A7790 if ARCH_R8A7790
select CLK_R8A7791 if ARCH_R8A7791 || ARCH_R8A7793
select CLK_R8A7792 if ARCH_R8A7792
select CLK_R8A7794 if ARCH_R8A7794
select CLK_R8A7795 if ARCH_R8A7795
select CLK_R8A7796 if ARCH_R8A7796
select CLK_SH73A0 if ARCH_SH73A0
if CLK_RENESAS
config CLK_RENESAS_LEGACY
bool "Legacy DT clock support"
depends on CLK_R8A7790 || CLK_R8A7791 || CLK_R8A7792 || CLK_R8A7794
default y
help
Enable backward compatibility with old device trees describing a
hierarchical representation of the various CPG and MSTP clocks.
Say Y if you want your kernel to work with old DTBs.
# SoC
config CLK_EMEV2
bool "Emma Mobile EV2 clock support" if COMPILE_TEST
config CLK_RZA1
bool
select CLK_RENESAS_CPG_MSTP
config CLK_R8A73A4
bool
select CLK_RENESAS_CPG_MSTP
select CLK_RENESAS_DIV6
config CLK_R8A7740
bool
select CLK_RENESAS_CPG_MSTP
select CLK_RENESAS_DIV6
config CLK_R8A7743
bool
select CLK_RCAR_GEN2_CPG
config CLK_R8A7745
bool
select CLK_RCAR_GEN2_CPG
config CLK_R8A7778
bool
select CLK_RENESAS_CPG_MSTP
config CLK_R8A7779
bool
select CLK_RENESAS_CPG_MSTP
config CLK_R8A7790
bool
select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY
select CLK_RCAR_GEN2_CPG
select CLK_RENESAS_DIV6
config CLK_R8A7791
bool
select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY
select CLK_RCAR_GEN2_CPG
select CLK_RENESAS_DIV6
config CLK_R8A7792
bool
select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY
select CLK_RCAR_GEN2_CPG
config CLK_R8A7794
bool
select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY
select CLK_RCAR_GEN2_CPG
select CLK_RENESAS_DIV6
config CLK_R8A7795
bool
select CLK_RCAR_GEN3_CPG
config CLK_R8A7796
bool
select CLK_RCAR_GEN3_CPG
config CLK_SH73A0
bool
select CLK_RENESAS_CPG_MSTP
select CLK_RENESAS_DIV6
# Family
config CLK_RCAR_GEN2
bool
select CLK_RENESAS_CPG_MSTP
select CLK_RENESAS_DIV6
config CLK_RCAR_GEN2_CPG
bool
select CLK_RENESAS_CPG_MSSR
config CLK_RCAR_GEN3_CPG
bool
select CLK_RENESAS_CPG_MSSR
# Generic
config CLK_RENESAS_CPG_MSSR
bool
default y if ARCH_R8A7743
default y if ARCH_R8A7745
default y if ARCH_R8A7795
default y if ARCH_R8A7796
select CLK_RENESAS_DIV6
config CLK_RENESAS_CPG_MSTP
bool
default y if ARCH_R7S72100
default y if ARCH_R8A73A4
default y if ARCH_R8A7740
default y if ARCH_R8A7778
default y if ARCH_R8A7779
default y if ARCH_R8A7790
default y if ARCH_R8A7791
default y if ARCH_R8A7792
default y if ARCH_R8A7793
default y if ARCH_R8A7794
default y if ARCH_SH73A0
config CLK_RENESAS_DIV6
bool "DIV6 clock support" if COMPILE_TEST
endif # CLK_RENESAS

41
drivers/clk/renesas/Makefile
View File

@ -1,19 +1,26 @@
obj-$(CONFIG_ARCH_EMEV2) += clk-emev2.o
obj-$(CONFIG_ARCH_R7S72100) += clk-rz.o
obj-$(CONFIG_ARCH_R8A73A4) += clk-r8a73a4.o clk-div6.o
obj-$(CONFIG_ARCH_R8A7740) += clk-r8a7740.o clk-div6.o
obj-$(CONFIG_ARCH_R8A7743) += r8a7743-cpg-mssr.o rcar-gen2-cpg.o
obj-$(CONFIG_ARCH_R8A7745) += r8a7745-cpg-mssr.o rcar-gen2-cpg.o
obj-$(CONFIG_ARCH_R8A7778) += clk-r8a7778.o
obj-$(CONFIG_ARCH_R8A7779) += clk-r8a7779.o
obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o clk-div6.o
obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o clk-div6.o
obj-$(CONFIG_ARCH_R8A7792) += clk-rcar-gen2.o clk-div6.o
obj-$(CONFIG_ARCH_R8A7793) += clk-rcar-gen2.o clk-div6.o
obj-$(CONFIG_ARCH_R8A7794) += clk-rcar-gen2.o clk-div6.o
obj-$(CONFIG_ARCH_R8A7795) += r8a7795-cpg-mssr.o rcar-gen3-cpg.o
obj-$(CONFIG_ARCH_R8A7796) += r8a7796-cpg-mssr.o rcar-gen3-cpg.o
obj-$(CONFIG_ARCH_SH73A0) += clk-sh73a0.o clk-div6.o
# SoC
obj-$(CONFIG_CLK_EMEV2) += clk-emev2.o
obj-$(CONFIG_CLK_RZA1) += clk-rz.o
obj-$(CONFIG_CLK_R8A73A4) += clk-r8a73a4.o
obj-$(CONFIG_CLK_R8A7740) += clk-r8a7740.o
obj-$(CONFIG_CLK_R8A7743) += r8a7743-cpg-mssr.o
obj-$(CONFIG_CLK_R8A7745) += r8a7745-cpg-mssr.o
obj-$(CONFIG_CLK_R8A7778) += clk-r8a7778.o
obj-$(CONFIG_CLK_R8A7779) += clk-r8a7779.o
obj-$(CONFIG_CLK_R8A7790) += r8a7790-cpg-mssr.o
obj-$(CONFIG_CLK_R8A7791) += r8a7791-cpg-mssr.o
obj-$(CONFIG_CLK_R8A7792) += r8a7792-cpg-mssr.o
obj-$(CONFIG_CLK_R8A7794) += r8a7794-cpg-mssr.o
obj-$(CONFIG_CLK_R8A7795) += r8a7795-cpg-mssr.o
obj-$(CONFIG_CLK_R8A7796) += r8a7796-cpg-mssr.o
obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
obj-$(CONFIG_CLK_RENESAS_CPG_MSSR) += renesas-cpg-mssr.o clk-div6.o
# Family
obj-$(CONFIG_CLK_RCAR_GEN2) += clk-rcar-gen2.o
obj-$(CONFIG_CLK_RCAR_GEN2_CPG) += rcar-gen2-cpg.o
obj-$(CONFIG_CLK_RCAR_GEN3_CPG) += rcar-gen3-cpg.o
# Generic
obj-$(CONFIG_CLK_RENESAS_CPG_MSSR) += renesas-cpg-mssr.o
obj-$(CONFIG_CLK_RENESAS_CPG_MSTP) += clk-mstp.o
obj-$(CONFIG_CLK_RENESAS_DIV6) += clk-div6.o

2
drivers/clk/renesas/clk-mstp.c
View File

@ -325,7 +325,7 @@ fail_put:
void cpg_mstp_detach_dev(struct generic_pm_domain *unused, struct device *dev)
{
if (!list_empty(&dev->power.subsys_data->clock_list))
if (!pm_clk_no_clocks(dev))
pm_clk_destroy(dev);
}

23
drivers/clk/renesas/clk-rcar-gen2.c
View File

@ -272,11 +272,14 @@ struct cpg_pll_config {
unsigned int extal_div;
unsigned int pll1_mult;
unsigned int pll3_mult;
unsigned int pll0_mult; /* For R-Car V2H and E2 only */
};
static const struct cpg_pll_config cpg_pll_configs[8] __initconst = {
{ 1, 208, 106 }, { 1, 208, 88 }, { 1, 156, 80 }, { 1, 156, 66 },
{ 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208, 88 },
{ 1, 208, 106, 200 }, { 1, 208, 88, 200 },
{ 1, 156, 80, 150 }, { 1, 156, 66, 150 },
{ 2, 240, 122, 230 }, { 2, 240, 102, 230 },
{ 2, 208, 106, 200 }, { 2, 208, 88, 200 },
};
/* SDHI divisors */
@ -298,6 +301,12 @@ static const struct clk_div_table cpg_sd01_div_table[] = {
static u32 cpg_mode __initdata;
static const char * const pll0_mult_match[] = {
"renesas,r8a7792-cpg-clocks",
"renesas,r8a7794-cpg-clocks",
NULL
};
static struct clk * __init
rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg,
const struct cpg_pll_config *config,
@ -318,9 +327,15 @@ rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg,
* clock implementation and we currently have no need to change
* the multiplier value.
*/
u32 value = clk_readl(cpg->reg + CPG_PLL0CR);
if (of_device_compatible_match(np, pll0_mult_match)) {
/* R-Car V2H and E2 do not have PLL0CR */
mult = config->pll0_mult;
div = 3;
} else {
u32 value = clk_readl(cpg->reg + CPG_PLL0CR);
mult = ((value >> 24) & ((1 << 7) - 1)) + 1;
}
parent_name = "main";
mult = ((value >> 24) & ((1 << 7) - 1)) + 1;
} else if (!strcmp(name, "pll1")) {
parent_name = "main";
mult = config->pll1_mult / 2;

17
drivers/clk/renesas/r8a7745-cpg-mssr.c
View File

@ -167,16 +167,12 @@ static const struct mssr_mod_clk r8a7745_mod_clks[] __initconst = {
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
DEF_MOD("scifa3", 1106, R8A7745_CLK_MP),
DEF_MOD("scifa4", 1107, R8A7745_CLK_MP),
DEF_MOD("scifa5", 1108, R8A7745_CLK_MP),
@ -194,31 +190,22 @@ static const unsigned int r8a7745_crit_mod_clks[] __initconst = {
* MD EXTAL PLL0 PLL1 PLL3
* 14 13 19 (MHz) *1 *2
*---------------------------------------------------
* 0 0 0 15 x200/3 x208/2 x106
* 0 0 1 15 x200/3 x208/2 x88
* 0 1 0 20 x150/3 x156/2 x80
* 0 1 1 20 x150/3 x156/2 x66
* 1 0 0 26 / 2 x230/3 x240/2 x122
* 1 0 1 26 / 2 x230/3 x240/2 x102
* 1 1 0 30 / 2 x200/3 x208/2 x106
* 1 1 1 30 / 2 x200/3 x208/2 x88
*
* *1 : Table 7.5b indicates VCO output (PLL0 = VCO/3)
* *2 : Table 7.5b indicates VCO output (PLL1 = VCO/2)
*/
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
(((md) & BIT(13)) >> 12) | \
(((md) & BIT(19)) >> 19))
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
(((md) & BIT(13)) >> 13))
static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
/* EXTAL div PLL1 mult PLL3 mult PLL0 mult */
{ 1, 208, 106, 200 },
{ 1, 208, 88, 200 },
{ 1, 156, 80, 150 },
{ 1, 156, 66, 150 },
{ 2, 240, 122, 230 },
{ 2, 240, 102, 230 },
{ 2, 208, 106, 200 },
{ 2, 208, 88, 200 },
};

278
drivers/clk/renesas/r8a7790-cpg-mssr.c Normal file
View File

@ -0,0 +1,278 @@
/*
* r8a7790 Clock Pulse Generator / Module Standby and Software Reset
*
* Copyright (C) 2017 Glider bvba
*
* Based on clk-rcar-gen2.c
*
* Copyright (C) 2013 Ideas On Board SPRL
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*/
#include <linux/device.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/soc/renesas/rcar-rst.h>
#include <dt-bindings/clock/r8a7790-cpg-mssr.h>
#include "renesas-cpg-mssr.h"
#include "rcar-gen2-cpg.h"
enum clk_ids {
/* Core Clock Outputs exported to DT */
LAST_DT_CORE_CLK = R8A7790_CLK_OSC,
/* External Input Clocks */
CLK_EXTAL,
CLK_USB_EXTAL,
/* Internal Core Clocks */
CLK_MAIN,
CLK_PLL0,
CLK_PLL1,
CLK_PLL3,
CLK_PLL1_DIV2,
/* Module Clocks */
MOD_CLK_BASE
};
static const struct cpg_core_clk r8a7790_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("usb_extal", CLK_USB_EXTAL),
/* Internal Core Clocks */
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
/* Core Clock Outputs */
DEF_BASE("z", R8A7790_CLK_Z, CLK_TYPE_GEN2_Z, CLK_PLL0),
DEF_BASE("lb", R8A7790_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1),
DEF_BASE("adsp", R8A7790_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),
DEF_BASE("sdh", R8A7790_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
DEF_BASE("sd0", R8A7790_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
DEF_BASE("sd1", R8A7790_CLK_SD1, CLK_TYPE_GEN2_SD1, CLK_PLL1),
DEF_BASE("qspi", R8A7790_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
DEF_BASE("rcan", R8A7790_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL),
DEF_FIXED("z2", R8A7790_CLK_Z2, CLK_PLL1, 2, 1),
DEF_FIXED("zg", R8A7790_CLK_ZG, CLK_PLL1, 3, 1),
DEF_FIXED("zx", R8A7790_CLK_ZX, CLK_PLL1, 3, 1),
DEF_FIXED("zs", R8A7790_CLK_ZS, CLK_PLL1, 6, 1),
DEF_FIXED("hp", R8A7790_CLK_HP, CLK_PLL1, 12, 1),
DEF_FIXED("i", R8A7790_CLK_I, CLK_PLL1, 2, 1),
DEF_FIXED("b", R8A7790_CLK_B, CLK_PLL1, 12, 1),
DEF_FIXED("p", R8A7790_CLK_P, CLK_PLL1, 24, 1),
DEF_FIXED("cl", R8A7790_CLK_CL, CLK_PLL1, 48, 1),
DEF_FIXED("m2", R8A7790_CLK_M2, CLK_PLL1, 8, 1),
DEF_FIXED("imp", R8A7790_CLK_IMP, CLK_PLL1, 4, 1),
DEF_FIXED("zb3", R8A7790_CLK_ZB3, CLK_PLL3, 4, 1),
DEF_FIXED("zb3d2", R8A7790_CLK_ZB3D2, CLK_PLL3, 8, 1),
DEF_FIXED("ddr", R8A7790_CLK_DDR, CLK_PLL3, 8, 1),
DEF_FIXED("mp", R8A7790_CLK_MP, CLK_PLL1_DIV2, 15, 1),
DEF_FIXED("cp", R8A7790_CLK_CP, CLK_EXTAL, 2, 1),
DEF_FIXED("r", R8A7790_CLK_R, CLK_PLL1, 49152, 1),
DEF_FIXED("osc", R8A7790_CLK_OSC, CLK_PLL1, 12288, 1),
DEF_DIV6P1("sd2", R8A7790_CLK_SD2, CLK_PLL1_DIV2, 0x078),
DEF_DIV6P1("sd3", R8A7790_CLK_SD3, CLK_PLL1_DIV2, 0x26c),
DEF_DIV6P1("mmc0", R8A7790_CLK_MMC0, CLK_PLL1_DIV2, 0x240),
DEF_DIV6P1("mmc1", R8A7790_CLK_MMC1, CLK_PLL1_DIV2, 0x244),
DEF_DIV6P1("ssp", R8A7790_CLK_SSP, CLK_PLL1_DIV2, 0x248),
DEF_DIV6P1("ssprs", R8A7790_CLK_SSPRS, CLK_PLL1_DIV2, 0x24c),
};
static const struct mssr_mod_clk r8a7790_mod_clks[] __initconst = {
DEF_MOD("msiof0", 0, R8A7790_CLK_MP),
DEF_MOD("vcp1", 100, R8A7790_CLK_ZS),
DEF_MOD("vcp0", 101, R8A7790_CLK_ZS),
DEF_MOD("vpc1", 102, R8A7790_CLK_ZS),
DEF_MOD("vpc0", 103, R8A7790_CLK_ZS),
DEF_MOD("jpu", 106, R8A7790_CLK_M2),
DEF_MOD("ssp1", 109, R8A7790_CLK_ZS),
DEF_MOD("tmu1", 111, R8A7790_CLK_P),
DEF_MOD("3dg", 112, R8A7790_CLK_ZG),
DEF_MOD("2d-dmac", 115, R8A7790_CLK_ZS),
DEF_MOD("fdp1-2", 117, R8A7790_CLK_ZS),
DEF_MOD("fdp1-1", 118, R8A7790_CLK_ZS),
DEF_MOD("fdp1-0", 119, R8A7790_CLK_ZS),
DEF_MOD("tmu3", 121, R8A7790_CLK_P),
DEF_MOD("tmu2", 122, R8A7790_CLK_P),
DEF_MOD("cmt0", 124, R8A7790_CLK_R),
DEF_MOD("tmu0", 125, R8A7790_CLK_CP),
DEF_MOD("vsp1du1", 127, R8A7790_CLK_ZS),
DEF_MOD("vsp1du0", 128, R8A7790_CLK_ZS),
DEF_MOD("vsp1-rt", 130, R8A7790_CLK_ZS),
DEF_MOD("vsp1-sy", 131, R8A7790_CLK_ZS),
DEF_MOD("scifa2", 202, R8A7790_CLK_MP),
DEF_MOD("scifa1", 203, R8A7790_CLK_MP),
DEF_MOD("scifa0", 204, R8A7790_CLK_MP),
DEF_MOD("msiof2", 205, R8A7790_CLK_MP),
DEF_MOD("scifb0", 206, R8A7790_CLK_MP),
DEF_MOD("scifb1", 207, R8A7790_CLK_MP),
DEF_MOD("msiof1", 208, R8A7790_CLK_MP),
DEF_MOD("msiof3", 215, R8A7790_CLK_MP),
DEF_MOD("scifb2", 216, R8A7790_CLK_MP),
DEF_MOD("sys-dmac1", 218, R8A7790_CLK_ZS),
DEF_MOD("sys-dmac0", 219, R8A7790_CLK_ZS),
DEF_MOD("iic2", 300, R8A7790_CLK_HP),
DEF_MOD("tpu0", 304, R8A7790_CLK_CP),
DEF_MOD("mmcif1", 305, R8A7790_CLK_MMC1),
DEF_MOD("scif2", 310, R8A7790_CLK_P),
DEF_MOD("sdhi3", 311, R8A7790_CLK_SD3),
DEF_MOD("sdhi2", 312, R8A7790_CLK_SD2),
DEF_MOD("sdhi1", 313, R8A7790_CLK_SD1),
DEF_MOD("sdhi0", 314, R8A7790_CLK_SD0),
DEF_MOD("mmcif0", 315, R8A7790_CLK_MMC0),
DEF_MOD("iic0", 318, R8A7790_CLK_HP),
DEF_MOD("pciec", 319, R8A7790_CLK_MP),
DEF_MOD("iic1", 323, R8A7790_CLK_HP),
DEF_MOD("usb3.0", 328, R8A7790_CLK_MP),
DEF_MOD("cmt1", 329, R8A7790_CLK_R),
DEF_MOD("usbhs-dmac0", 330, R8A7790_CLK_HP),
DEF_MOD("usbhs-dmac1", 331, R8A7790_CLK_HP),
DEF_MOD("irqc", 407, R8A7790_CLK_CP),
DEF_MOD("intc-sys", 408, R8A7790_CLK_ZS),
DEF_MOD("audio-dmac1", 501, R8A7790_CLK_HP),
DEF_MOD("audio-dmac0", 502, R8A7790_CLK_HP),
DEF_MOD("adsp_mod", 506, R8A7790_CLK_ADSP),
DEF_MOD("thermal", 522, CLK_EXTAL),
DEF_MOD("pwm", 523, R8A7790_CLK_P),
DEF_MOD("usb-ehci", 703, R8A7790_CLK_MP),
DEF_MOD("usbhs", 704, R8A7790_CLK_HP),
DEF_MOD("hscif1", 716, R8A7790_CLK_ZS),
DEF_MOD("hscif0", 717, R8A7790_CLK_ZS),
DEF_MOD("scif1", 720, R8A7790_CLK_P),
DEF_MOD("scif0", 721, R8A7790_CLK_P),
DEF_MOD("du2", 722, R8A7790_CLK_ZX),
DEF_MOD("du1", 723, R8A7790_CLK_ZX),
DEF_MOD("du0", 724, R8A7790_CLK_ZX),
DEF_MOD("lvds1", 725, R8A7790_CLK_ZX),
DEF_MOD("lvds0", 726, R8A7790_CLK_ZX),
DEF_MOD("mlb", 802, R8A7790_CLK_HP),
DEF_MOD("vin3", 808, R8A7790_CLK_ZG),
DEF_MOD("vin2", 809, R8A7790_CLK_ZG),
DEF_MOD("vin1", 810, R8A7790_CLK_ZG),
DEF_MOD("vin0", 811, R8A7790_CLK_ZG),
DEF_MOD("etheravb", 812, R8A7790_CLK_HP),
DEF_MOD("ether", 813, R8A7790_CLK_P),
DEF_MOD("sata1", 814, R8A7790_CLK_ZS),
DEF_MOD("sata0", 815, R8A7790_CLK_ZS),
DEF_MOD("gyro-adc", 901, R8A7790_CLK_P),
DEF_MOD("gpio5", 907, R8A7790_CLK_CP),
DEF_MOD("gpio4", 908, R8A7790_CLK_CP),
DEF_MOD("gpio3", 909, R8A7790_CLK_CP),
DEF_MOD("gpio2", 910, R8A7790_CLK_CP),
DEF_MOD("gpio1", 911, R8A7790_CLK_CP),
DEF_MOD("gpio0", 912, R8A7790_CLK_CP),
DEF_MOD("can1", 915, R8A7790_CLK_P),
DEF_MOD("can0", 916, R8A7790_CLK_P),
DEF_MOD("qspi_mod", 917, R8A7790_CLK_QSPI),
DEF_MOD("iicdvfs", 926, R8A7790_CLK_CP),
DEF_MOD("i2c3", 928, R8A7790_CLK_HP),
DEF_MOD("i2c2", 929, R8A7790_CLK_HP),
DEF_MOD("i2c1", 930, R8A7790_CLK_HP),
DEF_MOD("i2c0", 931, R8A7790_CLK_HP),
DEF_MOD("ssi-all", 1005, R8A7790_CLK_P),
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
DEF_MOD("scu-all", 1017, R8A7790_CLK_P),
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
};
static const unsigned int r8a7790_crit_mod_clks[] __initconst = {
MOD_CLK_ID(408), /* INTC-SYS (GIC) */
};
/*
* CPG Clock Data
*/
/*
* MD EXTAL PLL0 PLL1 PLL3
* 14 13 19 (MHz) *1 *1
*---------------------------------------------------
* 0 0 0 15 x172/2 x208/2 x106
* 0 0 1 15 x172/2 x208/2 x88
* 0 1 0 20 x130/2 x156/2 x80
* 0 1 1 20 x130/2 x156/2 x66
* 1 0 0 26 / 2 x200/2 x240/2 x122
* 1 0 1 26 / 2 x200/2 x240/2 x102
* 1 1 0 30 / 2 x172/2 x208/2 x106
* 1 1 1 30 / 2 x172/2 x208/2 x88
*
* *1 : Table 7.5a indicates VCO output (PLLx = VCO/2)
*/
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
(((md) & BIT(13)) >> 12) | \
(((md) & BIT(19)) >> 19))
static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
{ 1, 208, 106 }, { 1, 208, 88 }, { 1, 156, 80 }, { 1, 156, 66 },
{ 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208, 88 },
};
static int __init r8a7790_cpg_mssr_init(struct device *dev)
{
const struct rcar_gen2_cpg_pll_config *cpg_pll_config;
u32 cpg_mode;
int error;
error = rcar_rst_read_mode_pins(&cpg_mode);
if (error)
return error;
cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
return rcar_gen2_cpg_init(cpg_pll_config, 2, cpg_mode);
}
const struct cpg_mssr_info r8a7790_cpg_mssr_info __initconst = {
/* Core Clocks */
.core_clks = r8a7790_core_clks,
.num_core_clks = ARRAY_SIZE(r8a7790_core_clks),
.last_dt_core_clk = LAST_DT_CORE_CLK,
.num_total_core_clks = MOD_CLK_BASE,
/* Module Clocks */
.mod_clks = r8a7790_mod_clks,
.num_mod_clks = ARRAY_SIZE(r8a7790_mod_clks),
.num_hw_mod_clks = 12 * 32,
/* Critical Module Clocks */
.crit_mod_clks = r8a7790_crit_mod_clks,
.num_crit_mod_clks = ARRAY_SIZE(r8a7790_crit_mod_clks),
/* Callbacks */
.init = r8a7790_cpg_mssr_init,
.cpg_clk_register = rcar_gen2_cpg_clk_register,
};

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drivers/clk/renesas/r8a7791-cpg-mssr.c Normal file
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/*
* r8a7791 Clock Pulse Generator / Module Standby and Software Reset
*
* Copyright (C) 2015-2017 Glider bvba
*
* Based on clk-rcar-gen2.c
*
* Copyright (C) 2013 Ideas On Board SPRL
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*/
#include <linux/device.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/soc/renesas/rcar-rst.h>
#include <dt-bindings/clock/r8a7791-cpg-mssr.h>
#include "renesas-cpg-mssr.h"
#include "rcar-gen2-cpg.h"
enum clk_ids {
/* Core Clock Outputs exported to DT */
LAST_DT_CORE_CLK = R8A7791_CLK_OSC,
/* External Input Clocks */
CLK_EXTAL,
CLK_USB_EXTAL,
/* Internal Core Clocks */
CLK_MAIN,
CLK_PLL0,
CLK_PLL1,
CLK_PLL3,
CLK_PLL1_DIV2,
/* Module Clocks */
MOD_CLK_BASE
};
static struct cpg_core_clk r8a7791_core_clks[] __initdata = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("usb_extal", CLK_USB_EXTAL),
/* Internal Core Clocks */
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
/* Core Clock Outputs */
DEF_BASE("z", R8A7791_CLK_Z, CLK_TYPE_GEN2_Z, CLK_PLL0),
DEF_BASE("lb", R8A7791_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1),
DEF_BASE("adsp", R8A7791_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),
DEF_BASE("sdh", R8A7791_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
DEF_BASE("sd0", R8A7791_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
DEF_BASE("qspi", R8A7791_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
DEF_BASE("rcan", R8A7791_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL),
DEF_FIXED("zg", R8A7791_CLK_ZG, CLK_PLL1, 3, 1),
DEF_FIXED("zx", R8A7791_CLK_ZX, CLK_PLL1, 3, 1),
DEF_FIXED("zs", R8A7791_CLK_ZS, CLK_PLL1, 6, 1),
DEF_FIXED("hp", R8A7791_CLK_HP, CLK_PLL1, 12, 1),
DEF_FIXED("i", R8A7791_CLK_I, CLK_PLL1, 2, 1),
DEF_FIXED("b", R8A7791_CLK_B, CLK_PLL1, 12, 1),
DEF_FIXED("p", R8A7791_CLK_P, CLK_PLL1, 24, 1),
DEF_FIXED("cl", R8A7791_CLK_CL, CLK_PLL1, 48, 1),
DEF_FIXED("m2", R8A7791_CLK_M2, CLK_PLL1, 8, 1),
DEF_FIXED("zb3", R8A7791_CLK_ZB3, CLK_PLL3, 4, 1),
DEF_FIXED("zb3d2", R8A7791_CLK_ZB3D2, CLK_PLL3, 8, 1),
DEF_FIXED("ddr", R8A7791_CLK_DDR, CLK_PLL3, 8, 1),
DEF_FIXED("mp", R8A7791_CLK_MP, CLK_PLL1_DIV2, 15, 1),
DEF_FIXED("cp", R8A7791_CLK_CP, CLK_EXTAL, 2, 1),
DEF_FIXED("r", R8A7791_CLK_R, CLK_PLL1, 49152, 1),
DEF_FIXED("osc", R8A7791_CLK_OSC, CLK_PLL1, 12288, 1),
DEF_DIV6P1("sd2", R8A7791_CLK_SD2, CLK_PLL1_DIV2, 0x078),
DEF_DIV6P1("sd3", R8A7791_CLK_SD3, CLK_PLL1_DIV2, 0x26c),
DEF_DIV6P1("mmc0", R8A7791_CLK_MMC0, CLK_PLL1_DIV2, 0x240),
DEF_DIV6P1("ssp", R8A7791_CLK_SSP, CLK_PLL1_DIV2, 0x248),
DEF_DIV6P1("ssprs", R8A7791_CLK_SSPRS, CLK_PLL1_DIV2, 0x24c),
};
static const struct mssr_mod_clk r8a7791_mod_clks[] __initconst = {
DEF_MOD("msiof0", 0, R8A7791_CLK_MP),
DEF_MOD("vcp0", 101, R8A7791_CLK_ZS),
DEF_MOD("vpc0", 103, R8A7791_CLK_ZS),
DEF_MOD("jpu", 106, R8A7791_CLK_M2),
DEF_MOD("ssp1", 109, R8A7791_CLK_ZS),
DEF_MOD("tmu1", 111, R8A7791_CLK_P),
DEF_MOD("3dg", 112, R8A7791_CLK_ZG),
DEF_MOD("2d-dmac", 115, R8A7791_CLK_ZS),
DEF_MOD("fdp1-1", 118, R8A7791_CLK_ZS),
DEF_MOD("fdp1-0", 119, R8A7791_CLK_ZS),
DEF_MOD("tmu3", 121, R8A7791_CLK_P),
DEF_MOD("tmu2", 122, R8A7791_CLK_P),
DEF_MOD("cmt0", 124, R8A7791_CLK_R),
DEF_MOD("tmu0", 125, R8A7791_CLK_CP),
DEF_MOD("vsp1du1", 127, R8A7791_CLK_ZS),
DEF_MOD("vsp1du0", 128, R8A7791_CLK_ZS),
DEF_MOD("vsp1-sy", 131, R8A7791_CLK_ZS),
DEF_MOD("scifa2", 202, R8A7791_CLK_MP),
DEF_MOD("scifa1", 203, R8A7791_CLK_MP),
DEF_MOD("scifa0", 204, R8A7791_CLK_MP),
DEF_MOD("msiof2", 205, R8A7791_CLK_MP),
DEF_MOD("scifb0", 206, R8A7791_CLK_MP),
DEF_MOD("scifb1", 207, R8A7791_CLK_MP),
DEF_MOD("msiof1", 208, R8A7791_CLK_MP),
DEF_MOD("scifb2", 216, R8A7791_CLK_MP),
DEF_MOD("sys-dmac1", 218, R8A7791_CLK_ZS),
DEF_MOD("sys-dmac0", 219, R8A7791_CLK_ZS),
DEF_MOD("tpu0", 304, R8A7791_CLK_CP),
DEF_MOD("sdhi3", 311, R8A7791_CLK_SD3),
DEF_MOD("sdhi2", 312, R8A7791_CLK_SD2),
DEF_MOD("sdhi0", 314, R8A7791_CLK_SD0),
DEF_MOD("mmcif0", 315, R8A7791_CLK_MMC0),
DEF_MOD("iic0", 318, R8A7791_CLK_HP),
DEF_MOD("pciec", 319, R8A7791_CLK_MP),
DEF_MOD("iic1", 323, R8A7791_CLK_HP),
DEF_MOD("usb3.0", 328, R8A7791_CLK_MP),
DEF_MOD("cmt1", 329, R8A7791_CLK_R),
DEF_MOD("usbhs-dmac0", 330, R8A7791_CLK_HP),
DEF_MOD("usbhs-dmac1", 331, R8A7791_CLK_HP),
DEF_MOD("irqc", 407, R8A7791_CLK_CP),
DEF_MOD("intc-sys", 408, R8A7791_CLK_ZS),
DEF_MOD("audio-dmac1", 501, R8A7791_CLK_HP),
DEF_MOD("audio-dmac0", 502, R8A7791_CLK_HP),
DEF_MOD("adsp_mod", 506, R8A7791_CLK_ADSP),
DEF_MOD("thermal", 522, CLK_EXTAL),
DEF_MOD("pwm", 523, R8A7791_CLK_P),
DEF_MOD("usb-ehci", 703, R8A7791_CLK_MP),
DEF_MOD("usbhs", 704, R8A7791_CLK_HP),
DEF_MOD("hscif2", 713, R8A7791_CLK_ZS),
DEF_MOD("scif5", 714, R8A7791_CLK_P),
DEF_MOD("scif4", 715, R8A7791_CLK_P),
DEF_MOD("hscif1", 716, R8A7791_CLK_ZS),
DEF_MOD("hscif0", 717, R8A7791_CLK_ZS),
DEF_MOD("scif3", 718, R8A7791_CLK_P),
DEF_MOD("scif2", 719, R8A7791_CLK_P),
DEF_MOD("scif1", 720, R8A7791_CLK_P),
DEF_MOD("scif0", 721, R8A7791_CLK_P),
DEF_MOD("du1", 723, R8A7791_CLK_ZX),
DEF_MOD("du0", 724, R8A7791_CLK_ZX),
DEF_MOD("lvds0", 726, R8A7791_CLK_ZX),
DEF_MOD("ipmmu-sgx", 800, R8A7791_CLK_ZX),
DEF_MOD("mlb", 802, R8A7791_CLK_HP),
DEF_MOD("vin2", 809, R8A7791_CLK_ZG),
DEF_MOD("vin1", 810, R8A7791_CLK_ZG),
DEF_MOD("vin0", 811, R8A7791_CLK_ZG),
DEF_MOD("etheravb", 812, R8A7791_CLK_HP),
DEF_MOD("ether", 813, R8A7791_CLK_P),
DEF_MOD("sata1", 814, R8A7791_CLK_ZS),
DEF_MOD("sata0", 815, R8A7791_CLK_ZS),
DEF_MOD("gyro-adc", 901, R8A7791_CLK_P),
DEF_MOD("gpio7", 904, R8A7791_CLK_CP),
DEF_MOD("gpio6", 905, R8A7791_CLK_CP),
DEF_MOD("gpio5", 907, R8A7791_CLK_CP),
DEF_MOD("gpio4", 908, R8A7791_CLK_CP),
DEF_MOD("gpio3", 909, R8A7791_CLK_CP),
DEF_MOD("gpio2", 910, R8A7791_CLK_CP),
DEF_MOD("gpio1", 911, R8A7791_CLK_CP),
DEF_MOD("gpio0", 912, R8A7791_CLK_CP),
DEF_MOD("can1", 915, R8A7791_CLK_P),
DEF_MOD("can0", 916, R8A7791_CLK_P),
DEF_MOD("qspi_mod", 917, R8A7791_CLK_QSPI),
DEF_MOD("i2c5", 925, R8A7791_CLK_HP),
DEF_MOD("iicdvfs", 926, R8A7791_CLK_CP),
DEF_MOD("i2c4", 927, R8A7791_CLK_HP),
DEF_MOD("i2c3", 928, R8A7791_CLK_HP),
DEF_MOD("i2c2", 929, R8A7791_CLK_HP),
DEF_MOD("i2c1", 930, R8A7791_CLK_HP),
DEF_MOD("i2c0", 931, R8A7791_CLK_HP),
DEF_MOD("ssi-all", 1005, R8A7791_CLK_P),
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
DEF_MOD("scu-all", 1017, R8A7791_CLK_P),
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
DEF_MOD("scifa3", 1106, R8A7791_CLK_MP),
DEF_MOD("scifa4", 1107, R8A7791_CLK_MP),
DEF_MOD("scifa5", 1108, R8A7791_CLK_MP),
};
static const unsigned int r8a7791_crit_mod_clks[] __initconst = {
MOD_CLK_ID(408), /* INTC-SYS (GIC) */
};
/*
* CPG Clock Data
*/
/*
* MD EXTAL PLL0 PLL1 PLL3
* 14 13 19 (MHz) *1 *1
*---------------------------------------------------
* 0 0 0 15 x172/2 x208/2 x106
* 0 0 1 15 x172/2 x208/2 x88
* 0 1 0 20 x130/2 x156/2 x80
* 0 1 1 20 x130/2 x156/2 x66
* 1 0 0 26 / 2 x200/2 x240/2 x122
* 1 0 1 26 / 2 x200/2 x240/2 x102
* 1 1 0 30 / 2 x172/2 x208/2 x106
* 1 1 1 30 / 2 x172/2 x208/2 x88
*
* *1 : Table 7.5a indicates VCO output (PLLx = VCO/2)
*/
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
(((md) & BIT(13)) >> 12) | \
(((md) & BIT(19)) >> 19))
static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
{ 1, 208, 106 }, { 1, 208, 88 }, { 1, 156, 80 }, { 1, 156, 66 },
{ 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208, 88 },
};
static int __init r8a7791_cpg_mssr_init(struct device *dev)
{
const struct rcar_gen2_cpg_pll_config *cpg_pll_config;
struct device_node *np = dev->of_node;
unsigned int i;
u32 cpg_mode;
int error;
error = rcar_rst_read_mode_pins(&cpg_mode);
if (error)
return error;
cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
if (of_device_is_compatible(np, "renesas,r8a7793-cpg-mssr")) {
/* R-Car M2-N uses a 1/5 divider for ZG */
for (i = 0; i < ARRAY_SIZE(r8a7791_core_clks); i++)
if (r8a7791_core_clks[i].id == R8A7791_CLK_ZG) {
r8a7791_core_clks[i].div = 5;
break;
}
}
return rcar_gen2_cpg_init(cpg_pll_config, 2, cpg_mode);
}
const struct cpg_mssr_info r8a7791_cpg_mssr_info __initconst = {
/* Core Clocks */
.core_clks = r8a7791_core_clks,
.num_core_clks = ARRAY_SIZE(r8a7791_core_clks),
.last_dt_core_clk = LAST_DT_CORE_CLK,
.num_total_core_clks = MOD_CLK_BASE,
/* Module Clocks */
.mod_clks = r8a7791_mod_clks,
.num_mod_clks = ARRAY_SIZE(r8a7791_mod_clks),
.num_hw_mod_clks = 12 * 32,
/* Critical Module Clocks */
.crit_mod_clks = r8a7791_crit_mod_clks,
.num_crit_mod_clks = ARRAY_SIZE(r8a7791_crit_mod_clks),
/* Callbacks */
.init = r8a7791_cpg_mssr_init,
.cpg_clk_register = rcar_gen2_cpg_clk_register,
};

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drivers/clk/renesas/r8a7792-cpg-mssr.c Normal file
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/*
* r8a7792 Clock Pulse Generator / Module Standby and Software Reset
*
* Copyright (C) 2017 Glider bvba
*
* Based on clk-rcar-gen2.c
*
* Copyright (C) 2013 Ideas On Board SPRL
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*/
#include <linux/device.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/soc/renesas/rcar-rst.h>
#include <dt-bindings/clock/r8a7792-cpg-mssr.h>
#include "renesas-cpg-mssr.h"
#include "rcar-gen2-cpg.h"
enum clk_ids {
/* Core Clock Outputs exported to DT */
LAST_DT_CORE_CLK = R8A7792_CLK_OSC,
/* External Input Clocks */
CLK_EXTAL,
/* Internal Core Clocks */
CLK_MAIN,
CLK_PLL0,
CLK_PLL1,
CLK_PLL3,
CLK_PLL1_DIV2,
/* Module Clocks */
MOD_CLK_BASE
};
static const struct cpg_core_clk r8a7792_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
/* Internal Core Clocks */
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
/* Core Clock Outputs */
DEF_BASE("lb", R8A7792_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1),
DEF_BASE("qspi", R8A7792_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
DEF_FIXED("z", R8A7792_CLK_Z, CLK_PLL0, 1, 1),
DEF_FIXED("zg", R8A7792_CLK_ZG, CLK_PLL1, 5, 1),
DEF_FIXED("zx", R8A7792_CLK_ZX, CLK_PLL1, 3, 1),
DEF_FIXED("zs", R8A7792_CLK_ZS, CLK_PLL1, 6, 1),
DEF_FIXED("hp", R8A7792_CLK_HP, CLK_PLL1, 12, 1),
DEF_FIXED("i", R8A7792_CLK_I, CLK_PLL1, 3, 1),
DEF_FIXED("b", R8A7792_CLK_B, CLK_PLL1, 12, 1),
DEF_FIXED("p", R8A7792_CLK_P, CLK_PLL1, 24, 1),
DEF_FIXED("cl", R8A7792_CLK_CL, CLK_PLL1, 48, 1),
DEF_FIXED("m2", R8A7792_CLK_M2, CLK_PLL1, 8, 1),
DEF_FIXED("imp", R8A7792_CLK_IMP, CLK_PLL1, 4, 1),
DEF_FIXED("zb3", R8A7792_CLK_ZB3, CLK_PLL3, 4, 1),
DEF_FIXED("zb3d2", R8A7792_CLK_ZB3D2, CLK_PLL3, 8, 1),
DEF_FIXED("ddr", R8A7792_CLK_DDR, CLK_PLL3, 8, 1),
DEF_FIXED("sd", R8A7792_CLK_SD, CLK_PLL1_DIV2, 8, 1),
DEF_FIXED("mp", R8A7792_CLK_MP, CLK_PLL1_DIV2, 15, 1),
DEF_FIXED("cp", R8A7792_CLK_CP, CLK_PLL1, 48, 1),
DEF_FIXED("cpex", R8A7792_CLK_CPEX, CLK_EXTAL, 2, 1),
DEF_FIXED("rcan", R8A7792_CLK_RCAN, CLK_PLL1_DIV2, 49, 1),
DEF_FIXED("r", R8A7792_CLK_R, CLK_PLL1, 49152, 1),
DEF_FIXED("osc", R8A7792_CLK_OSC, CLK_PLL1, 12288, 1),
};
static const struct mssr_mod_clk r8a7792_mod_clks[] __initconst = {
DEF_MOD("msiof0", 0, R8A7792_CLK_MP),
DEF_MOD("jpu", 106, R8A7792_CLK_M2),
DEF_MOD("tmu1", 111, R8A7792_CLK_P),
DEF_MOD("3dg", 112, R8A7792_CLK_ZG),
DEF_MOD("2d-dmac", 115, R8A7792_CLK_ZS),
DEF_MOD("tmu3", 121, R8A7792_CLK_P),
DEF_MOD("tmu2", 122, R8A7792_CLK_P),
DEF_MOD("cmt0", 124, R8A7792_CLK_R),
DEF_MOD("tmu0", 125, R8A7792_CLK_CP),
DEF_MOD("vsp1du1", 127, R8A7792_CLK_ZS),
DEF_MOD("vsp1du0", 128, R8A7792_CLK_ZS),
DEF_MOD("vsp1-sy", 131, R8A7792_CLK_ZS),
DEF_MOD("msiof1", 208, R8A7792_CLK_MP),
DEF_MOD("sys-dmac1", 218, R8A7792_CLK_ZS),
DEF_MOD("sys-dmac0", 219, R8A7792_CLK_ZS),
DEF_MOD("tpu0", 304, R8A7792_CLK_CP),
DEF_MOD("sdhi0", 314, R8A7792_CLK_SD),
DEF_MOD("cmt1", 329, R8A7792_CLK_R),
DEF_MOD("irqc", 407, R8A7792_CLK_CP),
DEF_MOD("intc-sys", 408, R8A7792_CLK_ZS),
DEF_MOD("audio-dmac0", 502, R8A7792_CLK_HP),
DEF_MOD("thermal", 522, CLK_EXTAL),
DEF_MOD("pwm", 523, R8A7792_CLK_P),
DEF_MOD("hscif1", 716, R8A7792_CLK_ZS),
DEF_MOD("hscif0", 717, R8A7792_CLK_ZS),
DEF_MOD("scif3", 718, R8A7792_CLK_P),
DEF_MOD("scif2", 719, R8A7792_CLK_P),
DEF_MOD("scif1", 720, R8A7792_CLK_P),
DEF_MOD("scif0", 721, R8A7792_CLK_P),
DEF_MOD("du1", 723, R8A7792_CLK_ZX),
DEF_MOD("du0", 724, R8A7792_CLK_ZX),
DEF_MOD("vin5", 804, R8A7792_CLK_ZG),
DEF_MOD("vin4", 805, R8A7792_CLK_ZG),
DEF_MOD("vin3", 808, R8A7792_CLK_ZG),
DEF_MOD("vin2", 809, R8A7792_CLK_ZG),
DEF_MOD("vin1", 810, R8A7792_CLK_ZG),
DEF_MOD("vin0", 811, R8A7792_CLK_ZG),
DEF_MOD("etheravb", 812, R8A7792_CLK_HP),
DEF_MOD("gyro-adc", 901, R8A7792_CLK_P),
DEF_MOD("gpio7", 904, R8A7792_CLK_CP),
DEF_MOD("gpio6", 905, R8A7792_CLK_CP),
DEF_MOD("gpio5", 907, R8A7792_CLK_CP),
DEF_MOD("gpio4", 908, R8A7792_CLK_CP),
DEF_MOD("gpio3", 909, R8A7792_CLK_CP),
DEF_MOD("gpio2", 910, R8A7792_CLK_CP),
DEF_MOD("gpio1", 911, R8A7792_CLK_CP),
DEF_MOD("gpio0", 912, R8A7792_CLK_CP),
DEF_MOD("gpio11", 913, R8A7792_CLK_CP),
DEF_MOD("gpio10", 914, R8A7792_CLK_CP),
DEF_MOD("can1", 915, R8A7792_CLK_P),
DEF_MOD("can0", 916, R8A7792_CLK_P),
DEF_MOD("qspi_mod", 917, R8A7792_CLK_QSPI),
DEF_MOD("gpio9", 919, R8A7792_CLK_CP),
DEF_MOD("gpio8", 921, R8A7792_CLK_CP),
DEF_MOD("i2c5", 925, R8A7792_CLK_HP),
DEF_MOD("iicdvfs", 926, R8A7792_CLK_CP),
DEF_MOD("i2c4", 927, R8A7792_CLK_HP),
DEF_MOD("i2c3", 928, R8A7792_CLK_HP),
DEF_MOD("i2c2", 929, R8A7792_CLK_HP),
DEF_MOD("i2c1", 930, R8A7792_CLK_HP),
DEF_MOD("i2c0", 931, R8A7792_CLK_HP),
DEF_MOD("ssi-all", 1005, R8A7792_CLK_P),
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
};
static const unsigned int r8a7792_crit_mod_clks[] __initconst = {
MOD_CLK_ID(408), /* INTC-SYS (GIC) */
};
/*
* CPG Clock Data
*/
/*
* MD EXTAL PLL0 PLL1 PLL3
* 14 13 19 (MHz) *1 *2
*---------------------------------------------------
* 0 0 0 15 x200/3 x208/2 x106
* 0 0 1 15 x200/3 x208/2 x88
* 0 1 0 20 x150/3 x156/2 x80
* 0 1 1 20 x150/3 x156/2 x66
* 1 0 0 26 / 2 x230/3 x240/2 x122
* 1 0 1 26 / 2 x230/3 x240/2 x102
* 1 1 0 30 / 2 x200/3 x208/2 x106
* 1 1 1 30 / 2 x200/3 x208/2 x88
*
* *1 : Table 7.5b indicates VCO output (PLL0 = VCO/3)
* *2 : Table 7.5b indicates VCO output (PLL1 = VCO/2)
*/
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
(((md) & BIT(13)) >> 12) | \
(((md) & BIT(19)) >> 19))
static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
{ 1, 208, 106, 200 },
{ 1, 208, 88, 200 },
{ 1, 156, 80, 150 },
{ 1, 156, 66, 150 },
{ 2, 240, 122, 230 },
{ 2, 240, 102, 230 },
{ 2, 208, 106, 200 },
{ 2, 208, 88, 200 },
};
static int __init r8a7792_cpg_mssr_init(struct device *dev)
{
const struct rcar_gen2_cpg_pll_config *cpg_pll_config;
u32 cpg_mode;
int error;
error = rcar_rst_read_mode_pins(&cpg_mode);
if (error)
return error;
cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
return rcar_gen2_cpg_init(cpg_pll_config, 3, cpg_mode);
}
const struct cpg_mssr_info r8a7792_cpg_mssr_info __initconst = {
/* Core Clocks */
.core_clks = r8a7792_core_clks,
.num_core_clks = ARRAY_SIZE(r8a7792_core_clks),
.last_dt_core_clk = LAST_DT_CORE_CLK,
.num_total_core_clks = MOD_CLK_BASE,
/* Module Clocks */
.mod_clks = r8a7792_mod_clks,
.num_mod_clks = ARRAY_SIZE(r8a7792_mod_clks),
.num_hw_mod_clks = 12 * 32,
/* Critical Module Clocks */
.crit_mod_clks = r8a7792_crit_mod_clks,
.num_crit_mod_clks = ARRAY_SIZE(r8a7792_crit_mod_clks),
/* Callbacks */
.init = r8a7792_cpg_mssr_init,
.cpg_clk_register = rcar_gen2_cpg_clk_register,
};

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drivers/clk/renesas/r8a7794-cpg-mssr.c Normal file
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/*
* r8a7794 Clock Pulse Generator / Module Standby and Software Reset
*
* Copyright (C) 2017 Glider bvba
*
* Based on clk-rcar-gen2.c
*
* Copyright (C) 2013 Ideas On Board SPRL
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*/
#include <linux/device.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/soc/renesas/rcar-rst.h>
#include <dt-bindings/clock/r8a7794-cpg-mssr.h>
#include "renesas-cpg-mssr.h"
#include "rcar-gen2-cpg.h"
enum clk_ids {
/* Core Clock Outputs exported to DT */
LAST_DT_CORE_CLK = R8A7794_CLK_OSC,
/* External Input Clocks */
CLK_EXTAL,
CLK_USB_EXTAL,
/* Internal Core Clocks */
CLK_MAIN,
CLK_PLL0,
CLK_PLL1,
CLK_PLL3,
CLK_PLL1_DIV2,
/* Module Clocks */
MOD_CLK_BASE
};
static const struct cpg_core_clk r8a7794_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("usb_extal", CLK_USB_EXTAL),
/* Internal Core Clocks */
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
/* Core Clock Outputs */
DEF_BASE("lb", R8A7794_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1),
DEF_BASE("adsp", R8A7794_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),
DEF_BASE("sdh", R8A7794_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
DEF_BASE("sd0", R8A7794_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
DEF_BASE("qspi", R8A7794_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
DEF_BASE("rcan", R8A7794_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL),
DEF_FIXED("z2", R8A7794_CLK_Z2, CLK_PLL0, 1, 1),
DEF_FIXED("zg", R8A7794_CLK_ZG, CLK_PLL1, 6, 1),
DEF_FIXED("zx", R8A7794_CLK_ZX, CLK_PLL1, 3, 1),
DEF_FIXED("zs", R8A7794_CLK_ZS, CLK_PLL1, 6, 1),
DEF_FIXED("hp", R8A7794_CLK_HP, CLK_PLL1, 12, 1),
DEF_FIXED("i", R8A7794_CLK_I, CLK_PLL1, 2, 1),
DEF_FIXED("b", R8A7794_CLK_B, CLK_PLL1, 12, 1),
DEF_FIXED("p", R8A7794_CLK_P, CLK_PLL1, 24, 1),
DEF_FIXED("cl", R8A7794_CLK_CL, CLK_PLL1, 48, 1),
DEF_FIXED("cp", R8A7794_CLK_CP, CLK_PLL1, 48, 1),
DEF_FIXED("m2", R8A7794_CLK_M2, CLK_PLL1, 8, 1),
DEF_FIXED("zb3", R8A7794_CLK_ZB3, CLK_PLL3, 4, 1),
DEF_FIXED("zb3d2", R8A7794_CLK_ZB3D2, CLK_PLL3, 8, 1),
DEF_FIXED("ddr", R8A7794_CLK_DDR, CLK_PLL3, 8, 1),
DEF_FIXED("mp", R8A7794_CLK_MP, CLK_PLL1_DIV2, 15, 1),
DEF_FIXED("cpex", R8A7794_CLK_CPEX, CLK_EXTAL, 2, 1),
DEF_FIXED("r", R8A7794_CLK_R, CLK_PLL1, 49152, 1),
DEF_FIXED("osc", R8A7794_CLK_OSC, CLK_PLL1, 12288, 1),
DEF_DIV6P1("sd2", R8A7794_CLK_SD2, CLK_PLL1_DIV2, 0x078),
DEF_DIV6P1("sd3", R8A7794_CLK_SD3, CLK_PLL1_DIV2, 0x26c),
DEF_DIV6P1("mmc0", R8A7794_CLK_MMC0, CLK_PLL1_DIV2, 0x240),
};
static const struct mssr_mod_clk r8a7794_mod_clks[] __initconst = {
DEF_MOD("msiof0", 0, R8A7794_CLK_MP),
DEF_MOD("vcp0", 101, R8A7794_CLK_ZS),
DEF_MOD("vpc0", 103, R8A7794_CLK_ZS),
DEF_MOD("jpu", 106, R8A7794_CLK_M2),
DEF_MOD("tmu1", 111, R8A7794_CLK_P),
DEF_MOD("3dg", 112, R8A7794_CLK_ZG),
DEF_MOD("2d-dmac", 115, R8A7794_CLK_ZS),
DEF_MOD("fdp1-0", 119, R8A7794_CLK_ZS),
DEF_MOD("tmu3", 121, R8A7794_CLK_P),
DEF_MOD("tmu2", 122, R8A7794_CLK_P),
DEF_MOD("cmt0", 124, R8A7794_CLK_R),
DEF_MOD("tmu0", 125, R8A7794_CLK_CP),
DEF_MOD("vsp1du0", 128, R8A7794_CLK_ZS),
DEF_MOD("vsp1-sy", 131, R8A7794_CLK_ZS),
DEF_MOD("scifa2", 202, R8A7794_CLK_MP),
DEF_MOD("scifa1", 203, R8A7794_CLK_MP),
DEF_MOD("scifa0", 204, R8A7794_CLK_MP),
DEF_MOD("msiof2", 205, R8A7794_CLK_MP),
DEF_MOD("scifb0", 206, R8A7794_CLK_MP),
DEF_MOD("scifb1", 207, R8A7794_CLK_MP),
DEF_MOD("msiof1", 208, R8A7794_CLK_MP),
DEF_MOD("scifb2", 216, R8A7794_CLK_MP),
DEF_MOD("sys-dmac1", 218, R8A7794_CLK_ZS),
DEF_MOD("sys-dmac0", 219, R8A7794_CLK_ZS),
DEF_MOD("tpu0", 304, R8A7794_CLK_CP),
DEF_MOD("sdhi3", 311, R8A7794_CLK_SD3),
DEF_MOD("sdhi2", 312, R8A7794_CLK_SD2),
DEF_MOD("sdhi0", 314, R8A7794_CLK_SD0),
DEF_MOD("mmcif0", 315, R8A7794_CLK_MMC0),
DEF_MOD("iic0", 318, R8A7794_CLK_HP),
DEF_MOD("iic1", 323, R8A7794_CLK_HP),
DEF_MOD("cmt1", 329, R8A7794_CLK_R),
DEF_MOD("usbhs-dmac0", 330, R8A7794_CLK_HP),
DEF_MOD("usbhs-dmac1", 331, R8A7794_CLK_HP),
DEF_MOD("irqc", 407, R8A7794_CLK_CP),
DEF_MOD("intc-sys", 408, R8A7794_CLK_ZS),
DEF_MOD("audio-dmac0", 502, R8A7794_CLK_HP),
DEF_MOD("adsp_mod", 506, R8A7794_CLK_ADSP),
DEF_MOD("pwm", 523, R8A7794_CLK_P),
DEF_MOD("usb-ehci", 703, R8A7794_CLK_MP),
DEF_MOD("usbhs", 704, R8A7794_CLK_HP),
DEF_MOD("hscif2", 713, R8A7794_CLK_ZS),
DEF_MOD("scif5", 714, R8A7794_CLK_P),
DEF_MOD("scif4", 715, R8A7794_CLK_P),
DEF_MOD("hscif1", 716, R8A7794_CLK_ZS),
DEF_MOD("hscif0", 717, R8A7794_CLK_ZS),
DEF_MOD("scif3", 718, R8A7794_CLK_P),
DEF_MOD("scif2", 719, R8A7794_CLK_P),
DEF_MOD("scif1", 720, R8A7794_CLK_P),
DEF_MOD("scif0", 721, R8A7794_CLK_P),
DEF_MOD("du1", 723, R8A7794_CLK_ZX),
DEF_MOD("du0", 724, R8A7794_CLK_ZX),
DEF_MOD("ipmmu-sgx", 800, R8A7794_CLK_ZX),
DEF_MOD("mlb", 802, R8A7794_CLK_HP),
DEF_MOD("vin1", 810, R8A7794_CLK_ZG),
DEF_MOD("vin0", 811, R8A7794_CLK_ZG),
DEF_MOD("etheravb", 812, R8A7794_CLK_HP),
DEF_MOD("ether", 813, R8A7794_CLK_P),
DEF_MOD("gyro-adc", 901, R8A7794_CLK_P),
DEF_MOD("gpio6", 905, R8A7794_CLK_CP),
DEF_MOD("gpio5", 907, R8A7794_CLK_CP),
DEF_MOD("gpio4", 908, R8A7794_CLK_CP),
DEF_MOD("gpio3", 909, R8A7794_CLK_CP),
DEF_MOD("gpio2", 910, R8A7794_CLK_CP),
DEF_MOD("gpio1", 911, R8A7794_CLK_CP),
DEF_MOD("gpio0", 912, R8A7794_CLK_CP),
DEF_MOD("can1", 915, R8A7794_CLK_P),
DEF_MOD("can0", 916, R8A7794_CLK_P),
DEF_MOD("qspi_mod", 917, R8A7794_CLK_QSPI),
DEF_MOD("i2c5", 925, R8A7794_CLK_HP),
DEF_MOD("i2c4", 927, R8A7794_CLK_HP),
DEF_MOD("i2c3", 928, R8A7794_CLK_HP),
DEF_MOD("i2c2", 929, R8A7794_CLK_HP),
DEF_MOD("i2c1", 930, R8A7794_CLK_HP),
DEF_MOD("i2c0", 931, R8A7794_CLK_HP),
DEF_MOD("ssi-all", 1005, R8A7794_CLK_P),
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
DEF_MOD("scu-all", 1017, R8A7794_CLK_P),
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
DEF_MOD("scifa3", 1106, R8A7794_CLK_MP),
DEF_MOD("scifa4", 1107, R8A7794_CLK_MP),
DEF_MOD("scifa5", 1108, R8A7794_CLK_MP),
};
static const unsigned int r8a7794_crit_mod_clks[] __initconst = {
MOD_CLK_ID(408), /* INTC-SYS (GIC) */
};
/*
* CPG Clock Data
*/
/*
* MD EXTAL PLL0 PLL1 PLL3
* 14 13 19 (MHz) *1 *2
*---------------------------------------------------
* 0 0 1 15 x200/3 x208/2 x88
* 0 1 1 20 x150/3 x156/2 x66
* 1 0 1 26 / 2 x230/3 x240/2 x102
* 1 1 1 30 / 2 x200/3 x208/2 x88
*
* *1 : Table 7.5c indicates VCO output (PLL0 = VCO/3)
* *2 : Table 7.5c indicates VCO output (PLL1 = VCO/2)
*/
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
(((md) & BIT(13)) >> 13))
static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[4] __initconst = {
{ 1, 208, 88, 200 },
{ 1, 156, 66, 150 },
{ 2, 240, 102, 230 },
{ 2, 208, 88, 200 },
};
static int __init r8a7794_cpg_mssr_init(struct device *dev)
{
const struct rcar_gen2_cpg_pll_config *cpg_pll_config;
u32 cpg_mode;
int error;
error = rcar_rst_read_mode_pins(&cpg_mode);
if (error)
return error;
cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
return rcar_gen2_cpg_init(cpg_pll_config, 3, cpg_mode);
}
const struct cpg_mssr_info r8a7794_cpg_mssr_info __initconst = {
/* Core Clocks */
.core_clks = r8a7794_core_clks,
.num_core_clks = ARRAY_SIZE(r8a7794_core_clks),
.last_dt_core_clk = LAST_DT_CORE_CLK,
.num_total_core_clks = MOD_CLK_BASE,
/* Module Clocks */
.mod_clks = r8a7794_mod_clks,
.num_mod_clks = ARRAY_SIZE(r8a7794_mod_clks),
.num_hw_mod_clks = 12 * 32,
/* Critical Module Clocks */
.crit_mod_clks = r8a7794_crit_mod_clks,
.num_crit_mod_clks = ARRAY_SIZE(r8a7794_crit_mod_clks),
/* Callbacks */
.init = r8a7794_cpg_mssr_init,
.cpg_clk_register = rcar_gen2_cpg_clk_register,
};

43
drivers/clk/renesas/r8a7795-cpg-mssr.c
View File

@ -141,8 +141,10 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
DEF_MOD("sdif0", 314, R8A7795_CLK_SD0),
DEF_MOD("pcie1", 318, R8A7795_CLK_S3D1),
DEF_MOD("pcie0", 319, R8A7795_CLK_S3D1),
DEF_MOD("usb-dmac30", 326, R8A7795_CLK_S3D1),
DEF_MOD("usb3-if1", 327, R8A7795_CLK_S3D1), /* ES1.x */
DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1),
DEF_MOD("usb-dmac31", 329, R8A7795_CLK_S3D1),
DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D1),
DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D1),
DEF_MOD("rwdt", 402, R8A7795_CLK_R),
@ -164,7 +166,7 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1),
DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1),
DEF_MOD("thermal", 522, R8A7795_CLK_CP),
DEF_MOD("pwm", 523, R8A7795_CLK_S3D4),
DEF_MOD("pwm", 523, R8A7795_CLK_S0D12),
DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1), /* ES1.x */
DEF_MOD("fcpvd2", 601, R8A7795_CLK_S0D2),
DEF_MOD("fcpvd1", 602, R8A7795_CLK_S0D2),
@ -189,10 +191,12 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1), /* ES1.x */
DEF_MOD("vspi1", 630, R8A7795_CLK_S0D1),
DEF_MOD("vspi0", 631, R8A7795_CLK_S0D1),
DEF_MOD("ehci3", 700, R8A7795_CLK_S3D4),
DEF_MOD("ehci2", 701, R8A7795_CLK_S3D4),
DEF_MOD("ehci1", 702, R8A7795_CLK_S3D4),
DEF_MOD("ehci0", 703, R8A7795_CLK_S3D4),
DEF_MOD("hsusb", 704, R8A7795_CLK_S3D4),
DEF_MOD("hsusb3", 705, R8A7795_CLK_S3D4),
DEF_MOD("csi21", 713, R8A7795_CLK_CSI0), /* ES1.x */
DEF_MOD("csi20", 714, R8A7795_CLK_CSI0),
DEF_MOD("csi41", 715, R8A7795_CLK_CSI0),
@ -218,22 +222,22 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
DEF_MOD("imr2", 821, R8A7795_CLK_S0D2),
DEF_MOD("imr1", 822, R8A7795_CLK_S0D2),
DEF_MOD("imr0", 823, R8A7795_CLK_S0D2),
DEF_MOD("gpio7", 905, R8A7795_CLK_CP),
DEF_MOD("gpio6", 906, R8A7795_CLK_CP),
DEF_MOD("gpio5", 907, R8A7795_CLK_CP),
DEF_MOD("gpio4", 908, R8A7795_CLK_CP),
DEF_MOD("gpio3", 909, R8A7795_CLK_CP),
DEF_MOD("gpio2", 910, R8A7795_CLK_CP),
DEF_MOD("gpio1", 911, R8A7795_CLK_CP),
DEF_MOD("gpio0", 912, R8A7795_CLK_CP),
DEF_MOD("gpio7", 905, R8A7795_CLK_S3D4),
DEF_MOD("gpio6", 906, R8A7795_CLK_S3D4),
DEF_MOD("gpio5", 907, R8A7795_CLK_S3D4),
DEF_MOD("gpio4", 908, R8A7795_CLK_S3D4),
DEF_MOD("gpio3", 909, R8A7795_CLK_S3D4),
DEF_MOD("gpio2", 910, R8A7795_CLK_S3D4),
DEF_MOD("gpio1", 911, R8A7795_CLK_S3D4),
DEF_MOD("gpio0", 912, R8A7795_CLK_S3D4),
DEF_MOD("can-fd", 914, R8A7795_CLK_S3D2),
DEF_MOD("can-if1", 915, R8A7795_CLK_S3D4),
DEF_MOD("can-if0", 916, R8A7795_CLK_S3D4),
DEF_MOD("i2c6", 918, R8A7795_CLK_S3D2),
DEF_MOD("i2c5", 919, R8A7795_CLK_S3D2),
DEF_MOD("i2c6", 918, R8A7795_CLK_S0D6),
DEF_MOD("i2c5", 919, R8A7795_CLK_S0D6),
DEF_MOD("i2c-dvfs", 926, R8A7795_CLK_CP),
DEF_MOD("i2c4", 927, R8A7795_CLK_S3D2),
DEF_MOD("i2c3", 928, R8A7795_CLK_S3D2),
DEF_MOD("i2c4", 927, R8A7795_CLK_S0D6),
DEF_MOD("i2c3", 928, R8A7795_CLK_S0D6),
DEF_MOD("i2c2", 929, R8A7795_CLK_S3D2),
DEF_MOD("i2c1", 930, R8A7795_CLK_S3D2),
DEF_MOD("i2c0", 931, R8A7795_CLK_S3D2),
@ -346,6 +350,7 @@ static const struct mssr_mod_reparent r8a7795es1_mod_reparent[] __initconst = {
{ MOD_CLK_ID(219), R8A7795_CLK_S3D1 }, /* SYS-DMAC0 */
{ MOD_CLK_ID(501), R8A7795_CLK_S3D1 }, /* AUDMAC1 */
{ MOD_CLK_ID(502), R8A7795_CLK_S3D1 }, /* AUDMAC0 */
{ MOD_CLK_ID(523), R8A7795_CLK_S3D4 }, /* PWM */
{ MOD_CLK_ID(601), R8A7795_CLK_S2D1 }, /* FCPVD2 */
{ MOD_CLK_ID(602), R8A7795_CLK_S2D1 }, /* FCPVD1 */
{ MOD_CLK_ID(603), R8A7795_CLK_S2D1 }, /* FCPVD0 */
@ -376,6 +381,18 @@ static const struct mssr_mod_reparent r8a7795es1_mod_reparent[] __initconst = {
{ MOD_CLK_ID(821), R8A7795_CLK_S2D1 }, /* IMR2 */
{ MOD_CLK_ID(822), R8A7795_CLK_S2D1 }, /* IMR1 */
{ MOD_CLK_ID(823), R8A7795_CLK_S2D1 }, /* IMR0 */
{ MOD_CLK_ID(905), R8A7795_CLK_CP }, /* GPIO7 */
{ MOD_CLK_ID(906), R8A7795_CLK_CP }, /* GPIO6 */
{ MOD_CLK_ID(907), R8A7795_CLK_CP }, /* GPIO5 */
{ MOD_CLK_ID(908), R8A7795_CLK_CP }, /* GPIO4 */
{ MOD_CLK_ID(909), R8A7795_CLK_CP }, /* GPIO3 */
{ MOD_CLK_ID(910), R8A7795_CLK_CP }, /* GPIO2 */
{ MOD_CLK_ID(911), R8A7795_CLK_CP }, /* GPIO1 */
{ MOD_CLK_ID(912), R8A7795_CLK_CP }, /* GPIO0 */
{ MOD_CLK_ID(918), R8A7795_CLK_S3D2 }, /* I2C6 */
{ MOD_CLK_ID(919), R8A7795_CLK_S3D2 }, /* I2C5 */
{ MOD_CLK_ID(927), R8A7795_CLK_S3D2 }, /* I2C4 */
{ MOD_CLK_ID(928), R8A7795_CLK_S3D2 }, /* I2C3 */
};

39
drivers/clk/renesas/r8a7796-cpg-mssr.c
View File

@ -106,6 +106,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
DEF_DIV6P1("canfd", R8A7796_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
DEF_DIV6P1("csi0", R8A7796_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
DEF_DIV6P1("mso", R8A7796_CLK_MSO, CLK_PLL1_DIV4, 0x014),
DEF_DIV6P1("hdmi", R8A7796_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
DEF_DIV6_RO("osc", R8A7796_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
DEF_DIV6_RO("r_int", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
@ -135,8 +136,15 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
DEF_MOD("sdif2", 312, R8A7796_CLK_SD2),
DEF_MOD("sdif1", 313, R8A7796_CLK_SD1),
DEF_MOD("sdif0", 314, R8A7796_CLK_SD0),
DEF_MOD("pcie1", 318, R8A7796_CLK_S3D1),
DEF_MOD("pcie0", 319, R8A7796_CLK_S3D1),
DEF_MOD("usb-dmac0", 330, R8A7796_CLK_S3D1),
DEF_MOD("usb-dmac1", 331, R8A7796_CLK_S3D1),
DEF_MOD("rwdt", 402, R8A7796_CLK_R),
DEF_MOD("intc-ex", 407, R8A7796_CLK_CP),
DEF_MOD("intc-ap", 408, R8A7796_CLK_S3D1),
DEF_MOD("audmac1", 501, R8A7796_CLK_S0D3),
DEF_MOD("audmac0", 502, R8A7796_CLK_S0D3),
DEF_MOD("drif7", 508, R8A7796_CLK_S3D2),
DEF_MOD("drif6", 509, R8A7796_CLK_S3D2),
DEF_MOD("drif5", 510, R8A7796_CLK_S3D2),
@ -151,6 +159,7 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
DEF_MOD("hscif1", 519, R8A7796_CLK_S3D1),
DEF_MOD("hscif0", 520, R8A7796_CLK_S3D1),
DEF_MOD("thermal", 522, R8A7796_CLK_CP),
DEF_MOD("pwm", 523, R8A7796_CLK_S0D12),
DEF_MOD("fcpvd2", 601, R8A7796_CLK_S0D2),
DEF_MOD("fcpvd1", 602, R8A7796_CLK_S0D2),
DEF_MOD("fcpvd0", 603, R8A7796_CLK_S0D2),
@ -164,12 +173,16 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
DEF_MOD("vspd0", 623, R8A7796_CLK_S0D2),
DEF_MOD("vspb", 626, R8A7796_CLK_S0D1),
DEF_MOD("vspi0", 631, R8A7796_CLK_S0D1),
DEF_MOD("ehci1", 702, R8A7796_CLK_S3D4),
DEF_MOD("ehci0", 703, R8A7796_CLK_S3D4),
DEF_MOD("hsusb", 704, R8A7796_CLK_S3D4),
DEF_MOD("csi20", 714, R8A7796_CLK_CSI0),
DEF_MOD("csi40", 716, R8A7796_CLK_CSI0),
DEF_MOD("du2", 722, R8A7796_CLK_S2D1),
DEF_MOD("du1", 723, R8A7796_CLK_S2D1),
DEF_MOD("du0", 724, R8A7796_CLK_S2D1),
DEF_MOD("lvds", 727, R8A7796_CLK_S2D1),
DEF_MOD("hdmi0", 729, R8A7796_CLK_HDMI),
DEF_MOD("vin7", 804, R8A7796_CLK_S0D2),
DEF_MOD("vin6", 805, R8A7796_CLK_S0D2),
DEF_MOD("vin5", 806, R8A7796_CLK_S0D2),
@ -200,6 +213,32 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
DEF_MOD("i2c2", 929, R8A7796_CLK_S3D2),
DEF_MOD("i2c1", 930, R8A7796_CLK_S3D2),
DEF_MOD("i2c0", 931, R8A7796_CLK_S3D2),
DEF_MOD("ssi-all", 1005, R8A7796_CLK_S3D4),
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
DEF_MOD("scu-all", 1017, R8A7796_CLK_S3D4),
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
};
static const unsigned int r8a7796_crit_mod_clks[] __initconst = {

41
drivers/clk/renesas/renesas-cpg-mssr.c
View File

@ -257,7 +257,7 @@ static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
const struct cpg_mssr_info *info,
struct cpg_mssr_priv *priv)
{
struct clk *clk = NULL, *parent;
struct clk *clk = ERR_PTR(-ENOTSUPP), *parent;
struct device *dev = priv->dev;
unsigned int id = core->id, div = core->div;
const char *parent_name;
@ -477,7 +477,7 @@ fail_put:
void cpg_mssr_detach_dev(struct generic_pm_domain *unused, struct device *dev)
{
if (!list_empty(&dev->power.subsys_data->clock_list))
if (!pm_clk_no_clocks(dev))
pm_clk_destroy(dev);
}
@ -627,25 +627,54 @@ static inline int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv)
static const struct of_device_id cpg_mssr_match[] = {
#ifdef CONFIG_ARCH_R8A7743
#ifdef CONFIG_CLK_R8A7743
{
.compatible = "renesas,r8a7743-cpg-mssr",
.data = &r8a7743_cpg_mssr_info,
},
#endif
#ifdef CONFIG_ARCH_R8A7745
#ifdef CONFIG_CLK_R8A7745
{
.compatible = "renesas,r8a7745-cpg-mssr",
.data = &r8a7745_cpg_mssr_info,
},
#endif
#ifdef CONFIG_ARCH_R8A7795
#ifdef CONFIG_CLK_R8A7790
{
.compatible = "renesas,r8a7790-cpg-mssr",
.data = &r8a7790_cpg_mssr_info,
},
#endif
#ifdef CONFIG_CLK_R8A7791
{
.compatible = "renesas,r8a7791-cpg-mssr",
.data = &r8a7791_cpg_mssr_info,
},
/* R-Car M2-N is (almost) identical to R-Car M2-W w.r.t. clocks. */
{
.compatible = "renesas,r8a7793-cpg-mssr",
.data = &r8a7791_cpg_mssr_info,
},
#endif
#ifdef CONFIG_CLK_R8A7792
{
.compatible = "renesas,r8a7792-cpg-mssr",
.data = &r8a7792_cpg_mssr_info,
},
#endif
#ifdef CONFIG_CLK_R8A7794
{
.compatible = "renesas,r8a7794-cpg-mssr",
.data = &r8a7794_cpg_mssr_info,
},
#endif
#ifdef CONFIG_CLK_R8A7795
{
.compatible = "renesas,r8a7795-cpg-mssr",
.data = &r8a7795_cpg_mssr_info,
},
#endif
#ifdef CONFIG_ARCH_R8A7796
#ifdef CONFIG_CLK_R8A7796
{
.compatible = "renesas,r8a7796-cpg-mssr",
.data = &r8a7796_cpg_mssr_info,

4
drivers/clk/renesas/renesas-cpg-mssr.h
View File

@ -132,6 +132,10 @@ struct cpg_mssr_info {
extern const struct cpg_mssr_info r8a7743_cpg_mssr_info;
extern const struct cpg_mssr_info r8a7745_cpg_mssr_info;
extern const struct cpg_mssr_info r8a7790_cpg_mssr_info;
extern const struct cpg_mssr_info r8a7791_cpg_mssr_info;
extern const struct cpg_mssr_info r8a7792_cpg_mssr_info;
extern const struct cpg_mssr_info r8a7794_cpg_mssr_info;
extern const struct cpg_mssr_info r8a7795_cpg_mssr_info;
extern const struct cpg_mssr_info r8a7796_cpg_mssr_info;

52
include/dt-bindings/clock/r8a7790-cpg-mssr.h Normal file
View File

@ -0,0 +1,52 @@
/*
* Copyright (C) 2015 Renesas Electronics Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* r8a7790 CPG Core Clocks */
#define R8A7790_CLK_Z 0
#define R8A7790_CLK_Z2 1
#define R8A7790_CLK_ZG 2
#define R8A7790_CLK_ZTR 3
#define R8A7790_CLK_ZTRD2 4
#define R8A7790_CLK_ZT 5
#define R8A7790_CLK_ZX 6
#define R8A7790_CLK_ZS 7
#define R8A7790_CLK_HP 8
#define R8A7790_CLK_I 9
#define R8A7790_CLK_B 10
#define R8A7790_CLK_LB 11
#define R8A7790_CLK_P 12
#define R8A7790_CLK_CL 13
#define R8A7790_CLK_M2 14
#define R8A7790_CLK_ADSP 15
#define R8A7790_CLK_IMP 16
#define R8A7790_CLK_ZB3 17
#define R8A7790_CLK_ZB3D2 18
#define R8A7790_CLK_DDR 19
#define R8A7790_CLK_SDH 20
#define R8A7790_CLK_SD0 21
#define R8A7790_CLK_SD1 22
#define R8A7790_CLK_SD2 23
#define R8A7790_CLK_SD3 24
#define R8A7790_CLK_MMC0 25
#define R8A7790_CLK_MMC1 26
#define R8A7790_CLK_MP 27
#define R8A7790_CLK_SSP 28
#define R8A7790_CLK_SSPRS 29
#define R8A7790_CLK_QSPI 30
#define R8A7790_CLK_CP 31
#define R8A7790_CLK_RCAN 32
#define R8A7790_CLK_R 33
#define R8A7790_CLK_OSC 34
#endif /* __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ */

48
include/dt-bindings/clock/r8a7791-cpg-mssr.h Normal file
View File

@ -0,0 +1,48 @@
/*
* Copyright (C) 2015 Renesas Electronics Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* r8a7791 CPG Core Clocks */
#define R8A7791_CLK_Z 0
#define R8A7791_CLK_ZG 1
#define R8A7791_CLK_ZTR 2
#define R8A7791_CLK_ZTRD2 3
#define R8A7791_CLK_ZT 4
#define R8A7791_CLK_ZX 5
#define R8A7791_CLK_ZS 6
#define R8A7791_CLK_HP 7
#define R8A7791_CLK_I 8
#define R8A7791_CLK_B 9
#define R8A7791_CLK_LB 10
#define R8A7791_CLK_P 11
#define R8A7791_CLK_CL 12
#define R8A7791_CLK_M2 13
#define R8A7791_CLK_ADSP 14
#define R8A7791_CLK_ZB3 15
#define R8A7791_CLK_ZB3D2 16
#define R8A7791_CLK_DDR 17
#define R8A7791_CLK_SDH 18
#define R8A7791_CLK_SD0 19
#define R8A7791_CLK_SD2 20
#define R8A7791_CLK_SD3 21
#define R8A7791_CLK_MMC0 22
#define R8A7791_CLK_MP 23
#define R8A7791_CLK_SSP 24
#define R8A7791_CLK_SSPRS 25
#define R8A7791_CLK_QSPI 26
#define R8A7791_CLK_CP 27
#define R8A7791_CLK_RCAN 28
#define R8A7791_CLK_R 29
#define R8A7791_CLK_OSC 30
#endif /* __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__ */

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/*
* Copyright (C) 2015 Renesas Electronics Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* r8a7792 CPG Core Clocks */
#define R8A7792_CLK_Z 0
#define R8A7792_CLK_ZG 1
#define R8A7792_CLK_ZTR 2
#define R8A7792_CLK_ZTRD2 3
#define R8A7792_CLK_ZT 4
#define R8A7792_CLK_ZX 5
#define R8A7792_CLK_ZS 6
#define R8A7792_CLK_HP 7
#define R8A7792_CLK_I 8
#define R8A7792_CLK_B 9
#define R8A7792_CLK_LB 10
#define R8A7792_CLK_P 11
#define R8A7792_CLK_CL 12
#define R8A7792_CLK_M2 13
#define R8A7792_CLK_IMP 14
#define R8A7792_CLK_ZB3 15
#define R8A7792_CLK_ZB3D2 16
#define R8A7792_CLK_DDR 17
#define R8A7792_CLK_SD 18
#define R8A7792_CLK_MP 19
#define R8A7792_CLK_QSPI 20
#define R8A7792_CLK_CP 21
#define R8A7792_CLK_CPEX 22
#define R8A7792_CLK_RCAN 23
#define R8A7792_CLK_R 24
#define R8A7792_CLK_OSC 25
#endif /* __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__ */

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/*
* Copyright (C) 2015 Renesas Electronics Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* r8a7793 CPG Core Clocks */
#define R8A7793_CLK_Z 0
#define R8A7793_CLK_ZG 1
#define R8A7793_CLK_ZTR 2
#define R8A7793_CLK_ZTRD2 3
#define R8A7793_CLK_ZT 4
#define R8A7793_CLK_ZX 5
#define R8A7793_CLK_ZS 6
#define R8A7793_CLK_HP 7
#define R8A7793_CLK_I 8
#define R8A7793_CLK_B 9
#define R8A7793_CLK_LB 10
#define R8A7793_CLK_P 11
#define R8A7793_CLK_CL 12
#define R8A7793_CLK_M2 13
#define R8A7793_CLK_ADSP 14
#define R8A7793_CLK_ZB3 15
#define R8A7793_CLK_ZB3D2 16
#define R8A7793_CLK_DDR 17
#define R8A7793_CLK_SDH 18
#define R8A7793_CLK_SD0 19
#define R8A7793_CLK_SD2 20
#define R8A7793_CLK_SD3 21
#define R8A7793_CLK_MMC0 22
#define R8A7793_CLK_MP 23
#define R8A7793_CLK_SSP 24
#define R8A7793_CLK_SSPRS 25
#define R8A7793_CLK_QSPI 26
#define R8A7793_CLK_CP 27
#define R8A7793_CLK_RCAN 28
#define R8A7793_CLK_R 29
#define R8A7793_CLK_OSC 30
#endif /* __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__ */

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/*
* Copyright (C) 2015 Renesas Electronics Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* r8a7794 CPG Core Clocks */
#define R8A7794_CLK_Z2 0
#define R8A7794_CLK_ZG 1
#define R8A7794_CLK_ZTR 2
#define R8A7794_CLK_ZTRD2 3
#define R8A7794_CLK_ZT 4
#define R8A7794_CLK_ZX 5
#define R8A7794_CLK_ZS 6
#define R8A7794_CLK_HP 7
#define R8A7794_CLK_I 8
#define R8A7794_CLK_B 9
#define R8A7794_CLK_LB 10
#define R8A7794_CLK_P 11
#define R8A7794_CLK_CL 12
#define R8A7794_CLK_CP 13
#define R8A7794_CLK_M2 14
#define R8A7794_CLK_ADSP 15
#define R8A7794_CLK_ZB3 16
#define R8A7794_CLK_ZB3D2 17
#define R8A7794_CLK_DDR 18
#define R8A7794_CLK_SDH 19
#define R8A7794_CLK_SD0 20
#define R8A7794_CLK_SD2 21
#define R8A7794_CLK_SD3 22
#define R8A7794_CLK_MMC0 23
#define R8A7794_CLK_MP 24
#define R8A7794_CLK_QSPI 25
#define R8A7794_CLK_CPEX 26
#define R8A7794_CLK_RCAN 27
#define R8A7794_CLK_R 28
#define R8A7794_CLK_OSC 29
#endif /* __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ */