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drm/msm: drop quirks binding
This was never documented or used in upstream dtb. It is used by downstream bindings from android device kernels. But the quirks are a property of the gpu revision, and as such are redundant to be listed separately in dt. Instead, move the quirks to the device table. Signed-off-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net>
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@ -327,7 +327,7 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
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/* Enable RBBM error reporting bits */
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gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL0, 0x00000001);
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if (adreno_gpu->quirks & ADRENO_QUIRK_FAULT_DETECT_MASK) {
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if (adreno_gpu->info->quirks & ADRENO_QUIRK_FAULT_DETECT_MASK) {
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/*
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* Mask out the activity signals from RB1-3 to avoid false
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* positives
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@ -381,7 +381,7 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
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gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, (0x400 << 11 | 0x300 << 22));
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if (adreno_gpu->quirks & ADRENO_QUIRK_TWO_PASS_USE_WFI)
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if (adreno_gpu->info->quirks & ADRENO_QUIRK_TWO_PASS_USE_WFI)
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gpu_rmw(gpu, REG_A5XX_PC_DBG_ECO_CNTL, 0, (1 << 8));
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gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, 0xc0200100);
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@ -75,12 +75,14 @@ static const struct adreno_info gpulist[] = {
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.gmem = (SZ_1M + SZ_512K),
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.init = a4xx_gpu_init,
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}, {
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.rev = ADRENO_REV(5, 3, 0, ANY_ID),
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.rev = ADRENO_REV(5, 3, 0, 2),
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.revn = 530,
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.name = "A530",
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.pm4fw = "a530_pm4.fw",
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.pfpfw = "a530_pfp.fw",
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.gmem = SZ_1M,
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.quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI |
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ADRENO_QUIRK_FAULT_DETECT_MASK,
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.init = a5xx_gpu_init,
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.gpmufw = "a530v3_gpmu.fw2",
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},
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@ -181,14 +183,6 @@ static void set_gpu_pdev(struct drm_device *dev,
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priv->gpu_pdev = pdev;
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}
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static const struct {
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const char *str;
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uint32_t flag;
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} quirks[] = {
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{ "qcom,gpu-quirk-two-pass-use-wfi", ADRENO_QUIRK_TWO_PASS_USE_WFI },
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{ "qcom,gpu-quirk-fault-detect-mask", ADRENO_QUIRK_FAULT_DETECT_MASK },
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};
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static int find_chipid(struct device *dev, u32 *chipid)
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{
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struct device_node *node = dev->of_node;
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@ -231,7 +225,7 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
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static struct adreno_platform_config config = {};
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struct device_node *child, *node = dev->of_node;
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u32 val;
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int ret, i;
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int ret;
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ret = find_chipid(dev, &val);
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if (ret) {
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@ -267,10 +261,6 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
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config.slow_rate = 27000000;
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}
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for (i = 0; i < ARRAY_SIZE(quirks); i++)
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if (of_property_read_bool(node, quirks[i].str))
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config.quirks |= quirks[i].flag;
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dev->platform_data = &config;
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set_gpu_pdev(dev_get_drvdata(master), to_platform_device(dev));
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return 0;
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@ -352,7 +352,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
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adreno_gpu->gmem = adreno_gpu->info->gmem;
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adreno_gpu->revn = adreno_gpu->info->revn;
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adreno_gpu->rev = config->rev;
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adreno_gpu->quirks = config->quirks;
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gpu->fast_rate = config->fast_rate;
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gpu->slow_rate = config->slow_rate;
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@ -75,6 +75,7 @@ struct adreno_info {
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const char *pm4fw, *pfpfw;
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const char *gpmufw;
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uint32_t gmem;
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enum adreno_quirks quirks;
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struct msm_gpu *(*init)(struct drm_device *dev);
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};
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@ -116,8 +117,6 @@ struct adreno_gpu {
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* code (a3xx_gpu.c) and stored in this common location.
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*/
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const unsigned int *reg_offsets;
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uint32_t quirks;
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};
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#define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base)
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@ -128,7 +127,6 @@ struct adreno_platform_config {
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#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
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struct msm_bus_scale_pdata *bus_scale_table;
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#endif
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uint32_t quirks;
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};
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#define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000)
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