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drm/i915/gen9: Always set mask memory up when enabling DC5 or DC6

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Move call to gen9_set_dc_state_debugmask_memory_up() into
gen9_set_dc_state() to prevent us missing it somewhere.

Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1447084107-8521-3-git-send-email-patrik.jakobsson@linux.intel.com
This commit is contained in:
Patrik Jakobsson 2015-11-09 16:48:17 +01:00 committed by Imre Deak
parent fc131bf209
commit 4deccbb26b
1 changed files with 17 additions and 18 deletions
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35
drivers/gpu/drm/i915/intel_runtime_pm.c
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@ -395,6 +395,20 @@ static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
*/ */
} }
static void gen9_set_dc_state_debugmask_memory_up(
struct drm_i915_private *dev_priv)
{
uint32_t val;
/* The below bit doesn't need to be cleared ever afterwards */
val = I915_READ(DC_STATE_DEBUG);
if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) {
val |= DC_STATE_DEBUG_MASK_MEMORY_UP;
I915_WRITE(DC_STATE_DEBUG, val);
POSTING_READ(DC_STATE_DEBUG);
}
}
static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state) static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
{ {
uint32_t val; uint32_t val;
@ -408,6 +422,9 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
WARN_ON_ONCE(state & ~mask); WARN_ON_ONCE(state & ~mask);
if (state & DC_STATE_EN_UPTO_DC5_DC6_MASK)
gen9_set_dc_state_debugmask_memory_up(dev_priv);
val = I915_READ(DC_STATE_EN); val = I915_READ(DC_STATE_EN);
DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n", DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
val & mask, state); val & mask, state);
@ -435,20 +452,6 @@ void bxt_disable_dc9(struct drm_i915_private *dev_priv)
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
} }
static void gen9_set_dc_state_debugmask_memory_up(
struct drm_i915_private *dev_priv)
{
uint32_t val;
/* The below bit doesn't need to be cleared ever afterwards */
val = I915_READ(DC_STATE_DEBUG);
if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) {
val |= DC_STATE_DEBUG_MASK_MEMORY_UP;
I915_WRITE(DC_STATE_DEBUG, val);
POSTING_READ(DC_STATE_DEBUG);
}
}
static void assert_csr_loaded(struct drm_i915_private *dev_priv) static void assert_csr_loaded(struct drm_i915_private *dev_priv)
{ {
WARN_ONCE(!I915_READ(CSR_PROGRAM(0)), WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
@ -497,8 +500,6 @@ static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
DRM_DEBUG_KMS("Enabling DC5\n"); DRM_DEBUG_KMS("Enabling DC5\n");
gen9_set_dc_state_debugmask_memory_up(dev_priv);
gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5); gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
} }
@ -544,8 +545,6 @@ void skl_enable_dc6(struct drm_i915_private *dev_priv)
DRM_DEBUG_KMS("Enabling DC6\n"); DRM_DEBUG_KMS("Enabling DC6\n");
gen9_set_dc_state_debugmask_memory_up(dev_priv);
gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
} }