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mlx4_core: Add support for steerable IB UD QPs
This patch adds support for allocating IB UD QPs that we can steer traffic from. We introduce a new firmware command FLOW_STEERING_IB_UC_QP_RANGE and a capability bit. This command isn't supported for VFs. Signed-off-by: Matan Barak <matanb@mellanox.com> Signed-off-by: Or Gerlitz <ogerlitz@mellanox.com> Signed-off-by: Roland Dreier <roland@purestorage.com>
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@ -1371,6 +1371,15 @@ static struct mlx4_cmd_info cmd_info[] = {
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.verify = NULL,
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.wrapper = mlx4_QP_FLOW_STEERING_DETACH_wrapper
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},
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{
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.opcode = MLX4_FLOW_STEERING_IB_UC_QP_RANGE,
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.has_inbox = false,
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.has_outbox = false,
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.out_is_imm = false,
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.encode_slave_id = false,
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.verify = NULL,
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.wrapper = mlx4_FLOW_STEERING_IB_UC_QP_RANGE_wrapper
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},
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};
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static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
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@ -513,6 +513,7 @@ int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
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#define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67
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#define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68
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#define QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET 0x70
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#define QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET 0x74
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#define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76
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#define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77
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#define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
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@ -603,6 +604,9 @@ int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
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if (field & 0x80)
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dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN;
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dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f;
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MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
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if (field & 0x80)
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dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_IPOIB;
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MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET);
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dev_cap->fs_max_num_qp_per_entry = field;
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MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
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@ -860,6 +864,12 @@ int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
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MLX4_PUT(outbox->buf, field,
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QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
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}
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/* turn off ipoib managed steering for guests */
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MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
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field &= ~0x80;
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MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
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return 0;
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}
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@ -895,6 +895,23 @@ int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id)
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}
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EXPORT_SYMBOL_GPL(mlx4_flow_detach);
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int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn,
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u32 max_range_qpn)
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{
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int err;
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u64 in_param;
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in_param = ((u64) min_range_qpn) << 32;
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in_param |= ((u64) max_range_qpn) & 0xFFFFFFFF;
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err = mlx4_cmd(dev, in_param, 0, 0,
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MLX4_FLOW_STEERING_IB_UC_QP_RANGE,
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MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
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return err;
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}
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EXPORT_SYMBOL_GPL(mlx4_FLOW_STEERING_IB_UC_QP_RANGE);
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int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
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int block_mcast_loopback, enum mlx4_protocol prot,
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enum mlx4_steer_type steer)
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@ -1236,6 +1236,11 @@ int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
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struct mlx4_cmd_mailbox *inbox,
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struct mlx4_cmd_mailbox *outbox,
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struct mlx4_cmd_info *cmd);
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int mlx4_FLOW_STEERING_IB_UC_QP_RANGE_wrapper(struct mlx4_dev *dev, int slave,
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struct mlx4_vhcr *vhcr,
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struct mlx4_cmd_mailbox *inbox,
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struct mlx4_cmd_mailbox *outbox,
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struct mlx4_cmd_info *cmd);
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int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
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int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
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@ -3844,6 +3844,16 @@ int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
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return err;
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}
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int mlx4_FLOW_STEERING_IB_UC_QP_RANGE_wrapper(struct mlx4_dev *dev, int slave,
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struct mlx4_vhcr *vhcr,
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struct mlx4_cmd_mailbox *inbox,
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struct mlx4_cmd_mailbox *outbox,
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struct mlx4_cmd_info *cmd)
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{
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return -EPERM;
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}
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static void detach_qp(struct mlx4_dev *dev, int slave, struct res_qp *rqp)
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{
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struct res_gid *rgid;
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@ -157,6 +157,7 @@ enum {
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/* register/delete flow steering network rules */
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MLX4_QP_FLOW_STEERING_ATTACH = 0x65,
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MLX4_QP_FLOW_STEERING_DETACH = 0x66,
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MLX4_FLOW_STEERING_IB_UC_QP_RANGE = 0x64,
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};
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enum {
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@ -160,7 +160,8 @@ enum {
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MLX4_DEV_CAP_FLAG2_TS = 1LL << 5,
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MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6,
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MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7,
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MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8
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MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8,
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MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9
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};
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enum {
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@ -1144,6 +1145,9 @@ int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int
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void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid);
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__be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave);
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int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn,
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u32 max_range_qpn);
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cycle_t mlx4_read_clock(struct mlx4_dev *dev);
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#endif /* MLX4_DEVICE_H */
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