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drm/bridge: tc358767: fix 1-lane behavior
Use drm_dp_channel_eq_ok helper Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Andrey Gusakov <andrey.gusakov@cogentembedded.com> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Link: https://patchwork.freedesktop.org/patch/msgid/1510073785-16108-7-git-send-email-andrey.gusakov@cogentembedded.com
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@ -819,8 +819,6 @@ static int tc_main_link_setup(struct tc_data *tc)
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unsigned int rate;
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u32 dp_phy_ctrl;
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int timeout;
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bool aligned;
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bool ready;
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u32 value;
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int ret;
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u8 tmp[8];
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@ -965,16 +963,15 @@ static int tc_main_link_setup(struct tc_data *tc)
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ret = drm_dp_dpcd_read_link_status(aux, tmp + 2);
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if (ret < 0)
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goto err_dpcd_read;
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ready = (tmp[2] == ((DP_CHANNEL_EQ_BITS << 4) | /* Lane1 */
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DP_CHANNEL_EQ_BITS)); /* Lane0 */
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aligned = tmp[4] & DP_INTERLANE_ALIGN_DONE;
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} while ((--timeout) && !(ready && aligned));
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} while ((--timeout) &&
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!(drm_dp_channel_eq_ok(tmp + 2, tc->link.base.num_lanes)));
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if (timeout == 0) {
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/* Read DPCD 0x200-0x201 */
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ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT, tmp, 2);
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if (ret < 0)
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goto err_dpcd_read;
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dev_err(dev, "channel(s) EQ not ok\n");
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dev_info(dev, "0x0200 SINK_COUNT: 0x%02x\n", tmp[0]);
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dev_info(dev, "0x0201 DEVICE_SERVICE_IRQ_VECTOR: 0x%02x\n",
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tmp[1]);
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@ -985,10 +982,6 @@ static int tc_main_link_setup(struct tc_data *tc)
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dev_info(dev, "0x0206 ADJUST_REQUEST_LANE0_1: 0x%02x\n",
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tmp[6]);
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if (!ready)
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dev_err(dev, "Lane0/1 not ready\n");
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if (!aligned)
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dev_err(dev, "Lane0/1 not aligned\n");
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return -EAGAIN;
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}
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