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clk: mvebu: add missing CESA gate clk

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Even if not documented in the datasheet, the Armada 370 SoC can actually
gate the CESA (crypto engine) clock.
Add an entry in the gating_desc table to be able to reference the CESA
gateclk in the crypto node.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
This commit is contained in:
Boris Brezillon 2015-05-26 14:42:57 +02:00 committed by Michael Turquette
parent 5343325ff3
commit 4d52b2acef
2 changed files with 2 additions and 0 deletions
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1
Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
View File

@ -19,6 +19,7 @@ ID Clock Peripheral
9 pex1 PCIe Cntrl 1 9 pex1 PCIe Cntrl 1
15 sata0 SATA Host 0 15 sata0 SATA Host 0
17 sdio SDHCI Host 17 sdio SDHCI Host
23 crypto CESA (crypto engine)
25 tdm Time Division Mplx 25 tdm Time Division Mplx
28 ddr DDR Cntrl 28 ddr DDR Cntrl
30 sata1 SATA Host 0 30 sata1 SATA Host 0

1
drivers/clk/mvebu/armada-370.c
View File

@ -163,6 +163,7 @@ static const struct clk_gating_soc_desc a370_gating_desc[] __initconst = {
{ "pex1", "pex1_en", 9, 0 }, { "pex1", "pex1_en", 9, 0 },
{ "sata0", NULL, 15, 0 }, { "sata0", NULL, 15, 0 },
{ "sdio", NULL, 17, 0 }, { "sdio", NULL, 17, 0 },
{ "crypto", NULL, 23, 0 },
{ "tdm", NULL, 25, 0 }, { "tdm", NULL, 25, 0 },
{ "ddr", NULL, 28, CLK_IGNORE_UNUSED }, { "ddr", NULL, 28, CLK_IGNORE_UNUSED },
{ "sata1", NULL, 30, 0 }, { "sata1", NULL, 30, 0 },