mirror of
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drm/amdgpu: add DP audio support for si dce6 (v3)
v2: refine dce_v6_0_audio_endpt_wreg() and unify inconsistent method names v3: fix num_pins for tahiti, pitcairn, verde and oland Signed-off-by: Xiaojie Yuan <Xiaojie.Yuan@amd.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Junwei Zhang <Jerry.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Xiaojie Yuan
Alex Deucher
parent
6a124e675a
commit
4caca70668
@ -118,14 +118,27 @@ static const struct {
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static u32 dce_v6_0_audio_endpt_rreg(struct amdgpu_device *adev,
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u32 block_offset, u32 reg)
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{
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DRM_INFO("xxxx: dce_v6_0_audio_endpt_rreg ----no impl!!!!\n");
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return 0;
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unsigned long flags;
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u32 r;
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spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
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WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
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r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
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spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
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return r;
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}
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static void dce_v6_0_audio_endpt_wreg(struct amdgpu_device *adev,
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u32 block_offset, u32 reg, u32 v)
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{
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DRM_INFO("xxxx: dce_v6_0_audio_endpt_wreg ----no impl!!!!\n");
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unsigned long flags;
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spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
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WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset,
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reg | AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_WRITE_EN_MASK);
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WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
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spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
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}
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static bool dce_v6_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
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@ -1222,17 +1235,17 @@ static void dce_v6_0_bandwidth_update(struct amdgpu_device *adev)
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dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i+1], lb_size, num_heads);
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}
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}
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/*
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static void dce_v6_0_audio_get_connected_pins(struct amdgpu_device *adev)
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{
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int i;
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u32 offset, tmp;
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u32 tmp;
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for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
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offset = adev->mode_info.audio.pin[i].offset;
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tmp = RREG32_AUDIO_ENDPT(offset,
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AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
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if (((tmp & PORT_CONNECTIVITY_MASK) >> PORT_CONNECTIVITY_SHIFT) == 1)
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tmp = RREG32_AUDIO_ENDPT(adev->mode_info.audio.pin[i].offset,
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ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
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if (REG_GET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT,
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PORT_CONNECTIVITY))
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adev->mode_info.audio.pin[i].connected = false;
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else
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adev->mode_info.audio.pin[i].connected = true;
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@ -1254,45 +1267,206 @@ static struct amdgpu_audio_pin *dce_v6_0_audio_get_pin(struct amdgpu_device *ade
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return NULL;
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}
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static void dce_v6_0_afmt_audio_select_pin(struct drm_encoder *encoder)
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static void dce_v6_0_audio_select_pin(struct drm_encoder *encoder)
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{
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struct amdgpu_device *adev = encoder->dev->dev_private;
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struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
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struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
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u32 offset;
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if (!dig || !dig->afmt || !dig->afmt->pin)
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return;
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offset = dig->afmt->offset;
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WREG32(AFMT_AUDIO_SRC_CONTROL + offset,
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AFMT_AUDIO_SRC_SELECT(dig->afmt->pin->id));
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WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset,
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REG_SET_FIELD(0, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT,
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dig->afmt->pin->id));
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}
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static void dce_v6_0_audio_write_latency_fields(struct drm_encoder *encoder,
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struct drm_display_mode *mode)
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{
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DRM_INFO("xxxx: dce_v6_0_audio_write_latency_fields---no imp!!!!!\n");
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struct amdgpu_device *adev = encoder->dev->dev_private;
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struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
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struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
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struct drm_connector *connector;
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struct amdgpu_connector *amdgpu_connector = NULL;
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int interlace = 0;
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u32 tmp;
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list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
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if (connector->encoder == encoder) {
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amdgpu_connector = to_amdgpu_connector(connector);
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break;
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}
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}
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if (!amdgpu_connector) {
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DRM_ERROR("Couldn't find encoder's connector\n");
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return;
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}
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if (mode->flags & DRM_MODE_FLAG_INTERLACE)
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interlace = 1;
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if (connector->latency_present[interlace]) {
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tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
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VIDEO_LIPSYNC, connector->video_latency[interlace]);
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tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
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AUDIO_LIPSYNC, connector->audio_latency[interlace]);
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} else {
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tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
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VIDEO_LIPSYNC, 0);
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tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
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AUDIO_LIPSYNC, 0);
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}
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WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
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ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
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}
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static void dce_v6_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
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{
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DRM_INFO("xxxx: dce_v6_0_audio_write_speaker_allocation---no imp!!!!!\n");
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struct amdgpu_device *adev = encoder->dev->dev_private;
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struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
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struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
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struct drm_connector *connector;
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struct amdgpu_connector *amdgpu_connector = NULL;
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u8 *sadb = NULL;
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int sad_count;
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u32 tmp;
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list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
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if (connector->encoder == encoder) {
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amdgpu_connector = to_amdgpu_connector(connector);
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break;
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}
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}
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if (!amdgpu_connector) {
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DRM_ERROR("Couldn't find encoder's connector\n");
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return;
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}
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sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
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if (sad_count < 0) {
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DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
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sad_count = 0;
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}
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/* program the speaker allocation */
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tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
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ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
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tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
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HDMI_CONNECTION, 0);
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tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
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DP_CONNECTION, 0);
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if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort)
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tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
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DP_CONNECTION, 1);
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else
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tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
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HDMI_CONNECTION, 1);
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if (sad_count)
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tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
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SPEAKER_ALLOCATION, sadb[0]);
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else
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tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
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SPEAKER_ALLOCATION, 5); /* stereo */
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WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
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ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
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kfree(sadb);
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}
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static void dce_v6_0_audio_write_sad_regs(struct drm_encoder *encoder)
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{
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DRM_INFO("xxxx: dce_v6_0_audio_write_sad_regs---no imp!!!!!\n");
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struct amdgpu_device *adev = encoder->dev->dev_private;
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struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
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struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
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struct drm_connector *connector;
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struct amdgpu_connector *amdgpu_connector = NULL;
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struct cea_sad *sads;
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int i, sad_count;
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static const u16 eld_reg_to_type[][2] = {
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{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
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{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
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{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
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{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
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{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
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{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
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{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
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{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
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{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
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{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
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{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
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{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
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};
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list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
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if (connector->encoder == encoder) {
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amdgpu_connector = to_amdgpu_connector(connector);
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break;
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}
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}
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if (!amdgpu_connector) {
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DRM_ERROR("Couldn't find encoder's connector\n");
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return;
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}
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sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
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if (sad_count <= 0) {
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DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
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return;
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}
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for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
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u32 tmp = 0;
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u8 stereo_freqs = 0;
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int max_channels = -1;
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int j;
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for (j = 0; j < sad_count; j++) {
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struct cea_sad *sad = &sads[j];
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if (sad->format == eld_reg_to_type[i][1]) {
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if (sad->channels > max_channels) {
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tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
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MAX_CHANNELS, sad->channels);
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tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
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DESCRIPTOR_BYTE_2, sad->byte2);
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tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
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SUPPORTED_FREQUENCIES, sad->freq);
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max_channels = sad->channels;
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}
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if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
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stereo_freqs |= sad->freq;
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else
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break;
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}
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}
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tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
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SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
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WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
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}
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kfree(sads);
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}
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*/
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static void dce_v6_0_audio_enable(struct amdgpu_device *adev,
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struct amdgpu_audio_pin *pin,
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bool enable)
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{
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DRM_INFO("xxxx: dce_v6_0_audio_enable---no imp!!!!!\n");
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if (!pin)
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return;
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WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
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enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
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}
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static const u32 pin_offsets[7] =
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@ -1308,12 +1482,54 @@ static const u32 pin_offsets[7] =
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static int dce_v6_0_audio_init(struct amdgpu_device *adev)
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{
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int i;
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if (!amdgpu_audio)
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return 0;
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adev->mode_info.audio.enabled = true;
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switch (adev->asic_type) {
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case CHIP_TAHITI:
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case CHIP_PITCAIRN:
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case CHIP_VERDE:
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default:
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adev->mode_info.audio.num_pins = 6;
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break;
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case CHIP_OLAND:
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adev->mode_info.audio.num_pins = 2;
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break;
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}
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for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
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adev->mode_info.audio.pin[i].channels = -1;
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adev->mode_info.audio.pin[i].rate = -1;
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adev->mode_info.audio.pin[i].bits_per_sample = -1;
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adev->mode_info.audio.pin[i].status_bits = 0;
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adev->mode_info.audio.pin[i].category_code = 0;
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adev->mode_info.audio.pin[i].connected = false;
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adev->mode_info.audio.pin[i].offset = pin_offsets[i];
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adev->mode_info.audio.pin[i].id = i;
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dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
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}
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return 0;
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}
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static void dce_v6_0_audio_fini(struct amdgpu_device *adev)
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{
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int i;
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if (!amdgpu_audio)
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return;
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if (!adev->mode_info.audio.enabled)
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return;
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for (i = 0; i < adev->mode_info.audio.num_pins; i++)
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dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
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adev->mode_info.audio.enabled = false;
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}
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/*
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@ -1322,28 +1538,204 @@ static void dce_v6_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock
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DRM_INFO("xxxx: dce_v6_0_afmt_update_ACR---no imp!!!!!\n");
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}
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*/
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/*
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* build a HDMI Video Info Frame
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*/
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/*
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static void dce_v6_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
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void *buffer, size_t size)
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static void dce_v6_0_audio_set_avi_infoframe(struct drm_encoder *encoder,
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struct drm_display_mode *mode)
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{
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DRM_INFO("xxxx: dce_v6_0_afmt_update_avi_infoframe---no imp!!!!!\n");
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struct drm_device *dev = encoder->dev;
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struct amdgpu_device *adev = dev->dev_private;
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struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
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struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
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struct hdmi_avi_infoframe frame;
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u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
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uint8_t *payload = buffer + 3;
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uint8_t *header = buffer;
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ssize_t err;
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u32 tmp;
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err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
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if (err < 0) {
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DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
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return;
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}
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err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
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if (err < 0) {
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DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
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return;
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}
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WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
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payload[0x0] | (payload[0x1] << 8) | (payload[0x2] << 16) | (payload[0x3] << 24));
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WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
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payload[0x4] | (payload[0x5] << 8) | (payload[0x6] << 16) | (payload[0x7] << 24));
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WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
|
||||
payload[0x8] | (payload[0x9] << 8) | (payload[0xA] << 16) | (payload[0xB] << 24));
|
||||
WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
|
||||
payload[0xC] | (payload[0xD] << 8) | (header[1] << 24));
|
||||
|
||||
tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
|
||||
/* anything other than 0 */
|
||||
tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1,
|
||||
HDMI_AUDIO_INFO_LINE, 2);
|
||||
WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
|
||||
}
|
||||
|
||||
static void dce_v6_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
|
||||
{
|
||||
DRM_INFO("xxxx: dce_v6_0_audio_set_dto---no imp!!!!!\n");
|
||||
struct drm_device *dev = encoder->dev;
|
||||
struct amdgpu_device *adev = dev->dev_private;
|
||||
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
|
||||
u32 tmp;
|
||||
|
||||
/*
|
||||
* Two dtos: generally use dto0 for hdmi, dto1 for dp.
|
||||
* Express [24MHz / target pixel clock] as an exact rational
|
||||
* number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
|
||||
* is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
|
||||
*/
|
||||
tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
|
||||
tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE,
|
||||
DCCG_AUDIO_DTO0_SOURCE_SEL, amdgpu_crtc->crtc_id);
|
||||
tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, 1);
|
||||
WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
|
||||
WREG32(mmDCCG_AUDIO_DTO1_PHASE, 24000);
|
||||
WREG32(mmDCCG_AUDIO_DTO1_MODULE, clock);
|
||||
}
|
||||
*/
|
||||
/*
|
||||
* update the info frames with the data from the current display mode
|
||||
*/
|
||||
|
||||
static void dce_v6_0_audio_set_packet(struct drm_encoder *encoder)
|
||||
{
|
||||
struct drm_device *dev = encoder->dev;
|
||||
struct amdgpu_device *adev = dev->dev_private;
|
||||
struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
|
||||
struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
|
||||
u32 tmp;
|
||||
|
||||
tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
|
||||
tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
|
||||
WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
|
||||
|
||||
tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
|
||||
tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
|
||||
WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
|
||||
|
||||
tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
|
||||
tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
|
||||
WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
|
||||
|
||||
tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
|
||||
tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
|
||||
tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
|
||||
tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
|
||||
tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
|
||||
tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
|
||||
tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
|
||||
WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
|
||||
|
||||
tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset);
|
||||
tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, 0xff);
|
||||
WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, tmp);
|
||||
|
||||
tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
|
||||
tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
|
||||
tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
|
||||
WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
|
||||
|
||||
tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
|
||||
tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_RESET_FIFO_WHEN_AUDIO_DIS, 1);
|
||||
tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
|
||||
WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
|
||||
}
|
||||
|
||||
static void dce_v6_0_audio_set_mute(struct drm_encoder *encoder, bool mute)
|
||||
{
|
||||
struct drm_device *dev = encoder->dev;
|
||||
struct amdgpu_device *adev = dev->dev_private;
|
||||
struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
|
||||
struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
|
||||
u32 tmp;
|
||||
|
||||
tmp = RREG32(mmHDMI_GC + dig->afmt->offset);
|
||||
tmp = REG_SET_FIELD(tmp, HDMI_GC, HDMI_GC_AVMUTE, mute ? 1 : 0);
|
||||
WREG32(mmHDMI_GC + dig->afmt->offset, tmp);
|
||||
}
|
||||
|
||||
static void dce_v6_0_audio_dp_enable(struct drm_encoder *encoder, bool enable)
|
||||
{
|
||||
struct drm_device *dev = encoder->dev;
|
||||
struct amdgpu_device *adev = dev->dev_private;
|
||||
struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
|
||||
struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
|
||||
u32 tmp;
|
||||
|
||||
if (enable) {
|
||||
tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
|
||||
tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
|
||||
WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
|
||||
|
||||
tmp = RREG32(mmDP_SEC_TIMESTAMP + dig->afmt->offset);
|
||||
tmp = REG_SET_FIELD(tmp, DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, 1);
|
||||
WREG32(mmDP_SEC_TIMESTAMP + dig->afmt->offset, tmp);
|
||||
|
||||
tmp = RREG32(mmDP_SEC_CNTL + dig->afmt->offset);
|
||||
tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);
|
||||
tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_ATP_ENABLE, 1);
|
||||
tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_AIP_ENABLE, 1);
|
||||
tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
|
||||
WREG32(mmDP_SEC_CNTL + dig->afmt->offset, tmp);
|
||||
} else {
|
||||
WREG32(mmDP_SEC_CNTL + dig->afmt->offset, 0);
|
||||
}
|
||||
}
|
||||
|
||||
static void dce_v6_0_afmt_setmode(struct drm_encoder *encoder,
|
||||
struct drm_display_mode *mode)
|
||||
{
|
||||
DRM_INFO("xxxx: dce_v6_0_afmt_setmode ----no impl !!!!!!!!\n");
|
||||
struct drm_device *dev = encoder->dev;
|
||||
struct amdgpu_device *adev = dev->dev_private;
|
||||
struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
|
||||
struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
|
||||
struct drm_connector *connector;
|
||||
struct amdgpu_connector *amdgpu_connector = NULL;
|
||||
|
||||
if (!dig || !dig->afmt)
|
||||
return;
|
||||
|
||||
list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
|
||||
if (connector->encoder == encoder) {
|
||||
amdgpu_connector = to_amdgpu_connector(connector);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (!amdgpu_connector) {
|
||||
DRM_ERROR("Couldn't find encoder's connector\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if (!dig->afmt->enabled)
|
||||
return;
|
||||
|
||||
dig->afmt->pin = dce_v6_0_audio_get_pin(adev);
|
||||
if (!dig->afmt->pin)
|
||||
return;
|
||||
|
||||
/* disable audio before setting up hw */
|
||||
dce_v6_0_audio_enable(adev, dig->afmt->pin, false);
|
||||
|
||||
dce_v6_0_audio_set_mute(encoder, true);
|
||||
dce_v6_0_audio_write_speaker_allocation(encoder);
|
||||
dce_v6_0_audio_write_sad_regs(encoder);
|
||||
dce_v6_0_audio_write_latency_fields(encoder, mode);
|
||||
dce_v6_0_audio_set_dto(encoder, adev->clock.default_dispclk * 10);
|
||||
dce_v6_0_audio_set_packet(encoder);
|
||||
dce_v6_0_audio_select_pin(encoder);
|
||||
dce_v6_0_audio_set_avi_infoframe(encoder, mode);
|
||||
dce_v6_0_audio_set_mute(encoder, false);
|
||||
dce_v6_0_audio_dp_enable(encoder, 1);
|
||||
|
||||
/* enable audio after setting up hw */
|
||||
dce_v6_0_audio_enable(adev, dig->afmt->pin, true);
|
||||
}
|
||||
|
||||
static void dce_v6_0_afmt_enable(struct drm_encoder *encoder, bool enable)
|
||||
@ -1359,6 +1751,7 @@ static void dce_v6_0_afmt_enable(struct drm_encoder *encoder, bool enable)
|
||||
/* Silent, r600_hdmi_enable will raise WARN for us */
|
||||
if (enable && dig->afmt->enabled)
|
||||
return;
|
||||
|
||||
if (!enable && !dig->afmt->enabled)
|
||||
return;
|
||||
|
||||
@ -2753,6 +3146,7 @@ dce_v6_0_encoder_mode_set(struct drm_encoder *encoder,
|
||||
{
|
||||
|
||||
struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
|
||||
int em = amdgpu_atombios_encoder_get_encoder_mode(encoder);
|
||||
|
||||
amdgpu_encoder->pixel_clock = adjusted_mode->clock;
|
||||
|
||||
@ -2762,7 +3156,7 @@ dce_v6_0_encoder_mode_set(struct drm_encoder *encoder,
|
||||
/* set scaler clears this on some chips */
|
||||
dce_v6_0_set_interleave(encoder->crtc, mode);
|
||||
|
||||
if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
|
||||
if (em == ATOM_ENCODER_MODE_HDMI || ENCODER_MODE_IS_DP(em)) {
|
||||
dce_v6_0_afmt_enable(encoder, true);
|
||||
dce_v6_0_afmt_setmode(encoder, adjusted_mode);
|
||||
}
|
||||
@ -2824,11 +3218,12 @@ static void dce_v6_0_encoder_disable(struct drm_encoder *encoder)
|
||||
|
||||
struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
|
||||
struct amdgpu_encoder_atom_dig *dig;
|
||||
int em = amdgpu_atombios_encoder_get_encoder_mode(encoder);
|
||||
|
||||
amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
|
||||
|
||||
if (amdgpu_atombios_encoder_is_digital(encoder)) {
|
||||
if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
|
||||
if (em == ATOM_ENCODER_MODE_HDMI || ENCODER_MODE_IS_DP(em))
|
||||
dce_v6_0_afmt_enable(encoder, false);
|
||||
dig = amdgpu_encoder->enc_priv;
|
||||
dig->dig_encoder = -1;
|
||||
|
||||
@ -906,6 +906,8 @@
|
||||
#define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x00000000
|
||||
#define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x000000ffL
|
||||
#define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x00000000
|
||||
#define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_WRITE_EN_MASK 0x00000100L
|
||||
#define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_WRITE_EN__SHIFT 0x00000008
|
||||
#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x0000003fL
|
||||
#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x00000000
|
||||
#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x00000200L
|
||||
|
||||
Loading…
Reference in New Issue
Block a user