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https://github.com/edk2-porting/linux-next.git
synced 2024-12-25 21:54:06 +08:00
Merge branch 'pci/host-imx6' into next
* pci/host-imx6: PCI: imx6: Fix bugs in PCIe startup code PCI: imx6: Start link in Gen1 before negotiating for Gen2 mode PCI: imx6: Factor out link up wait loop PCI: imx6: Factor out PHY reset PCI: imx6: Report "link up" only after link training completes PCI: imx6: Make reset-gpio optional
This commit is contained in:
Bjorn Helgaas
commit
4bd70bc997
@ -19,6 +19,8 @@ Required properties:
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to define the mapping of the PCIe interface to interrupt
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numbers.
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- num-lanes: number of lanes to use
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Optional properties:
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- reset-gpio: gpio pin number of power good signal
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Optional properties for fsl,imx6q-pcie
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@ -44,10 +44,18 @@ struct imx6_pcie {
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void __iomem *mem_base;
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};
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/* PCIe Root Complex registers (memory-mapped) */
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#define PCIE_RC_LCR 0x7c
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#define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1 0x1
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#define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2 0x2
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#define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK 0xf
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/* PCIe Port Logic registers (memory-mapped) */
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#define PL_OFFSET 0x700
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#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
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#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
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#define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING (1 << 29)
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#define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP (1 << 4)
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#define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
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#define PCIE_PHY_CTRL_DATA_LOC 0
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@ -59,6 +67,9 @@ struct imx6_pcie {
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#define PCIE_PHY_STAT (PL_OFFSET + 0x110)
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#define PCIE_PHY_STAT_ACK_LOC 16
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#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
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#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
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/* PHY registers (not memory-mapped) */
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#define PCIE_PHY_RX_ASIC_OUT 0x100D
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@ -209,15 +220,9 @@ static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
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IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
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IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
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IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
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gpio_set_value(imx6_pcie->reset_gpio, 0);
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msleep(100);
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gpio_set_value(imx6_pcie->reset_gpio, 1);
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return 0;
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}
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@ -261,6 +266,12 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
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/* allow the clocks to stabilize */
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usleep_range(200, 500);
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/* Some boards don't have PCIe reset GPIO. */
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if (gpio_is_valid(imx6_pcie->reset_gpio)) {
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gpio_set_value(imx6_pcie->reset_gpio, 0);
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msleep(100);
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gpio_set_value(imx6_pcie->reset_gpio, 1);
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}
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return 0;
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err_pcie_axi:
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@ -299,11 +310,90 @@ static void imx6_pcie_init_phy(struct pcie_port *pp)
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IMX6Q_GPR8_TX_SWING_LOW, 127 << 25);
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}
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static int imx6_pcie_wait_for_link(struct pcie_port *pp)
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{
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int count = 200;
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while (!dw_pcie_link_up(pp)) {
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usleep_range(100, 1000);
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if (--count)
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continue;
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dev_err(pp->dev, "phy link never came up\n");
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dev_dbg(pp->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
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readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
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readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
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return -EINVAL;
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}
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return 0;
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}
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static int imx6_pcie_start_link(struct pcie_port *pp)
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{
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struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
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uint32_t tmp;
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int ret, count;
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/*
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* Force Gen1 operation when starting the link. In case the link is
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* started in Gen2 mode, there is a possibility the devices on the
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* bus will not be detected at all. This happens with PCIe switches.
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*/
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tmp = readl(pp->dbi_base + PCIE_RC_LCR);
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tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
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tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1;
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writel(tmp, pp->dbi_base + PCIE_RC_LCR);
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/* Start LTSSM. */
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
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IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
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ret = imx6_pcie_wait_for_link(pp);
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if (ret)
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return ret;
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/* Allow Gen2 mode after the link is up. */
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tmp = readl(pp->dbi_base + PCIE_RC_LCR);
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tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
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tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2;
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writel(tmp, pp->dbi_base + PCIE_RC_LCR);
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/*
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* Start Directed Speed Change so the best possible speed both link
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* partners support can be negotiated.
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*/
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tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
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tmp |= PORT_LOGIC_SPEED_CHANGE;
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writel(tmp, pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
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count = 200;
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while (count--) {
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tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
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/* Test if the speed change finished. */
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if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
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break;
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usleep_range(100, 1000);
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}
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/* Make sure link training is finished as well! */
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if (count)
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ret = imx6_pcie_wait_for_link(pp);
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else
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ret = -EINVAL;
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if (ret) {
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dev_err(pp->dev, "Failed to bring link up!\n");
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} else {
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tmp = readl(pp->dbi_base + 0x80);
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dev_dbg(pp->dev, "Link up, Gen=%i\n", (tmp >> 16) & 0xf);
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}
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return ret;
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}
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static void imx6_pcie_host_init(struct pcie_port *pp)
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{
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int count = 0;
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struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
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imx6_pcie_assert_core_reset(pp);
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imx6_pcie_init_phy(pp);
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@ -312,33 +402,41 @@ static void imx6_pcie_host_init(struct pcie_port *pp)
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dw_pcie_setup_rc(pp);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
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IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
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imx6_pcie_start_link(pp);
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}
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while (!dw_pcie_link_up(pp)) {
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usleep_range(100, 1000);
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count++;
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if (count >= 200) {
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dev_err(pp->dev, "phy link never came up\n");
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dev_dbg(pp->dev,
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"DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
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readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
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readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
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break;
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}
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}
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static void imx6_pcie_reset_phy(struct pcie_port *pp)
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{
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uint32_t temp;
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return;
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pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
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temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN |
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PHY_RX_OVRD_IN_LO_RX_PLL_EN);
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pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, temp);
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usleep_range(2000, 3000);
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pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
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temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN |
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PHY_RX_OVRD_IN_LO_RX_PLL_EN);
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pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, temp);
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}
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static int imx6_pcie_link_up(struct pcie_port *pp)
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{
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u32 rc, ltssm, rx_valid, temp;
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u32 rc, ltssm, rx_valid;
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/* link is debug bit 36, debug register 1 starts at bit 32 */
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rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1) & (0x1 << (36 - 32));
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if (rc)
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return -EAGAIN;
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/*
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* Test if the PHY reports that the link is up and also that
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* the link training finished. It might happen that the PHY
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* reports the link is already up, but the link training bit
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* is still set, so make sure to check the training is done
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* as well here.
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*/
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rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);
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if ((rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_UP) &&
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!(rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING))
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return 1;
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/*
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* From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
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@ -358,21 +456,7 @@ static int imx6_pcie_link_up(struct pcie_port *pp)
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dev_err(pp->dev, "transition to gen2 is stuck, reset PHY!\n");
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pcie_phy_read(pp->dbi_base,
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PHY_RX_OVRD_IN_LO, &temp);
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temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN
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| PHY_RX_OVRD_IN_LO_RX_PLL_EN);
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pcie_phy_write(pp->dbi_base,
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PHY_RX_OVRD_IN_LO, temp);
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usleep_range(2000, 3000);
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pcie_phy_read(pp->dbi_base,
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PHY_RX_OVRD_IN_LO, &temp);
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temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN
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| PHY_RX_OVRD_IN_LO_RX_PLL_EN);
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pcie_phy_write(pp->dbi_base,
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PHY_RX_OVRD_IN_LO, temp);
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imx6_pcie_reset_phy(pp);
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return 0;
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}
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@ -432,17 +516,13 @@ static int __init imx6_pcie_probe(struct platform_device *pdev)
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/* Fetch GPIOs */
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imx6_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
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if (!gpio_is_valid(imx6_pcie->reset_gpio)) {
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dev_err(&pdev->dev, "no reset-gpio defined\n");
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ret = -ENODEV;
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}
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ret = devm_gpio_request_one(&pdev->dev,
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imx6_pcie->reset_gpio,
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GPIOF_OUT_INIT_LOW,
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"PCIe reset");
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if (ret) {
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dev_err(&pdev->dev, "unable to get reset gpio\n");
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return ret;
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if (gpio_is_valid(imx6_pcie->reset_gpio)) {
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ret = devm_gpio_request_one(&pdev->dev, imx6_pcie->reset_gpio,
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GPIOF_OUT_INIT_LOW, "PCIe reset");
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if (ret) {
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dev_err(&pdev->dev, "unable to get reset gpio\n");
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return ret;
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}
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}
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imx6_pcie->power_on_gpio = of_get_named_gpio(np, "power-on-gpio", 0);
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