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Merge branch 'bnxt_en-Updates-to-devlink-info_get-cb'
Vasundhara Volam says: ==================== bnxt_en: Updates to devlink info_get cb This series adds support for a generic macro to devlink info_get cb. Adds support for fw.mgmt.api and board.id info to bnxt_en driver info_get cb. Also, updates the devlink-info.rst and bnxt.rst documentation accordingly. This series adds a patch to fix few macro names that maps to bnxt_en firmware versions. v1->v2: Remove ECN dev param, base_mh_addr and serial number info support in this series. Rename drv.spec macro to fw.api. --- v2->v3: Remove hw.addr info as it is per netdev but not per device info. --- v3->v4: Rename "fw.api" to "fw.mgmt.api". Also, add a patch that modifies few macro names in info_get command, to match the devlink documentation. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
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commit
4bd27ee66d
@ -51,6 +51,9 @@ The ``bnxt_en`` driver reports the following versions
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* - Name
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- Type
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- Description
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* - ``board.id``
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- fixed
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- Part number identifying the board design
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* - ``asic.id``
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- fixed
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- ASIC design identifier
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@ -63,12 +66,15 @@ The ``bnxt_en`` driver reports the following versions
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* - ``fw``
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- stored, running
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- Overall board firmware version
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* - ``fw.app``
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- stored, running
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- Data path firmware version
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* - ``fw.mgmt``
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- stored, running
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- Management firmware version
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- NIC hardware resource management firmware version
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* - ``fw.mgmt.api``
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- running
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- Minimum firmware interface spec version supported between driver and firmware
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* - ``fw.nsci``
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- stored, running
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- General platform management firmware version
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* - ``fw.roce``
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- stored, running
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- RoCE management firmware version
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@ -157,6 +157,12 @@ Control unit firmware version. This firmware is responsible for house
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keeping tasks, PHY control etc. but not the packet-by-packet data path
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operation.
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fw.mgmt.api
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-----------
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Firmware interface specification version of the software interfaces between
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driver and firmware.
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fw.app
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------
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@ -7223,7 +7223,7 @@ static int __bnxt_hwrm_ver_get(struct bnxt *bp, bool silent)
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static int bnxt_hwrm_ver_get(struct bnxt *bp)
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{
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struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
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u32 dev_caps_cfg;
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u32 dev_caps_cfg, hwrm_ver;
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int rc;
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bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
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@ -7243,6 +7243,19 @@ static int bnxt_hwrm_ver_get(struct bnxt *bp)
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resp->hwrm_intf_upd_8b);
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netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
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}
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hwrm_ver = HWRM_VERSION_MAJOR << 16 | HWRM_VERSION_MINOR << 8 |
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HWRM_VERSION_UPDATE;
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if (bp->hwrm_spec_code > hwrm_ver)
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snprintf(bp->hwrm_ver_supp, FW_VER_STR_LEN, "%d.%d.%d",
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HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR,
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HWRM_VERSION_UPDATE);
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else
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snprintf(bp->hwrm_ver_supp, FW_VER_STR_LEN, "%d.%d.%d",
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resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
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resp->hwrm_intf_upd_8b);
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snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d.%d",
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resp->hwrm_fw_maj_8b, resp->hwrm_fw_min_8b,
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resp->hwrm_fw_bld_8b, resp->hwrm_fw_rsvd_8b);
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@ -11739,6 +11752,63 @@ static int bnxt_init_mac_addr(struct bnxt *bp)
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return rc;
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}
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#define BNXT_VPD_LEN 512
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static void bnxt_vpd_read_info(struct bnxt *bp)
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{
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struct pci_dev *pdev = bp->pdev;
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int i, len, pos, ro_size;
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ssize_t vpd_size;
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u8 *vpd_data;
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vpd_data = kmalloc(BNXT_VPD_LEN, GFP_KERNEL);
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if (!vpd_data)
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return;
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vpd_size = pci_read_vpd(pdev, 0, BNXT_VPD_LEN, vpd_data);
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if (vpd_size <= 0) {
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netdev_err(bp->dev, "Unable to read VPD\n");
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goto exit;
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}
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i = pci_vpd_find_tag(vpd_data, 0, vpd_size, PCI_VPD_LRDT_RO_DATA);
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if (i < 0) {
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netdev_err(bp->dev, "VPD READ-Only not found\n");
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goto exit;
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}
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ro_size = pci_vpd_lrdt_size(&vpd_data[i]);
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i += PCI_VPD_LRDT_TAG_SIZE;
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if (i + ro_size > vpd_size)
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goto exit;
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pos = pci_vpd_find_info_keyword(vpd_data, i, ro_size,
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PCI_VPD_RO_KEYWORD_PARTNO);
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if (pos < 0)
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goto read_sn;
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len = pci_vpd_info_field_size(&vpd_data[pos]);
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pos += PCI_VPD_INFO_FLD_HDR_SIZE;
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if (len + pos > vpd_size)
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goto read_sn;
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strlcpy(bp->board_partno, &vpd_data[pos], min(len, BNXT_VPD_FLD_LEN));
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read_sn:
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pos = pci_vpd_find_info_keyword(vpd_data, i, ro_size,
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PCI_VPD_RO_KEYWORD_SERIALNO);
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if (pos < 0)
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goto exit;
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len = pci_vpd_info_field_size(&vpd_data[pos]);
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pos += PCI_VPD_INFO_FLD_HDR_SIZE;
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if (len + pos > vpd_size)
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goto exit;
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strlcpy(bp->board_serialno, &vpd_data[pos], min(len, BNXT_VPD_FLD_LEN));
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exit:
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kfree(vpd_data);
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}
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static int bnxt_pcie_dsn_get(struct bnxt *bp, u8 dsn[])
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{
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struct pci_dev *pdev = bp->pdev;
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@ -11796,6 +11866,8 @@ static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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dev->ethtool_ops = &bnxt_ethtool_ops;
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pci_set_drvdata(pdev, dev);
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bnxt_vpd_read_info(bp);
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rc = bnxt_alloc_hwrm_resources(bp);
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if (rc)
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goto init_err_pci_clean;
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@ -1500,6 +1500,10 @@ struct bnxt {
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(chip_num) == CHIP_NUM_58804 || \
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(chip_num) == CHIP_NUM_58808)
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#define BNXT_VPD_FLD_LEN 32
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char board_partno[BNXT_VPD_FLD_LEN];
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char board_serialno[BNXT_VPD_FLD_LEN];
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struct net_device *dev;
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struct pci_dev *pdev;
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@ -1730,6 +1734,7 @@ struct bnxt {
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#define BC_HWRM_STR_LEN 21
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#define PHY_VER_STR_LEN (FW_VER_STR_LEN - BC_HWRM_STR_LEN)
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char fw_ver_str[FW_VER_STR_LEN];
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char hwrm_ver_supp[FW_VER_STR_LEN];
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__be16 vxlan_port;
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u8 vxlan_port_cnt;
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__le16 vxlan_fw_dst_port_id;
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@ -403,6 +403,14 @@ static int bnxt_dl_info_get(struct devlink *dl, struct devlink_info_req *req,
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if (rc)
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return rc;
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if (strlen(bp->board_partno)) {
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rc = devlink_info_version_fixed_put(req,
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DEVLINK_INFO_VERSION_GENERIC_BOARD_ID,
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bp->board_partno);
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if (rc)
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return rc;
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}
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sprintf(buf, "%X", bp->chip_num);
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rc = devlink_info_version_fixed_put(req,
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DEVLINK_INFO_VERSION_GENERIC_ASIC_ID, buf);
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@ -471,13 +479,19 @@ static int bnxt_dl_info_get(struct devlink *dl, struct devlink_info_req *req,
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ver_resp->roce_fw_bld_8b, ver_resp->roce_fw_rsvd_8b);
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}
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rc = devlink_info_version_running_put(req,
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DEVLINK_INFO_VERSION_GENERIC_FW_APP, fw_ver);
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DEVLINK_INFO_VERSION_GENERIC_FW_MGMT, fw_ver);
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if (rc)
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return rc;
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rc = devlink_info_version_running_put(req,
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DEVLINK_INFO_VERSION_GENERIC_FW_MGMT_API,
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bp->hwrm_ver_supp);
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if (rc)
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return rc;
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if (!(bp->flags & BNXT_FLAG_CHIP_P5)) {
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rc = devlink_info_version_running_put(req,
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DEVLINK_INFO_VERSION_GENERIC_FW_MGMT, mgmt_ver);
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DEVLINK_INFO_VERSION_GENERIC_FW_NCSI, mgmt_ver);
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if (rc)
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return rc;
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@ -2184,6 +2184,7 @@ int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
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#define PCI_VPD_INFO_FLD_HDR_SIZE 3
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#define PCI_VPD_RO_KEYWORD_PARTNO "PN"
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#define PCI_VPD_RO_KEYWORD_SERIALNO "SN"
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#define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
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#define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
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#define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
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@ -481,6 +481,8 @@ enum devlink_param_generic_id {
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#define DEVLINK_INFO_VERSION_GENERIC_FW "fw"
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/* Control processor FW version */
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#define DEVLINK_INFO_VERSION_GENERIC_FW_MGMT "fw.mgmt"
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/* FW interface specification version */
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#define DEVLINK_INFO_VERSION_GENERIC_FW_MGMT_API "fw.mgmt.api"
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/* Data path microcode controlling high-speed packet processing */
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#define DEVLINK_INFO_VERSION_GENERIC_FW_APP "fw.app"
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/* UNDI software version */
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