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i2c: mlxbf: Remove unecessary wrapper functions
Few wrapper functions are useless and can be inlined. So
delete mlxbf_i2c_read() and mlxbf_i2c_write() and replace
them with readl() and writel(), respectively. Also delete
mlxbf_i2c_read_data() and mlxbf_i2c_write() and replace
them with ioread32be() and iowrite32be(), respectively.
Fixes: b5b5b32081 ("i2c: mlxbf: I2C SMBus driver for Mellanox BlueField SoC")
Reviewed-by: Leon Romanovsky <leonro@nvidia.com>
Reviewed-by: Vadim Pasternak <vadimp@nvidia.com>
Signed-off-by: Khalil Blaiech <kblaiech@nvidia.com>
Signed-off-by: Wolfram Sang <wsa@kernel.org>
This commit is contained in:
Khalil Blaiech
Wolfram Sang
parent
08e019e27a
commit
4b19d806ac
@ -489,44 +489,6 @@ static struct mutex mlxbf_i2c_bus_lock;
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#define MLXBF_I2C_FREQUENCY_1GHZ 1000000000
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static void mlxbf_i2c_write(void __iomem *io, int reg, u32 val)
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{
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writel(val, io + reg);
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}
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static u32 mlxbf_i2c_read(void __iomem *io, int reg)
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{
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return readl(io + reg);
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}
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/*
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* This function is used to read data from Master GW Data Descriptor.
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* Data bytes in the Master GW Data Descriptor are shifted left so the
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* data starts at the MSB of the descriptor registers as set by the
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* underlying hardware. TYU_READ_DATA enables byte swapping while
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* reading data bytes, and MUST be called by the SMBus read routines
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* to copy data from the 32 * 32-bit HW Data registers a.k.a Master GW
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* Data Descriptor.
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*/
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static u32 mlxbf_i2c_read_data(void __iomem *io, int reg)
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{
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return ioread32be(io + reg);
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}
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/*
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* This function is used to write data to the Master GW Data Descriptor.
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* Data copied to the Master GW Data Descriptor MUST be shifted left so
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* the data starts at the MSB of the descriptor registers as required by
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* the underlying hardware. TYU_WRITE_DATA enables byte swapping when
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* writing data bytes, and MUST be called by the SMBus write routines to
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* copy data to the 32 * 32-bit HW Data registers a.k.a Master GW Data
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* Descriptor.
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*/
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static void mlxbf_i2c_write_data(void __iomem *io, int reg, u32 val)
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{
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iowrite32be(val, io + reg);
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}
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/*
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* Function to poll a set of bits at a specific address; it checks whether
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* the bits are equal to zero when eq_zero is set to 'true', and not equal
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@ -541,7 +503,7 @@ static u32 mlxbf_smbus_poll(void __iomem *io, u32 addr, u32 mask,
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timeout = (timeout / MLXBF_I2C_POLL_FREQ_IN_USEC) + 1;
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do {
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bits = mlxbf_i2c_read(io, addr) & mask;
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bits = readl(io + addr) & mask;
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if (eq_zero ? bits == 0 : bits != 0)
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return eq_zero ? 1 : bits;
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udelay(MLXBF_I2C_POLL_FREQ_IN_USEC);
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@ -609,16 +571,16 @@ static int mlxbf_i2c_smbus_check_status(struct mlxbf_i2c_priv *priv)
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MLXBF_I2C_SMBUS_TIMEOUT);
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/* Read cause status bits. */
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cause_status_bits = mlxbf_i2c_read(priv->mst_cause->io,
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MLXBF_I2C_CAUSE_ARBITER);
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cause_status_bits = readl(priv->mst_cause->io +
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MLXBF_I2C_CAUSE_ARBITER);
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cause_status_bits &= MLXBF_I2C_CAUSE_MASTER_ARBITER_BITS_MASK;
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/*
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* Parse both Cause and Master GW bits, then return transaction status.
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*/
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master_status_bits = mlxbf_i2c_read(priv->smbus->io,
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MLXBF_I2C_SMBUS_MASTER_STATUS);
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master_status_bits = readl(priv->smbus->io +
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MLXBF_I2C_SMBUS_MASTER_STATUS);
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master_status_bits &= MLXBF_I2C_SMBUS_MASTER_STATUS_MASK;
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if (mlxbf_i2c_smbus_transaction_success(master_status_bits,
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@ -649,10 +611,17 @@ static void mlxbf_i2c_smbus_write_data(struct mlxbf_i2c_priv *priv,
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aligned_length = round_up(length, 4);
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/* Copy data bytes from 4-byte aligned source buffer. */
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/*
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* Copy data bytes from 4-byte aligned source buffer.
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* Data copied to the Master GW Data Descriptor MUST be shifted
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* left so the data starts at the MSB of the descriptor registers
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* as required by the underlying hardware. Enable byte swapping
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* when writing data bytes to the 32 * 32-bit HW Data registers
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* a.k.a Master GW Data Descriptor.
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*/
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for (offset = 0; offset < aligned_length; offset += sizeof(u32)) {
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data32 = *((u32 *)(data + offset));
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mlxbf_i2c_write_data(priv->smbus->io, addr + offset, data32);
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iowrite32be(data32, priv->smbus->io + addr + offset);
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}
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}
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@ -664,15 +633,23 @@ static void mlxbf_i2c_smbus_read_data(struct mlxbf_i2c_priv *priv,
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mask = sizeof(u32) - 1;
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/*
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* Data bytes in the Master GW Data Descriptor are shifted left
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* so the data starts at the MSB of the descriptor registers as
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* set by the underlying hardware. Enable byte swapping while
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* reading data bytes from the 32 * 32-bit HW Data registers
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* a.k.a Master GW Data Descriptor.
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*/
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for (offset = 0; offset < (length & ~mask); offset += sizeof(u32)) {
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data32 = mlxbf_i2c_read_data(priv->smbus->io, addr + offset);
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data32 = ioread32be(priv->smbus->io + addr + offset);
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*((u32 *)(data + offset)) = data32;
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}
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if (!(length & mask))
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return;
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data32 = mlxbf_i2c_read_data(priv->smbus->io, addr + offset);
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data32 = ioread32be(priv->smbus->io + addr + offset);
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for (byte = 0; byte < (length & mask); byte++) {
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data[offset + byte] = data32 & GENMASK(7, 0);
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@ -698,16 +675,16 @@ static int mlxbf_i2c_smbus_enable(struct mlxbf_i2c_priv *priv, u8 slave,
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command |= rol32(pec_en, MLXBF_I2C_MASTER_SEND_PEC_SHIFT);
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/* Clear status bits. */
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mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_MASTER_STATUS, 0x0);
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writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_STATUS);
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/* Set the cause data. */
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mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_CAUSE_OR_CLEAR, ~0x0);
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writel(~0x0, priv->smbus->io + MLXBF_I2C_CAUSE_OR_CLEAR);
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/* Zero PEC byte. */
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mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_MASTER_PEC, 0x0);
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writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_PEC);
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/* Zero byte count. */
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mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_RS_BYTES, 0x0);
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writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_RS_BYTES);
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/* GW activation. */
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mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_MASTER_GW, command);
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writel(command, priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_GW);
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/*
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* Poll master status and check status bits. An ACK is sent when
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@ -823,8 +800,8 @@ mlxbf_i2c_smbus_start_transaction(struct mlxbf_i2c_priv *priv,
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* needs to be 'manually' reset. This should be removed in
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* next tag integration.
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*/
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mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_MASTER_FSM,
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MLXBF_I2C_SMBUS_MASTER_FSM_PS_STATE_MASK);
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writel(MLXBF_I2C_SMBUS_MASTER_FSM_PS_STATE_MASK,
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priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_FSM);
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}
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return ret;
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@ -1113,8 +1090,8 @@ static void mlxbf_i2c_set_timings(struct mlxbf_i2c_priv *priv,
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timer |= mlxbf_i2c_set_timer(priv, timings->scl_low,
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false, MLXBF_I2C_MASK_16,
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MLXBF_I2C_SHIFT_16);
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mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_TIMER_SCL_LOW_SCL_HIGH,
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timer);
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writel(timer, priv->smbus->io +
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MLXBF_I2C_SMBUS_TIMER_SCL_LOW_SCL_HIGH);
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timer = mlxbf_i2c_set_timer(priv, timings->sda_rise, false,
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MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_0);
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@ -1124,37 +1101,34 @@ static void mlxbf_i2c_set_timings(struct mlxbf_i2c_priv *priv,
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MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_16);
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timer |= mlxbf_i2c_set_timer(priv, timings->scl_fall, false,
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MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_24);
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mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_TIMER_FALL_RISE_SPIKE,
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timer);
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writel(timer, priv->smbus->io +
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MLXBF_I2C_SMBUS_TIMER_FALL_RISE_SPIKE);
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timer = mlxbf_i2c_set_timer(priv, timings->hold_start, true,
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MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0);
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timer |= mlxbf_i2c_set_timer(priv, timings->hold_data, true,
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MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16);
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mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_TIMER_THOLD, timer);
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writel(timer, priv->smbus->io + MLXBF_I2C_SMBUS_TIMER_THOLD);
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timer = mlxbf_i2c_set_timer(priv, timings->setup_start, true,
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MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0);
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timer |= mlxbf_i2c_set_timer(priv, timings->setup_stop, true,
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MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16);
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mlxbf_i2c_write(priv->smbus->io,
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MLXBF_I2C_SMBUS_TIMER_TSETUP_START_STOP, timer);
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writel(timer, priv->smbus->io +
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MLXBF_I2C_SMBUS_TIMER_TSETUP_START_STOP);
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timer = mlxbf_i2c_set_timer(priv, timings->setup_data, true,
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MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0);
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mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_TIMER_TSETUP_DATA,
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timer);
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writel(timer, priv->smbus->io + MLXBF_I2C_SMBUS_TIMER_TSETUP_DATA);
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timer = mlxbf_i2c_set_timer(priv, timings->buf, false,
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MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0);
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timer |= mlxbf_i2c_set_timer(priv, timings->thigh_max, false,
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MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16);
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mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_THIGH_MAX_TBUF,
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timer);
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writel(timer, priv->smbus->io + MLXBF_I2C_SMBUS_THIGH_MAX_TBUF);
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timer = timings->timeout;
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mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_SCL_LOW_TIMEOUT,
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timer);
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writel(timer, priv->smbus->io + MLXBF_I2C_SMBUS_SCL_LOW_TIMEOUT);
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}
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enum mlxbf_i2c_timings_config {
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@ -1426,19 +1400,15 @@ static int mlxbf_i2c_init_master(struct platform_device *pdev,
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* platform firmware; disabling the bus might compromise the system
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* functionality.
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*/
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config_reg = mlxbf_i2c_read(gpio_res->io,
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MLXBF_I2C_GPIO_0_FUNC_EN_0);
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config_reg = readl(gpio_res->io + MLXBF_I2C_GPIO_0_FUNC_EN_0);
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config_reg = MLXBF_I2C_GPIO_SMBUS_GW_ASSERT_PINS(priv->bus,
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config_reg);
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mlxbf_i2c_write(gpio_res->io, MLXBF_I2C_GPIO_0_FUNC_EN_0,
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config_reg);
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writel(config_reg, gpio_res->io + MLXBF_I2C_GPIO_0_FUNC_EN_0);
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config_reg = mlxbf_i2c_read(gpio_res->io,
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MLXBF_I2C_GPIO_0_FORCE_OE_EN);
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config_reg = readl(gpio_res->io + MLXBF_I2C_GPIO_0_FORCE_OE_EN);
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config_reg = MLXBF_I2C_GPIO_SMBUS_GW_RESET_PINS(priv->bus,
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config_reg);
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mlxbf_i2c_write(gpio_res->io, MLXBF_I2C_GPIO_0_FORCE_OE_EN,
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config_reg);
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writel(config_reg, gpio_res->io + MLXBF_I2C_GPIO_0_FORCE_OE_EN);
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mutex_unlock(gpio_res->lock);
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@ -1454,8 +1424,7 @@ static u64 mlxbf_calculate_freq_from_tyu(struct mlxbf_i2c_resource *corepll_res)
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pad_frequency = MLXBF_I2C_TYU_PLL_IN_FREQ;
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corepll_val = mlxbf_i2c_read(corepll_res->io,
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MLXBF_I2C_CORE_PLL_REG1);
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corepll_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG1);
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/* Get Core PLL configuration bits. */
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core_f = rol32(corepll_val, MLXBF_I2C_COREPLL_CORE_F_TYU_SHIFT) &
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@ -1490,10 +1459,8 @@ static u64 mlxbf_calculate_freq_from_yu(struct mlxbf_i2c_resource *corepll_res)
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pad_frequency = MLXBF_I2C_YU_PLL_IN_FREQ;
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corepll_reg1_val = mlxbf_i2c_read(corepll_res->io,
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MLXBF_I2C_CORE_PLL_REG1);
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corepll_reg2_val = mlxbf_i2c_read(corepll_res->io,
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MLXBF_I2C_CORE_PLL_REG2);
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corepll_reg1_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG1);
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corepll_reg2_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG2);
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/* Get Core PLL configuration bits */
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core_f = rol32(corepll_reg1_val, MLXBF_I2C_COREPLL_CORE_F_YU_SHIFT) &
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@ -1585,7 +1552,7 @@ static int mlxbf_slave_enable(struct mlxbf_i2c_priv *priv, u8 addr)
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* (7-bit address, 1 status bit (1 if enabled, 0 if not)).
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*/
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for (reg = 0; reg < reg_cnt; reg++) {
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slave_reg = mlxbf_i2c_read(priv->smbus->io,
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slave_reg = readl(priv->smbus->io +
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MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + reg * 0x4);
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/*
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* Each register holds 4 slave addresses. So, we have to keep
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@ -1643,8 +1610,8 @@ static int mlxbf_slave_enable(struct mlxbf_i2c_priv *priv, u8 addr)
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/* Enable the slave address and update the register. */
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slave_reg |= (1 << MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT) << (byte * 8);
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mlxbf_i2c_write(priv->smbus->io,
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MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + reg * 0x4, slave_reg);
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writel(slave_reg, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG +
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reg * 0x4);
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return 0;
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}
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@ -1668,7 +1635,7 @@ static int mlxbf_slave_disable(struct mlxbf_i2c_priv *priv)
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* (7-bit address, 1 status bit (1 if enabled, 0 if not)).
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*/
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for (reg = 0; reg < reg_cnt; reg++) {
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slave_reg = mlxbf_i2c_read(priv->smbus->io,
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slave_reg = readl(priv->smbus->io +
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MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + reg * 0x4);
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/* Check whether the address slots are empty. */
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@ -1708,8 +1675,8 @@ static int mlxbf_slave_disable(struct mlxbf_i2c_priv *priv)
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/* Cleanup the slave address slot. */
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slave_reg &= ~(GENMASK(7, 0) << (slave_byte * 8));
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mlxbf_i2c_write(priv->smbus->io,
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MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + reg * 0x4, slave_reg);
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writel(slave_reg, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG +
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reg * 0x4);
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return 0;
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}
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@ -1801,7 +1768,7 @@ static int mlxbf_i2c_init_slave(struct platform_device *pdev,
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int ret;
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/* Reset FSM. */
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mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_SLAVE_FSM, 0);
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writel(0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_FSM);
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/*
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* Enable slave cause interrupt bits. Drive
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@ -1810,15 +1777,13 @@ static int mlxbf_i2c_init_slave(struct platform_device *pdev,
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* masters issue a Read and Write, respectively. But, clear all
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* interrupts first.
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*/
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mlxbf_i2c_write(priv->slv_cause->io,
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MLXBF_I2C_CAUSE_OR_CLEAR, ~0);
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writel(~0, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_CLEAR);
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int_reg = MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE;
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int_reg |= MLXBF_I2C_CAUSE_WRITE_SUCCESS;
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mlxbf_i2c_write(priv->slv_cause->io,
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MLXBF_I2C_CAUSE_OR_EVTEN0, int_reg);
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writel(int_reg, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_EVTEN0);
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/* Finally, set the 'ready' bit to start handling transactions. */
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mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_SLAVE_READY, 0x1);
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||||
writel(0x1, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_READY);
|
||||
|
||||
/* Initialize the cause coalesce resource. */
|
||||
ret = mlxbf_i2c_init_coalesce(pdev, priv);
|
||||
@ -1844,23 +1809,21 @@ static bool mlxbf_i2c_has_coalesce(struct mlxbf_i2c_priv *priv, bool *read,
|
||||
MLXBF_I2C_CAUSE_YU_SLAVE_BIT :
|
||||
priv->bus + MLXBF_I2C_CAUSE_TYU_SLAVE_BIT;
|
||||
|
||||
coalesce0_reg = mlxbf_i2c_read(priv->coalesce->io,
|
||||
MLXBF_I2C_CAUSE_COALESCE_0);
|
||||
coalesce0_reg = readl(priv->coalesce->io + MLXBF_I2C_CAUSE_COALESCE_0);
|
||||
is_set = coalesce0_reg & (1 << slave_shift);
|
||||
|
||||
if (!is_set)
|
||||
return false;
|
||||
|
||||
/* Check the source of the interrupt, i.e. whether a Read or Write. */
|
||||
cause_reg = mlxbf_i2c_read(priv->slv_cause->io,
|
||||
MLXBF_I2C_CAUSE_ARBITER);
|
||||
cause_reg = readl(priv->slv_cause->io + MLXBF_I2C_CAUSE_ARBITER);
|
||||
if (cause_reg & MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE)
|
||||
*read = true;
|
||||
else if (cause_reg & MLXBF_I2C_CAUSE_WRITE_SUCCESS)
|
||||
*write = true;
|
||||
|
||||
/* Clear cause bits. */
|
||||
mlxbf_i2c_write(priv->slv_cause->io, MLXBF_I2C_CAUSE_OR_CLEAR, ~0x0);
|
||||
writel(~0x0, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_CLEAR);
|
||||
|
||||
return true;
|
||||
}
|
||||
@ -1900,8 +1863,8 @@ static int mlxbf_smbus_irq_send(struct mlxbf_i2c_priv *priv, u8 recv_bytes)
|
||||
* address, if supplied.
|
||||
*/
|
||||
if (recv_bytes > 0) {
|
||||
data32 = mlxbf_i2c_read_data(priv->smbus->io,
|
||||
MLXBF_I2C_SLAVE_DATA_DESC_ADDR);
|
||||
data32 = ioread32be(priv->smbus->io +
|
||||
MLXBF_I2C_SLAVE_DATA_DESC_ADDR);
|
||||
|
||||
/* Parse the received bytes. */
|
||||
switch (recv_bytes) {
|
||||
@ -1966,7 +1929,7 @@ static int mlxbf_smbus_irq_send(struct mlxbf_i2c_priv *priv, u8 recv_bytes)
|
||||
control32 |= rol32(write_size, MLXBF_I2C_SLAVE_WRITE_BYTES_SHIFT);
|
||||
control32 |= rol32(pec_en, MLXBF_I2C_SLAVE_SEND_PEC_SHIFT);
|
||||
|
||||
mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_SLAVE_GW, control32);
|
||||
writel(control32, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_GW);
|
||||
|
||||
/*
|
||||
* Wait until the transfer is completed; the driver will wait
|
||||
@ -1975,10 +1938,9 @@ static int mlxbf_smbus_irq_send(struct mlxbf_i2c_priv *priv, u8 recv_bytes)
|
||||
mlxbf_smbus_slave_wait_for_idle(priv, MLXBF_I2C_SMBUS_TIMEOUT);
|
||||
|
||||
/* Release the Slave GW. */
|
||||
mlxbf_i2c_write(priv->smbus->io,
|
||||
MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES, 0x0);
|
||||
mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_SLAVE_PEC, 0x0);
|
||||
mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_SLAVE_READY, 0x1);
|
||||
writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES);
|
||||
writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_PEC);
|
||||
writel(0x1, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_READY);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -2023,10 +1985,9 @@ static int mlxbf_smbus_irq_recv(struct mlxbf_i2c_priv *priv, u8 recv_bytes)
|
||||
i2c_slave_event(slave, I2C_SLAVE_STOP, &value);
|
||||
|
||||
/* Release the Slave GW. */
|
||||
mlxbf_i2c_write(priv->smbus->io,
|
||||
MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES, 0x0);
|
||||
mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_SLAVE_PEC, 0x0);
|
||||
mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_SLAVE_READY, 0x1);
|
||||
writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES);
|
||||
writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_PEC);
|
||||
writel(0x1, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_READY);
|
||||
|
||||
return ret;
|
||||
}
|
||||
@ -2061,8 +2022,8 @@ static irqreturn_t mlxbf_smbus_irq(int irq, void *ptr)
|
||||
* slave, if the higher 8 bits are sent then the slave expect N bytes
|
||||
* from the master.
|
||||
*/
|
||||
rw_bytes_reg = mlxbf_i2c_read(priv->smbus->io,
|
||||
MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES);
|
||||
rw_bytes_reg = readl(priv->smbus->io +
|
||||
MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES);
|
||||
recv_bytes = (rw_bytes_reg >> 8) & GENMASK(7, 0);
|
||||
|
||||
/*
|
||||
|
||||
Loading…
Reference in New Issue
Block a user