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ACPICA: IORT: Add in support for the SMMUv3 subtable
ACPICA commit 9f7c3e148f440049615e2791d73b292f65692d7e The most recent version of the IORT specification adds in a definition for a subtable to describe SMMUv3 devices; there is already a subtable for SMMUv1/v2 devices. Add in the definition of the subtable, add in the code to compile it, and add in a template for it. Link: https://github.com/acpica/acpica/commit/9f7c3e14 Signed-off-by: Al Stone <ahs3@redhat.com> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Lv Zheng <lv.zheng@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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@ -660,7 +660,7 @@ struct acpi_ibft_target {
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* IORT - IO Remapping Table
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*
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* Conforms to "IO Remapping Table System Software on ARM Platforms",
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* Document number: ARM DEN 0049A, 2015
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* Document number: ARM DEN 0049B, October 2015
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*
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******************************************************************************/
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@ -690,7 +690,8 @@ enum acpi_iort_node_type {
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ACPI_IORT_NODE_ITS_GROUP = 0x00,
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ACPI_IORT_NODE_NAMED_COMPONENT = 0x01,
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ACPI_IORT_NODE_PCI_ROOT_COMPLEX = 0x02,
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ACPI_IORT_NODE_SMMU = 0x03
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ACPI_IORT_NODE_SMMU = 0x03,
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ACPI_IORT_NODE_SMMU_V3 = 0x04
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};
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struct acpi_iort_id_mapping {
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@ -780,6 +781,23 @@ struct acpi_iort_smmu {
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#define ACPI_IORT_SMMU_DVM_SUPPORTED (1)
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#define ACPI_IORT_SMMU_COHERENT_WALK (1<<1)
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struct acpi_iort_smmu_v3 {
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u64 base_address; /* SMMUv3 base address */
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u32 flags;
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u32 reserved;
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u64 vatos_address;
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u32 model; /* O: generic SMMUv3 */
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u32 event_gsiv;
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u32 pri_gsiv;
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u32 gerr_gsiv;
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u32 sync_gsiv;
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};
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/* Masks for Flags field above */
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#define ACPI_IORT_SMMU_V3_COHACC_OVERRIDE (1)
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#define ACPI_IORT_SMMU_V3_HTTU_OVERRIDE (1<<1)
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/*******************************************************************************
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*
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* IVRS - I/O Virtualization Reporting Structure
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