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Code

drm/nouveau/i2c: convert to new-style nvkm_subdev

Browse Source 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2015-08-20 14:54:20 +10:00
parent 2ea7249fe2
commit 49bd8da513
23 changed files with 200 additions and 327 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/nouveau/include/nvif/device.h
View File

@ -56,7 +56,7 @@ u64 nvif_device_time(struct nvif_device *);
#define nvxx_bar(a) nvxx_device(a)->bar
#define nvxx_gpio(a) nvxx_device(a)->gpio
#define nvxx_clk(a) nvxx_device(a)->clk
#define nvxx_i2c(a) nvkm_i2c(nvxx_device(a))
#define nvxx_i2c(a) nvxx_device(a)->i2c
#define nvxx_therm(a) nvkm_therm(nvxx_device(a))
#include <core/device.h>

26
drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h
View File

@ -69,31 +69,27 @@ int nvkm_i2c_aux_lnk_ctl(struct nvkm_i2c_aux *, int link_nr, int link_bw,
bool enhanced_framing);
struct nvkm_i2c {
const struct nvkm_i2c_func *func;
struct nvkm_subdev subdev;
struct nvkm_event event;
struct list_head pad;
struct list_head bus;
struct list_head aux;
struct nvkm_event event;
};
struct nvkm_i2c_bus *nvkm_i2c_bus_find(struct nvkm_i2c *, int);
struct nvkm_i2c_aux *nvkm_i2c_aux_find(struct nvkm_i2c *, int);
static inline struct nvkm_i2c *
nvkm_i2c(void *obj)
{
return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_I2C);
}
extern struct nvkm_oclass *nv04_i2c_oclass;
extern struct nvkm_oclass *nv4e_i2c_oclass;
extern struct nvkm_oclass *nv50_i2c_oclass;
extern struct nvkm_oclass *g94_i2c_oclass;
extern struct nvkm_oclass *gf110_i2c_oclass;
extern struct nvkm_oclass *gf117_i2c_oclass;
extern struct nvkm_oclass *gk104_i2c_oclass;
extern struct nvkm_oclass *gm204_i2c_oclass;
int nv04_i2c_new(struct nvkm_device *, int, struct nvkm_i2c **);
int nv4e_i2c_new(struct nvkm_device *, int, struct nvkm_i2c **);
int nv50_i2c_new(struct nvkm_device *, int, struct nvkm_i2c **);
int g94_i2c_new(struct nvkm_device *, int, struct nvkm_i2c **);
int gf117_i2c_new(struct nvkm_device *, int, struct nvkm_i2c **);
int gf119_i2c_new(struct nvkm_device *, int, struct nvkm_i2c **);
int gk104_i2c_new(struct nvkm_device *, int, struct nvkm_i2c **);
int gm204_i2c_new(struct nvkm_device *, int, struct nvkm_i2c **);
static inline int
nvkm_rdi2cr(struct i2c_adapter *adap, u8 addr, u8 reg)

134
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
View File

@ -81,7 +81,7 @@ nv4_chipset = {
.clk = nv04_clk_new,
.devinit = nv04_devinit_new,
.fb = nv04_fb_new,
// .i2c = nv04_i2c_new,
.i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
@ -101,7 +101,7 @@ nv5_chipset = {
.clk = nv04_clk_new,
.devinit = nv05_devinit_new,
.fb = nv04_fb_new,
// .i2c = nv04_i2c_new,
.i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
@ -122,7 +122,7 @@ nv10_chipset = {
.devinit = nv10_devinit_new,
.fb = nv10_fb_new,
.gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
.i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
@ -141,7 +141,7 @@ nv11_chipset = {
.devinit = nv10_devinit_new,
.fb = nv10_fb_new,
.gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
.i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
@ -162,7 +162,7 @@ nv15_chipset = {
.devinit = nv10_devinit_new,
.fb = nv10_fb_new,
.gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
.i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
@ -183,7 +183,7 @@ nv17_chipset = {
.devinit = nv10_devinit_new,
.fb = nv10_fb_new,
.gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
.i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
@ -204,7 +204,7 @@ nv18_chipset = {
.devinit = nv10_devinit_new,
.fb = nv10_fb_new,
.gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
.i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
@ -225,7 +225,7 @@ nv1a_chipset = {
.devinit = nv1a_devinit_new,
.fb = nv1a_fb_new,
.gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
.i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
@ -246,7 +246,7 @@ nv1f_chipset = {
.devinit = nv1a_devinit_new,
.fb = nv1a_fb_new,
.gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
.i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
@ -267,7 +267,7 @@ nv20_chipset = {
.devinit = nv20_devinit_new,
.fb = nv20_fb_new,
.gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
.i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
@ -288,7 +288,7 @@ nv25_chipset = {
.devinit = nv20_devinit_new,
.fb = nv25_fb_new,
.gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
.i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
@ -309,7 +309,7 @@ nv28_chipset = {
.devinit = nv20_devinit_new,
.fb = nv25_fb_new,
.gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
.i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
@ -330,7 +330,7 @@ nv2a_chipset = {
.devinit = nv20_devinit_new,
.fb = nv25_fb_new,
.gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
.i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
@ -351,7 +351,7 @@ nv30_chipset = {
.devinit = nv20_devinit_new,
.fb = nv30_fb_new,
.gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
.i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
@ -372,7 +372,7 @@ nv31_chipset = {
.devinit = nv20_devinit_new,
.fb = nv30_fb_new,
.gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
.i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
@ -394,7 +394,7 @@ nv34_chipset = {
.devinit = nv10_devinit_new,
.fb = nv10_fb_new,
.gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
.i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
@ -416,7 +416,7 @@ nv35_chipset = {
.devinit = nv20_devinit_new,
.fb = nv35_fb_new,
.gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
.i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
@ -437,7 +437,7 @@ nv36_chipset = {
.devinit = nv20_devinit_new,
.fb = nv36_fb_new,
.gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
.i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
@ -459,7 +459,7 @@ nv40_chipset = {
.devinit = nv1a_devinit_new,
.fb = nv40_fb_new,
.gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
.i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
// .mc = nv40_mc_new,
// .mmu = nv04_mmu_new,
@ -484,7 +484,7 @@ nv41_chipset = {
.devinit = nv1a_devinit_new,
.fb = nv41_fb_new,
.gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
.i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
// .mc = nv40_mc_new,
// .mmu = nv41_mmu_new,
@ -509,7 +509,7 @@ nv42_chipset = {
.devinit = nv1a_devinit_new,
.fb = nv41_fb_new,
.gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
.i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
// .mc = nv40_mc_new,
// .mmu = nv41_mmu_new,
@ -534,7 +534,7 @@ nv43_chipset = {
.devinit = nv1a_devinit_new,
.fb = nv41_fb_new,
.gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
.i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
// .mc = nv40_mc_new,
// .mmu = nv41_mmu_new,
@ -559,7 +559,7 @@ nv44_chipset = {
.devinit = nv1a_devinit_new,
.fb = nv44_fb_new,
.gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
.i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
// .mc = nv44_mc_new,
// .mmu = nv44_mmu_new,
@ -584,7 +584,7 @@ nv45_chipset = {
.devinit = nv1a_devinit_new,
.fb = nv40_fb_new,
.gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
.i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
// .mc = nv40_mc_new,
// .mmu = nv04_mmu_new,
@ -609,7 +609,7 @@ nv46_chipset = {
.devinit = nv1a_devinit_new,
.fb = nv46_fb_new,
.gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
.i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
// .mc = nv44_mc_new,
// .mmu = nv44_mmu_new,
@ -634,7 +634,7 @@ nv47_chipset = {
.devinit = nv1a_devinit_new,
.fb = nv47_fb_new,
.gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
.i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
// .mc = nv40_mc_new,
// .mmu = nv41_mmu_new,
@ -659,7 +659,7 @@ nv49_chipset = {
.devinit = nv1a_devinit_new,
.fb = nv49_fb_new,
.gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
.i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
// .mc = nv40_mc_new,
// .mmu = nv41_mmu_new,
@ -684,7 +684,7 @@ nv4a_chipset = {
.devinit = nv1a_devinit_new,
.fb = nv44_fb_new,
.gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
.i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
// .mc = nv44_mc_new,
// .mmu = nv44_mmu_new,
@ -709,7 +709,7 @@ nv4b_chipset = {
.devinit = nv1a_devinit_new,
.fb = nv49_fb_new,
.gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
.i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
// .mc = nv40_mc_new,
// .mmu = nv41_mmu_new,
@ -734,7 +734,7 @@ nv4c_chipset = {
.devinit = nv1a_devinit_new,
.fb = nv46_fb_new,
.gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
.i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
// .mc = nv4c_mc_new,
// .mmu = nv44_mmu_new,
@ -759,7 +759,7 @@ nv4e_chipset = {
.devinit = nv1a_devinit_new,
.fb = nv4e_fb_new,
.gpio = nv10_gpio_new,
// .i2c = nv4e_i2c_new,
.i2c = nv4e_i2c_new,
// .imem = nv40_instmem_new,
// .mc = nv4c_mc_new,
// .mmu = nv44_mmu_new,
@ -786,7 +786,7 @@ nv50_chipset = {
.fb = nv50_fb_new,
.fuse = nv50_fuse_new,
.gpio = nv50_gpio_new,
// .i2c = nv50_i2c_new,
.i2c = nv50_i2c_new,
// .imem = nv50_instmem_new,
// .mc = nv50_mc_new,
// .mmu = nv50_mmu_new,
@ -812,7 +812,7 @@ nv63_chipset = {
.devinit = nv1a_devinit_new,
.fb = nv46_fb_new,
.gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
.i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
// .mc = nv4c_mc_new,
// .mmu = nv44_mmu_new,
@ -837,7 +837,7 @@ nv67_chipset = {
.devinit = nv1a_devinit_new,
.fb = nv46_fb_new,
.gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
.i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
// .mc = nv4c_mc_new,
// .mmu = nv44_mmu_new,
@ -862,7 +862,7 @@ nv68_chipset = {
.devinit = nv1a_devinit_new,
.fb = nv46_fb_new,
.gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
.i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
// .mc = nv4c_mc_new,
// .mmu = nv44_mmu_new,
@ -889,7 +889,7 @@ nv84_chipset = {
.fb = g84_fb_new,
.fuse = nv50_fuse_new,
.gpio = nv50_gpio_new,
// .i2c = nv50_i2c_new,
.i2c = nv50_i2c_new,
// .imem = nv50_instmem_new,
// .mc = nv50_mc_new,
// .mmu = nv50_mmu_new,
@ -920,7 +920,7 @@ nv86_chipset = {
.fb = g84_fb_new,
.fuse = nv50_fuse_new,
.gpio = nv50_gpio_new,
// .i2c = nv50_i2c_new,
.i2c = nv50_i2c_new,
// .imem = nv50_instmem_new,
// .mc = nv50_mc_new,
// .mmu = nv50_mmu_new,
@ -951,7 +951,7 @@ nv92_chipset = {
.fb = g84_fb_new,
.fuse = nv50_fuse_new,
.gpio = nv50_gpio_new,
// .i2c = nv50_i2c_new,
.i2c = nv50_i2c_new,
// .imem = nv50_instmem_new,
// .mc = nv50_mc_new,
// .mmu = nv50_mmu_new,
@ -982,7 +982,7 @@ nv94_chipset = {
.fb = g84_fb_new,
.fuse = nv50_fuse_new,
.gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
.i2c = g94_i2c_new,
// .imem = nv50_instmem_new,
// .mc = g94_mc_new,
// .mmu = nv50_mmu_new,
@ -1007,7 +1007,7 @@ nv96_chipset = {
.name = "G96",
.bios = nvkm_bios_new,
.gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
.i2c = g94_i2c_new,
.fuse = nv50_fuse_new,
.clk = g84_clk_new,
// .therm = g84_therm_new,
@ -1038,7 +1038,7 @@ nv98_chipset = {
.name = "G98",
.bios = nvkm_bios_new,
.gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
.i2c = g94_i2c_new,
.fuse = nv50_fuse_new,
.clk = g84_clk_new,
// .therm = g84_therm_new,
@ -1075,7 +1075,7 @@ nva0_chipset = {
.fb = g84_fb_new,
.fuse = nv50_fuse_new,
.gpio = g94_gpio_new,
// .i2c = nv50_i2c_new,
.i2c = nv50_i2c_new,
// .imem = nv50_instmem_new,
// .mc = g98_mc_new,
// .mmu = nv50_mmu_new,
@ -1106,7 +1106,7 @@ nva3_chipset = {
.fb = gt215_fb_new,
.fuse = nv50_fuse_new,
.gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
.i2c = g94_i2c_new,
// .imem = nv50_instmem_new,
// .mc = g98_mc_new,
// .mmu = nv50_mmu_new,
@ -1139,7 +1139,7 @@ nva5_chipset = {
.fb = gt215_fb_new,
.fuse = nv50_fuse_new,
.gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
.i2c = g94_i2c_new,
// .imem = nv50_instmem_new,
// .mc = g98_mc_new,
// .mmu = nv50_mmu_new,
@ -1171,7 +1171,7 @@ nva8_chipset = {
.fb = gt215_fb_new,
.fuse = nv50_fuse_new,
.gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
.i2c = g94_i2c_new,
// .imem = nv50_instmem_new,
// .mc = g98_mc_new,
// .mmu = nv50_mmu_new,
@ -1203,7 +1203,7 @@ nvaa_chipset = {
.fb = mcp77_fb_new,
.fuse = nv50_fuse_new,
.gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
.i2c = g94_i2c_new,
// .imem = nv50_instmem_new,
// .mc = g98_mc_new,
// .mmu = nv50_mmu_new,
@ -1234,7 +1234,7 @@ nvac_chipset = {
.fb = mcp77_fb_new,
.fuse = nv50_fuse_new,
.gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
.i2c = g94_i2c_new,
// .imem = nv50_instmem_new,
// .mc = g98_mc_new,
// .mmu = nv50_mmu_new,
@ -1265,7 +1265,7 @@ nvaf_chipset = {
.fb = mcp89_fb_new,
.fuse = nv50_fuse_new,
.gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
.i2c = g94_i2c_new,
// .imem = nv50_instmem_new,
// .mc = g98_mc_new,
// .mmu = nv50_mmu_new,
@ -1297,7 +1297,7 @@ nvc0_chipset = {
.fb = gf100_fb_new,
.fuse = gf100_fuse_new,
.gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
.i2c = g94_i2c_new,
// .ibus = gf100_ibus_new,
// .imem = nv50_instmem_new,
// .ltc = gf100_ltc_new,
@ -1332,7 +1332,7 @@ nvc1_chipset = {
.fb = gf100_fb_new,
.fuse = gf100_fuse_new,
.gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
.i2c = g94_i2c_new,
// .ibus = gf100_ibus_new,
// .imem = nv50_instmem_new,
// .ltc = gf100_ltc_new,
@ -1366,7 +1366,7 @@ nvc3_chipset = {
.fb = gf100_fb_new,
.fuse = gf100_fuse_new,
.gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
.i2c = g94_i2c_new,
// .ibus = gf100_ibus_new,
// .imem = nv50_instmem_new,
// .ltc = gf100_ltc_new,
@ -1400,7 +1400,7 @@ nvc4_chipset = {
.fb = gf100_fb_new,
.fuse = gf100_fuse_new,
.gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
.i2c = g94_i2c_new,
// .ibus = gf100_ibus_new,
// .imem = nv50_instmem_new,
// .ltc = gf100_ltc_new,
@ -1435,7 +1435,7 @@ nvc8_chipset = {
.fb = gf100_fb_new,
.fuse = gf100_fuse_new,
.gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
.i2c = g94_i2c_new,
// .ibus = gf100_ibus_new,
// .imem = nv50_instmem_new,
// .ltc = gf100_ltc_new,
@ -1470,7 +1470,7 @@ nvce_chipset = {
.fb = gf100_fb_new,
.fuse = gf100_fuse_new,
.gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
.i2c = g94_i2c_new,
// .ibus = gf100_ibus_new,
// .imem = nv50_instmem_new,
// .ltc = gf100_ltc_new,
@ -1505,7 +1505,7 @@ nvcf_chipset = {
.fb = gf100_fb_new,
.fuse = gf100_fuse_new,
.gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
.i2c = g94_i2c_new,
// .ibus = gf100_ibus_new,
// .imem = nv50_instmem_new,
// .ltc = gf100_ltc_new,
@ -1539,7 +1539,7 @@ nvd7_chipset = {
.fb = gf100_fb_new,
.fuse = gf100_fuse_new,
.gpio = gf119_gpio_new,
// .i2c = gf117_i2c_new,
.i2c = gf117_i2c_new,
// .ibus = gf100_ibus_new,
// .imem = nv50_instmem_new,
// .ltc = gf100_ltc_new,
@ -1571,7 +1571,7 @@ nvd9_chipset = {
.fb = gf100_fb_new,
.fuse = gf100_fuse_new,
.gpio = gf119_gpio_new,
// .i2c = gf110_i2c_new,
.i2c = gf119_i2c_new,
// .ibus = gf100_ibus_new,
// .imem = nv50_instmem_new,
// .ltc = gf100_ltc_new,
@ -1605,7 +1605,7 @@ nve4_chipset = {
.fb = gk104_fb_new,
.fuse = gf100_fuse_new,
.gpio = gk104_gpio_new,
// .i2c = gk104_i2c_new,
.i2c = gk104_i2c_new,
// .ibus = gk104_ibus_new,
// .imem = nv50_instmem_new,
// .ltc = gk104_ltc_new,
@ -1641,7 +1641,7 @@ nve6_chipset = {
.fb = gk104_fb_new,
.fuse = gf100_fuse_new,
.gpio = gk104_gpio_new,
// .i2c = gk104_i2c_new,
.i2c = gk104_i2c_new,
// .ibus = gk104_ibus_new,
// .imem = nv50_instmem_new,
// .ltc = gk104_ltc_new,
@ -1677,7 +1677,7 @@ nve7_chipset = {
.fb = gk104_fb_new,
.fuse = gf100_fuse_new,
.gpio = gk104_gpio_new,
// .i2c = gk104_i2c_new,
.i2c = gk104_i2c_new,
// .ibus = gk104_ibus_new,
// .imem = nv50_instmem_new,
// .ltc = gk104_ltc_new,
@ -1737,7 +1737,7 @@ nvf0_chipset = {
.fb = gk104_fb_new,
.fuse = gf100_fuse_new,
.gpio = gk104_gpio_new,
// .i2c = gk104_i2c_new,
.i2c = gk104_i2c_new,
// .ibus = gk104_ibus_new,
// .imem = nv50_instmem_new,
// .ltc = gk104_ltc_new,
@ -1773,7 +1773,7 @@ nvf1_chipset = {
.fb = gk104_fb_new,
.fuse = gf100_fuse_new,
.gpio = gk104_gpio_new,
// .i2c = gf110_i2c_new,
.i2c = gf119_i2c_new,
// .ibus = gk104_ibus_new,
// .imem = nv50_instmem_new,
// .ltc = gk104_ltc_new,
@ -1809,7 +1809,7 @@ nv106_chipset = {
.fb = gk104_fb_new,
.fuse = gf100_fuse_new,
.gpio = gk104_gpio_new,
// .i2c = gk104_i2c_new,
.i2c = gk104_i2c_new,
// .ibus = gk104_ibus_new,
// .imem = nv50_instmem_new,
// .ltc = gk104_ltc_new,
@ -1844,7 +1844,7 @@ nv108_chipset = {
.fb = gk104_fb_new,
.fuse = gf100_fuse_new,
.gpio = gk104_gpio_new,
// .i2c = gk104_i2c_new,
.i2c = gk104_i2c_new,
// .ibus = gk104_ibus_new,
// .imem = nv50_instmem_new,
// .ltc = gk104_ltc_new,
@ -1879,7 +1879,7 @@ nv117_chipset = {
.fb = gm107_fb_new,
.fuse = gm107_fuse_new,
.gpio = gk104_gpio_new,
// .i2c = gf110_i2c_new,
.i2c = gf119_i2c_new,
// .ibus = gk104_ibus_new,
// .imem = nv50_instmem_new,
// .ltc = gm107_ltc_new,
@ -1908,7 +1908,7 @@ nv124_chipset = {
.fb = gm107_fb_new,
.fuse = gm107_fuse_new,
.gpio = gk104_gpio_new,
// .i2c = gm204_i2c_new,
.i2c = gm204_i2c_new,
// .ibus = gk104_ibus_new,
// .imem = nv50_instmem_new,
// .ltc = gm107_ltc_new,
@ -1937,7 +1937,7 @@ nv126_chipset = {
.fb = gm107_fb_new,
.fuse = gm107_fuse_new,
.gpio = gk104_gpio_new,
// .i2c = gm204_i2c_new,
.i2c = gm204_i2c_new,
// .ibus = gk104_ibus_new,
// .imem = nv50_instmem_new,
// .ltc = gm107_ltc_new,

9
drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c
View File

@ -28,7 +28,6 @@ gf100_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0xc0:
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
@ -52,7 +51,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xc4:
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
@ -76,7 +74,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xc3:
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
@ -99,7 +96,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xce:
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
@ -123,7 +119,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xcf:
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
@ -146,7 +141,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xc1:
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
@ -169,7 +163,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gf108_pm_oclass;
break;
case 0xc8:
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
@ -193,7 +186,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xd9:
device->oclass[NVDEV_SUBDEV_I2C ] = gf110_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
@ -216,7 +208,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gf117_pm_oclass;
break;
case 0xd7:
device->oclass[NVDEV_SUBDEV_I2C ] = gf117_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;

7
drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
View File

@ -28,7 +28,6 @@ gk104_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0xe4:
device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
@ -53,7 +52,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
break;
case 0xe7:
device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
@ -78,7 +76,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
break;
case 0xe6:
device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
@ -119,7 +116,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_PMU ] = gk20a_pmu_oclass;
break;
case 0xf0:
device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
@ -144,7 +140,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass;
break;
case 0xf1:
device->oclass[NVDEV_SUBDEV_I2C ] = gf110_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
@ -169,7 +164,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass;
break;
case 0x106:
device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
@ -193,7 +187,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
break;
case 0x108:
device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;

3
drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
View File

@ -28,7 +28,6 @@ gm100_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0x117:
device->oclass[NVDEV_SUBDEV_I2C ] = gf110_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
@ -59,7 +58,6 @@ gm100_identify(struct nvkm_device *device)
#endif
break;
case 0x124:
device->oclass[NVDEV_SUBDEV_I2C ] = gm204_i2c_oclass;
#if 0
/* looks to be some non-trivial changes */
/* priv ring says no to 0x10eb14 writes */
@ -91,7 +89,6 @@ gm100_identify(struct nvkm_device *device)
#endif
break;
case 0x126:
device->oclass[NVDEV_SUBDEV_I2C ] = gm204_i2c_oclass;
#if 0
/* looks to be some non-trivial changes */
/* priv ring says no to 0x10eb14 writes */

2
drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
View File

@ -28,7 +28,6 @@ nv04_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0x04:
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
@ -40,7 +39,6 @@ nv04_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x05:
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;

8
drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
View File

@ -28,7 +28,6 @@ nv10_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0x10:
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
@ -38,7 +37,6 @@ nv10_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x15:
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
@ -50,7 +48,6 @@ nv10_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x16:
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
@ -62,7 +59,6 @@ nv10_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x1a:
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
@ -74,7 +70,6 @@ nv10_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x11:
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
@ -86,7 +81,6 @@ nv10_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x17:
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
@ -98,7 +92,6 @@ nv10_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x1f:
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
@ -110,7 +103,6 @@ nv10_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x18:
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;

4
drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
View File

@ -28,7 +28,6 @@ nv20_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0x20:
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
@ -40,7 +39,6 @@ nv20_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x25:
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
@ -52,7 +50,6 @@ nv20_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x28:
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
@ -64,7 +61,6 @@ nv20_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x2a:
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;

5
drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
View File

@ -28,7 +28,6 @@ nv30_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0x30:
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
@ -40,7 +39,6 @@ nv30_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x35:
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
@ -52,7 +50,6 @@ nv30_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x31:
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
@ -65,7 +62,6 @@ nv30_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x36:
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
@ -78,7 +74,6 @@ nv30_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x34:
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;

16
drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
View File

@ -28,7 +28,6 @@ nv40_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0x40:
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@ -44,7 +43,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x41:
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@ -60,7 +58,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x42:
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@ -76,7 +73,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x43:
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@ -92,7 +88,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x45:
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@ -108,7 +103,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x47:
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@ -124,7 +118,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x49:
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@ -140,7 +133,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x4b:
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@ -156,7 +148,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x44:
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@ -172,7 +163,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x46:
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@ -188,7 +178,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x4a:
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@ -204,7 +193,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x4c:
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@ -220,7 +208,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x4e:
device->oclass[NVDEV_SUBDEV_I2C ] = nv4e_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@ -236,7 +223,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x63:
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@ -252,7 +238,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x67:
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@ -268,7 +253,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x68:
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;

14
drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
View File

@ -28,7 +28,6 @@ nv50_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0x50:
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
@ -45,7 +44,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv50_pm_oclass;
break;
case 0x84:
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
@ -65,7 +63,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x86:
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
@ -85,7 +82,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x92:
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
@ -105,7 +101,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x94:
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g94_mc_oclass;
@ -125,7 +120,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x96:
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g94_mc_oclass;
@ -145,7 +139,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x98:
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
@ -165,7 +158,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0xa0:
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
@ -185,7 +177,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gt200_pm_oclass;
break;
case 0xaa:
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
@ -205,7 +196,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0xac:
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
@ -225,7 +215,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0xa3:
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
@ -247,7 +236,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
break;
case 0xa5:
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
@ -268,7 +256,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
break;
case 0xa8:
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
@ -289,7 +276,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
break;
case 0xaf:
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;

2
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/Kbuild
View File

@ -3,8 +3,8 @@ nvkm-y += nvkm/subdev/i2c/nv04.o
nvkm-y += nvkm/subdev/i2c/nv4e.o
nvkm-y += nvkm/subdev/i2c/nv50.o
nvkm-y += nvkm/subdev/i2c/g94.o
nvkm-y += nvkm/subdev/i2c/gf110.o
nvkm-y += nvkm/subdev/i2c/gf117.o
nvkm-y += nvkm/subdev/i2c/gf119.o
nvkm-y += nvkm/subdev/i2c/gk104.o
nvkm-y += nvkm/subdev/i2c/gm204.o

113
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c
View File

@ -91,9 +91,8 @@ nvkm_i2c_intr_fini(struct nvkm_event *event, int type, int id)
{
struct nvkm_i2c *i2c = container_of(event, typeof(*i2c), event);
struct nvkm_i2c_aux *aux = nvkm_i2c_aux_find(i2c, id);
const struct nvkm_i2c_impl *impl = (void *)nv_object(i2c)->oclass;
if (aux)
impl->aux_mask(i2c, type, aux->intr, 0);
i2c->func->aux_mask(i2c, type, aux->intr, 0);
}
static void
@ -101,9 +100,8 @@ nvkm_i2c_intr_init(struct nvkm_event *event, int type, int id)
{
struct nvkm_i2c *i2c = container_of(event, typeof(*i2c), event);
struct nvkm_i2c_aux *aux = nvkm_i2c_aux_find(i2c, id);
const struct nvkm_i2c_impl *impl = (void *)nv_object(i2c)->oclass;
if (aux)
impl->aux_mask(i2c, type, aux->intr, aux->intr);
i2c->func->aux_mask(i2c, type, aux->intr, aux->intr);
}
static int
@ -120,18 +118,24 @@ nvkm_i2c_intr_ctor(struct nvkm_object *object, void *data, u32 size,
return -EINVAL;
}
static const struct nvkm_event_func
nvkm_i2c_intr_func = {
.ctor = nvkm_i2c_intr_ctor,
.init = nvkm_i2c_intr_init,
.fini = nvkm_i2c_intr_fini,
};
static void
nvkm_i2c_intr(struct nvkm_subdev *obj)
nvkm_i2c_intr(struct nvkm_subdev *subdev)
{
struct nvkm_i2c *i2c = container_of(obj, typeof(*i2c), subdev);
struct nvkm_i2c_impl *impl = (void *)i2c->subdev.object.oclass;
struct nvkm_i2c *i2c = nvkm_i2c(subdev);
struct nvkm_i2c_aux *aux;
u32 hi, lo, rq, tx;
if (!impl->aux_stat)
if (!i2c->func->aux_stat)
return;
impl->aux_stat(i2c, &hi, &lo, &rq, &tx);
i2c->func->aux_stat(i2c, &hi, &lo, &rq, &tx);
if (!hi && !lo && !rq && !tx)
return;
@ -151,44 +155,31 @@ nvkm_i2c_intr(struct nvkm_subdev *obj)
}
}
static const struct nvkm_event_func
nvkm_i2c_intr_func = {
.ctor = nvkm_i2c_intr_ctor,
.init = nvkm_i2c_intr_init,
.fini = nvkm_i2c_intr_fini,
};
int
_nvkm_i2c_fini(struct nvkm_object *object, bool suspend)
static int
nvkm_i2c_fini(struct nvkm_subdev *subdev, bool suspend)
{
struct nvkm_i2c_impl *impl = (void *)nv_oclass(object);
struct nvkm_i2c *i2c = (void *)object;
struct nvkm_i2c *i2c = nvkm_i2c(subdev);
struct nvkm_i2c_pad *pad;
u32 mask;
if ((mask = (1 << impl->aux) - 1), impl->aux_stat) {
impl->aux_mask(i2c, NVKM_I2C_ANY, mask, 0);
impl->aux_stat(i2c, &mask, &mask, &mask, &mask);
if ((mask = (1 << i2c->func->aux) - 1), i2c->func->aux_stat) {
i2c->func->aux_mask(i2c, NVKM_I2C_ANY, mask, 0);
i2c->func->aux_stat(i2c, &mask, &mask, &mask, &mask);
}
list_for_each_entry(pad, &i2c->pad, head) {
nvkm_i2c_pad_fini(pad);
}
return nvkm_subdev_fini_old(&i2c->subdev, suspend);
return 0;
}
int
_nvkm_i2c_init(struct nvkm_object *object)
static int
nvkm_i2c_init(struct nvkm_subdev *subdev)
{
struct nvkm_i2c *i2c = (void *)object;
struct nvkm_i2c *i2c = nvkm_i2c(subdev);
struct nvkm_i2c_bus *bus;
struct nvkm_i2c_pad *pad;
int ret;
ret = nvkm_subdev_init_old(&i2c->subdev);
if (ret)
return ret;
list_for_each_entry(pad, &i2c->pad, head) {
nvkm_i2c_pad_init(pad);
@ -201,10 +192,10 @@ _nvkm_i2c_init(struct nvkm_object *object)
return 0;
}
void
_nvkm_i2c_dtor(struct nvkm_object *object)
static void *
nvkm_i2c_dtor(struct nvkm_subdev *subdev)
{
struct nvkm_i2c *i2c = (void *)object;
struct nvkm_i2c *i2c = nvkm_i2c(subdev);
nvkm_event_fini(&i2c->event);
@ -226,9 +217,17 @@ _nvkm_i2c_dtor(struct nvkm_object *object)
nvkm_i2c_pad_del(&pad);
}
nvkm_subdev_destroy(&i2c->subdev);
return i2c;
}
static const struct nvkm_subdev_func
nvkm_i2c = {
.dtor = nvkm_i2c_dtor,
.init = nvkm_i2c_init,
.fini = nvkm_i2c_fini,
.intr = nvkm_i2c_intr,
};
static const struct nvkm_i2c_drv {
u8 bios;
u8 addr;
@ -242,11 +241,9 @@ nvkm_i2c_drv[] = {
};
int
nvkm_i2c_create_(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, int length, void **pobject)
nvkm_i2c_new_(const struct nvkm_i2c_func *func, struct nvkm_device *device,
int index, struct nvkm_i2c **pi2c)
{
struct nvkm_i2c_impl *impl = (void *)oclass;
struct nvkm_device *device = (void *)parent;
struct nvkm_bios *bios = device->bios;
struct nvkm_i2c *i2c;
struct dcb_i2c_entry ccbE;
@ -254,17 +251,15 @@ nvkm_i2c_create_(struct nvkm_object *parent, struct nvkm_object *engine,
u8 ver, hdr;
int ret, i;
ret = nvkm_subdev_create(parent, engine, oclass, 0, "I2C", "i2c", &i2c);
*pobject = nv_object(i2c);
if (ret)
return ret;
if (!(i2c = *pi2c = kzalloc(sizeof(*i2c), GFP_KERNEL)))
return -ENOMEM;
nvkm_subdev_ctor(&nvkm_i2c, device, index, 0, &i2c->subdev);
i2c->func = func;
INIT_LIST_HEAD(&i2c->pad);
INIT_LIST_HEAD(&i2c->bus);
INIT_LIST_HEAD(&i2c->aux);
nv_subdev(i2c)->intr = nvkm_i2c_intr;
i = -1;
while (!dcb_i2c_parse(bios, ++i, &ccbE)) {
struct nvkm_i2c_pad *pad = NULL;
@ -278,11 +273,11 @@ nvkm_i2c_create_(struct nvkm_object *parent, struct nvkm_object *engine,
if (ccbE.share != DCB_I2C_UNUSED) {
const int id = NVKM_I2C_PAD_HYBRID(ccbE.share);
if (!(pad = nvkm_i2c_pad_find(i2c, id)))
ret = impl->pad_s_new(i2c, id, &pad);
ret = func->pad_s_new(i2c, id, &pad);
else
ret = 0;
} else {
ret = impl->pad_x_new(i2c, NVKM_I2C_PAD_CCB(i), &pad);
ret = func->pad_x_new(i2c, NVKM_I2C_PAD_CCB(i), &pad);
}
if (ret) {
@ -397,25 +392,5 @@ nvkm_i2c_create_(struct nvkm_object *parent, struct nvkm_object *engine,
}
}
ret = nvkm_event_init(&nvkm_i2c_intr_func, 4, i, &i2c->event);
if (ret)
return ret;
return 0;
}
int
_nvkm_i2c_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct nvkm_i2c *i2c;
int ret;
ret = nvkm_i2c_create(parent, engine, oclass, &i2c);
*pobject = nv_object(i2c);
if (ret)
return ret;
return 0;
return nvkm_event_init(&nvkm_i2c_intr_func, 4, i, &i2c->event);
}

19
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/g94.c
View File

@ -56,18 +56,17 @@ g94_aux_mask(struct nvkm_i2c *i2c, u32 type, u32 mask, u32 data)
nvkm_wr32(device, 0x00e068, temp);
}
struct nvkm_oclass *
g94_i2c_oclass = &(struct nvkm_i2c_impl) {
.base.handle = NV_SUBDEV(I2C, 0x94),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = _nvkm_i2c_ctor,
.dtor = _nvkm_i2c_dtor,
.init = _nvkm_i2c_init,
.fini = _nvkm_i2c_fini,
},
static const struct nvkm_i2c_func
g94_i2c = {
.pad_x_new = g94_i2c_pad_x_new,
.pad_s_new = g94_i2c_pad_s_new,
.aux = 4,
.aux_stat = g94_aux_stat,
.aux_mask = g94_aux_mask,
}.base;
};
int
g94_i2c_new(struct nvkm_device *device, int index, struct nvkm_i2c **pi2c)
{
return nvkm_i2c_new_(&g94_i2c, device, index, pi2c);
}

19
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf117.c
View File

@ -24,14 +24,13 @@
#include "priv.h"
#include "pad.h"
struct nvkm_oclass *
gf117_i2c_oclass = &(struct nvkm_i2c_impl) {
.base.handle = NV_SUBDEV(I2C, 0xd7),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = _nvkm_i2c_ctor,
.dtor = _nvkm_i2c_dtor,
.init = _nvkm_i2c_init,
.fini = _nvkm_i2c_fini,
},
static const struct nvkm_i2c_func
gf117_i2c = {
.pad_x_new = gf119_i2c_pad_x_new,
}.base;
};
int
gf117_i2c_new(struct nvkm_device *device, int index, struct nvkm_i2c **pi2c)
{
return nvkm_i2c_new_(&gf117_i2c, device, index, pi2c);
}

19
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf110.c → drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf119.c
View File

@ -24,18 +24,17 @@
#include "priv.h"
#include "pad.h"
struct nvkm_oclass *
gf110_i2c_oclass = &(struct nvkm_i2c_impl) {
.base.handle = NV_SUBDEV(I2C, 0xd0),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = _nvkm_i2c_ctor,
.dtor = _nvkm_i2c_dtor,
.init = _nvkm_i2c_init,
.fini = _nvkm_i2c_fini,
},
static const struct nvkm_i2c_func
gf119_i2c = {
.pad_x_new = gf119_i2c_pad_x_new,
.pad_s_new = gf119_i2c_pad_s_new,
.aux = 4,
.aux_stat = g94_aux_stat,
.aux_mask = g94_aux_mask,
}.base;
};
int
gf119_i2c_new(struct nvkm_device *device, int index, struct nvkm_i2c **pi2c)
{
return nvkm_i2c_new_(&gf119_i2c, device, index, pi2c);
}

19
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk104.c
View File

@ -56,18 +56,17 @@ gk104_aux_mask(struct nvkm_i2c *i2c, u32 type, u32 mask, u32 data)
nvkm_wr32(device, 0x00dc68, temp);
}
struct nvkm_oclass *
gk104_i2c_oclass = &(struct nvkm_i2c_impl) {
.base.handle = NV_SUBDEV(I2C, 0xe0),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = _nvkm_i2c_ctor,
.dtor = _nvkm_i2c_dtor,
.init = _nvkm_i2c_init,
.fini = _nvkm_i2c_fini,
},
static const struct nvkm_i2c_func
gk104_i2c = {
.pad_x_new = gf119_i2c_pad_x_new,
.pad_s_new = gf119_i2c_pad_s_new,
.aux = 4,
.aux_stat = gk104_aux_stat,
.aux_mask = gk104_aux_mask,
}.base;
};
int
gk104_i2c_new(struct nvkm_device *device, int index, struct nvkm_i2c **pi2c)
{
return nvkm_i2c_new_(&gk104_i2c, device, index, pi2c);
}

19
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gm204.c
View File

@ -24,18 +24,17 @@
#include "priv.h"
#include "pad.h"
struct nvkm_oclass *
gm204_i2c_oclass = &(struct nvkm_i2c_impl) {
.base.handle = NV_SUBDEV(I2C, 0x24),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = _nvkm_i2c_ctor,
.dtor = _nvkm_i2c_dtor,
.init = _nvkm_i2c_init,
.fini = _nvkm_i2c_fini,
},
static const struct nvkm_i2c_func
gm204_i2c = {
.pad_x_new = gf119_i2c_pad_x_new,
.pad_s_new = gm204_i2c_pad_s_new,
.aux = 8,
.aux_stat = gk104_aux_stat,
.aux_mask = gk104_aux_mask,
}.base;
};
int
gm204_i2c_new(struct nvkm_device *device, int index, struct nvkm_i2c **pi2c)
{
return nvkm_i2c_new_(&gm204_i2c, device, index, pi2c);
}

19
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv04.c
View File

@ -24,14 +24,13 @@
#include "priv.h"
#include "pad.h"
struct nvkm_oclass *
nv04_i2c_oclass = &(struct nvkm_i2c_impl) {
.base.handle = NV_SUBDEV(I2C, 0x04),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = _nvkm_i2c_ctor,
.dtor = _nvkm_i2c_dtor,
.init = _nvkm_i2c_init,
.fini = _nvkm_i2c_fini,
},
static const struct nvkm_i2c_func
nv04_i2c = {
.pad_x_new = nv04_i2c_pad_new,
}.base;
};
int
nv04_i2c_new(struct nvkm_device *device, int index, struct nvkm_i2c **pi2c)
{
return nvkm_i2c_new_(&nv04_i2c, device, index, pi2c);
}

19
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv4e.c
View File

@ -24,14 +24,13 @@
#include "priv.h"
#include "pad.h"
struct nvkm_oclass *
nv4e_i2c_oclass = &(struct nvkm_i2c_impl) {
.base.handle = NV_SUBDEV(I2C, 0x4e),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = _nvkm_i2c_ctor,
.dtor = _nvkm_i2c_dtor,
.init = _nvkm_i2c_init,
.fini = _nvkm_i2c_fini,
},
static const struct nvkm_i2c_func
nv4e_i2c = {
.pad_x_new = nv4e_i2c_pad_new,
}.base;
};
int
nv4e_i2c_new(struct nvkm_device *device, int index, struct nvkm_i2c **pi2c)
{
return nvkm_i2c_new_(&nv4e_i2c, device, index, pi2c);
}

19
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv50.c
View File

@ -24,14 +24,13 @@
#include "priv.h"
#include "pad.h"
struct nvkm_oclass *
nv50_i2c_oclass = &(struct nvkm_i2c_impl) {
.base.handle = NV_SUBDEV(I2C, 0x50),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = _nvkm_i2c_ctor,
.dtor = _nvkm_i2c_dtor,
.init = _nvkm_i2c_init,
.fini = _nvkm_i2c_fini,
},
static const struct nvkm_i2c_func
nv50_i2c = {
.pad_x_new = nv50_i2c_pad_new,
}.base;
};
int
nv50_i2c_new(struct nvkm_device *device, int index, struct nvkm_i2c **pi2c)
{
return nvkm_i2c_new_(&nv50_i2c, device, index, pi2c);
}

30
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/priv.h
View File

@ -1,34 +1,12 @@
#ifndef __NVKM_I2C_PRIV_H__
#define __NVKM_I2C_PRIV_H__
#define nvkm_i2c(p) container_of((p), struct nvkm_i2c, subdev)
#include <subdev/i2c.h>
#define nvkm_i2c_create(p,e,o,d) \
nvkm_i2c_create_((p), (e), (o), sizeof(**d), (void **)d)
#define nvkm_i2c_destroy(p) ({ \
struct nvkm_i2c *i2c = (p); \
_nvkm_i2c_dtor(nv_object(i2c)); \
})
#define nvkm_i2c_init(p) ({ \
struct nvkm_i2c *i2c = (p); \
_nvkm_i2c_init(nv_object(i2c)); \
})
#define nvkm_i2c_fini(p,s) ({ \
struct nvkm_i2c *i2c = (p); \
_nvkm_i2c_fini(nv_object(i2c), (s)); \
})
int nvkm_i2c_create_(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, int, void **);
int _nvkm_i2c_ctor(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, void *, u32,
struct nvkm_object **);
void _nvkm_i2c_dtor(struct nvkm_object *);
int _nvkm_i2c_init(struct nvkm_object *);
int _nvkm_i2c_fini(struct nvkm_object *, bool);
struct nvkm_i2c_impl {
struct nvkm_oclass base;
int nvkm_i2c_new_(const struct nvkm_i2c_func *, struct nvkm_device *,
int index, struct nvkm_i2c **);
struct nvkm_i2c_func {
int (*pad_x_new)(struct nvkm_i2c *, int id, struct nvkm_i2c_pad **);
int (*pad_s_new)(struct nvkm_i2c *, int id, struct nvkm_i2c_pad **);