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media: dt-bindings: media: sunxi-ir: Add A31 compatible
Allwinner A31 has introduced a new memory mapping and a reset line. The difference in memory mapping are : - In the configure register there is a new sample bit and Allwinner has introduced the active threshold feature. - In the status register a new STAT bit is present. Note: CGPO and DRQ_EN bits are removed on A31 but present on A13 and on new SoCs like A64/H6. This is actually not an issue as these bits are togglable and new SoCs have a dedicated bindings. Introduce this bindings to make a difference since this generation. And declare the reset line required since A31. Signed-off-by: Clément Péron <peron.clem@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Sean Young <sean@mess.org> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
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Device-Tree bindings for SUNXI IR controller found in sunXi SoC family
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Required properties:
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- compatible : "allwinner,sun4i-a10-ir" or "allwinner,sun5i-a13-ir"
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- compatible :
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"allwinner,sun4i-a10-ir"
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"allwinner,sun5i-a13-ir"
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"allwinner,sun6i-a31-ir"
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- clocks : list of clock specifiers, corresponding to
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entries in clock-names property;
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- clock-names : should contain "apb" and "ir" entries;
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- interrupts : should contain IR IRQ number;
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- reg : should contain IO map address for IR.
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Required properties since A31:
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- resets : phandle + reset specifier pair
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Optional properties:
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- linux,rc-map-name: see rc.txt file in the same directory.
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- resets : phandle + reset specifier pair
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- clock-frequency : IR Receiver clock frequency, in Hertz. Defaults to 8 MHz
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if missing.
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