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drm/radeon/kms/atom: add support for DCE6.x dig transmitters
Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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@ -703,6 +703,7 @@ union dig_transmitter_control {
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DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
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DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
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DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
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DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
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};
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void
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@ -723,6 +724,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
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int connector_object_id = 0;
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int igp_lane_info = 0;
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int dig_encoder = dig->dig_encoder;
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int hpd_id = RADEON_HPD_NONE;
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if (action == ATOM_TRANSMITTER_ACTION_INIT) {
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connector = radeon_get_connector_for_encoder_init(encoder);
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@ -738,6 +740,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
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struct radeon_connector_atom_dig *dig_connector =
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radeon_connector->con_priv;
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hpd_id = radeon_connector->hpd.hpd;
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dp_clock = dig_connector->dp_clock;
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dp_lane_count = dig_connector->dp_lane_count;
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connector_object_id =
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@ -1003,6 +1006,60 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
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args.v4.acConfig.fDualLinkConnector = 1;
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}
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break;
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case 5:
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args.v5.ucAction = action;
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if (is_dp)
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args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
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else
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args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
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switch (radeon_encoder->encoder_id) {
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
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if (dig->linkb)
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args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
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else
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args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
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break;
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
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if (dig->linkb)
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args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
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else
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args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
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break;
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
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if (dig->linkb)
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args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
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else
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args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
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break;
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}
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if (is_dp)
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args.v5.ucLaneNum = dp_lane_count;
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else if (radeon_encoder->pixel_clock > 165000)
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args.v5.ucLaneNum = 8;
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else
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args.v5.ucLaneNum = 4;
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args.v5.ucConnObjId = connector_object_id;
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args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
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if (is_dp && rdev->clock.dp_extclk)
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args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
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else
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args.v5.asConfig.ucPhyClkSrcId = pll_id;
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if (is_dp)
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args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
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else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
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if (dig->coherent_mode)
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args.v5.asConfig.ucCoherentMode = 1;
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}
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if (hpd_id == RADEON_HPD_NONE)
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args.v5.asConfig.ucHPDSel = 0;
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else
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args.v5.asConfig.ucHPDSel = hpd_id + 1;
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args.v5.ucDigEncoderSel = 1 << dig_encoder;
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args.v5.ucDPLaneSet = lane_set;
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break;
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default:
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DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
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break;
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