mirror of
https://github.com/edk2-porting/linux-next.git
synced 2025-01-15 00:54:03 +08:00
drm/amd/pp: Remove wrong code in fiji_start_smu
HW CG feature will be enabled after hw ip initialized Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
e5a4059ceb
commit
479afffe21
@ -302,16 +302,6 @@ static int fiji_start_smu(struct pp_hwmgr *hwmgr)
|
||||
hwmgr->avfs_supported = false;
|
||||
}
|
||||
|
||||
/* To initialize all clock gating before RLC loaded and running.*/
|
||||
amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
|
||||
AMD_IP_BLOCK_TYPE_GFX, AMD_CG_STATE_GATE);
|
||||
amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
|
||||
AMD_IP_BLOCK_TYPE_GMC, AMD_CG_STATE_GATE);
|
||||
amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
|
||||
AMD_IP_BLOCK_TYPE_SDMA, AMD_CG_STATE_GATE);
|
||||
amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
|
||||
AMD_IP_BLOCK_TYPE_COMMON, AMD_CG_STATE_GATE);
|
||||
|
||||
/* Setup SoftRegsStart here for register lookup in case
|
||||
* DummyBackEnd is used and ProcessFirmwareHeader is not executed
|
||||
*/
|
||||
|
Loading…
Reference in New Issue
Block a user