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drm/amd/display: Hook DCN2 into amdgpu_dm and expose as config (v2)
Enable DCN2 support in DM (Display Manager). v2: fix spurious raven change (Alex) Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -16,6 +16,15 @@ config DRM_AMD_DC_DCN1_0
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help
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help
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RV family support for display engine
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RV family support for display engine
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config DRM_AMD_DC_DCN2_0
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bool "DCN 2.0 family"
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default y
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depends on DRM_AMD_DC && X86
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depends on DRM_AMD_DC_DCN1_0
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help
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Choose this option if you want to have
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Navi support for display engine
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config DEBUG_KERNEL_DC
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config DEBUG_KERNEL_DC
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bool "Enable kgdb break in DC"
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bool "Enable kgdb break in DC"
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depends on DRM_AMD_DC
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depends on DRM_AMD_DC
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@ -666,6 +666,7 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
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case CHIP_VEGA10:
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case CHIP_VEGA10:
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case CHIP_VEGA12:
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case CHIP_VEGA12:
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case CHIP_VEGA20:
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case CHIP_VEGA20:
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case CHIP_NAVI10:
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return 0;
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return 0;
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case CHIP_RAVEN:
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case CHIP_RAVEN:
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if (ASICREV_IS_PICASSO(adev->external_rev_id))
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if (ASICREV_IS_PICASSO(adev->external_rev_id))
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@ -2210,6 +2211,9 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
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break;
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break;
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#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
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#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
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case CHIP_RAVEN:
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case CHIP_RAVEN:
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#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
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case CHIP_NAVI10:
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#endif
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if (dcn10_register_irq_handlers(dm->adev)) {
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if (dcn10_register_irq_handlers(dm->adev)) {
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DRM_ERROR("DM: Failed to initialize IRQ\n");
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DRM_ERROR("DM: Failed to initialize IRQ\n");
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goto fail;
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goto fail;
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@ -2362,6 +2366,13 @@ static int dm_early_init(void *handle)
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adev->mode_info.num_hpd = 4;
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adev->mode_info.num_hpd = 4;
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adev->mode_info.num_dig = 4;
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adev->mode_info.num_dig = 4;
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break;
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break;
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#endif
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#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
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case CHIP_NAVI10:
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adev->mode_info.num_crtc = 6;
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adev->mode_info.num_hpd = 6;
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adev->mode_info.num_dig = 6;
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break;
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#endif
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#endif
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default:
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default:
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DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
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DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
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@ -2655,6 +2666,9 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
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if (adev->asic_type == CHIP_VEGA10 ||
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if (adev->asic_type == CHIP_VEGA10 ||
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adev->asic_type == CHIP_VEGA12 ||
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adev->asic_type == CHIP_VEGA12 ||
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adev->asic_type == CHIP_VEGA20 ||
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adev->asic_type == CHIP_VEGA20 ||
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#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
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adev->asic_type == CHIP_NAVI10 ||
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#endif
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adev->asic_type == CHIP_RAVEN) {
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adev->asic_type == CHIP_RAVEN) {
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/* Fill GFX9 params */
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/* Fill GFX9 params */
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tiling_info->gfx9.num_pipes =
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tiling_info->gfx9.num_pipes =
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@ -166,7 +166,7 @@ int amdgpu_dm_set_regamma_lut(struct dm_crtc_state *crtc)
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*/
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*/
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stream->out_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS;
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stream->out_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS;
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ret = mod_color_calculate_regamma_params(stream->out_transfer_func,
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ret = mod_color_calculate_regamma_params(stream->out_transfer_func,
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gamma, true, adev->asic_type <= CHIP_RAVEN, NULL);
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gamma, true, adev->asic_type <= CHIP_NAVI10, NULL);
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if (gamma)
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if (gamma)
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dc_gamma_release(&gamma);
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dc_gamma_release(&gamma);
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