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bus: mvebu-mbus: provide a mechanism to save SDRAM window configuration
On Marvell EBU platforms, when doing suspend/resume, the SDRAM window configuration must be saved on suspend, and restored on resume. However, it needs to be restored on resume *before* re-entering the kernel, because the SDRAM window configuration defines the layout of the memory. For this reason, it cannot simply be done in the ->suspend() and ->resume() hooks of the mvebu-mbus driver. Instead, it needs to be restored by the bootloader "boot info" mechanism used when resuming. This mechanism allows the kernel to define a list of (address, value) pairs when suspending, that the bootloader will restore on resume before jumping back into the kernel. This commit therefore adds a new function to the mvebu-mbus driver, called mvebu_mbus_save_cpu_target(), which will be called by the platform code to make the mvebu-mbus driver save the SDRAM window configuration in a way that can be understood by the bootloader "boot info" mechanism. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1416585613-2113-8-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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@ -110,6 +110,8 @@ struct mvebu_mbus_soc_data {
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bool has_mbus_bridge;
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unsigned int (*win_cfg_offset)(const int win);
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void (*setup_cpu_target)(struct mvebu_mbus_state *s);
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int (*save_cpu_target)(struct mvebu_mbus_state *s,
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u32 *store_addr);
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int (*show_cpu_target)(struct mvebu_mbus_state *s,
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struct seq_file *seq, void *v);
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};
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@ -128,6 +130,7 @@ struct mvebu_mbus_state {
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void __iomem *mbuswins_base;
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void __iomem *sdramwins_base;
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void __iomem *mbusbridge_base;
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phys_addr_t sdramwins_phys_base;
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struct dentry *debugfs_root;
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struct dentry *debugfs_sdram;
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struct dentry *debugfs_devs;
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@ -541,6 +544,28 @@ mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
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mvebu_mbus_dram_info.num_cs = cs;
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}
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static int
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mvebu_mbus_default_save_cpu_target(struct mvebu_mbus_state *mbus,
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u32 *store_addr)
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{
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int i;
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for (i = 0; i < 4; i++) {
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u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
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u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
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writel(mbus->sdramwins_phys_base + DDR_BASE_CS_OFF(i),
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store_addr++);
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writel(base, store_addr++);
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writel(mbus->sdramwins_phys_base + DDR_SIZE_CS_OFF(i),
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store_addr++);
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writel(size, store_addr++);
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}
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/* We've written 16 words to the store address */
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return 16;
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}
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static void __init
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mvebu_mbus_dove_setup_cpu_target(struct mvebu_mbus_state *mbus)
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{
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@ -571,11 +596,35 @@ mvebu_mbus_dove_setup_cpu_target(struct mvebu_mbus_state *mbus)
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mvebu_mbus_dram_info.num_cs = cs;
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}
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static int
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mvebu_mbus_dove_save_cpu_target(struct mvebu_mbus_state *mbus,
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u32 *store_addr)
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{
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int i;
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for (i = 0; i < 2; i++) {
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u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
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writel(mbus->sdramwins_phys_base + DOVE_DDR_BASE_CS_OFF(i),
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store_addr++);
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writel(map, store_addr++);
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}
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/* We've written 4 words to the store address */
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return 4;
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}
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int mvebu_mbus_save_cpu_target(u32 *store_addr)
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{
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return mbus_state.soc->save_cpu_target(&mbus_state, store_addr);
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}
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static const struct mvebu_mbus_soc_data armada_370_xp_mbus_data = {
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.num_wins = 20,
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.num_remappable_wins = 8,
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.has_mbus_bridge = true,
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.win_cfg_offset = armada_370_xp_mbus_win_offset,
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.save_cpu_target = mvebu_mbus_default_save_cpu_target,
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.setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
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.show_cpu_target = mvebu_sdram_debug_show_orion,
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};
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@ -584,6 +633,7 @@ static const struct mvebu_mbus_soc_data kirkwood_mbus_data = {
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.num_wins = 8,
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.num_remappable_wins = 4,
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.win_cfg_offset = orion_mbus_win_offset,
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.save_cpu_target = mvebu_mbus_default_save_cpu_target,
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.setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
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.show_cpu_target = mvebu_sdram_debug_show_orion,
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};
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@ -592,6 +642,7 @@ static const struct mvebu_mbus_soc_data dove_mbus_data = {
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.num_wins = 8,
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.num_remappable_wins = 4,
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.win_cfg_offset = orion_mbus_win_offset,
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.save_cpu_target = mvebu_mbus_dove_save_cpu_target,
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.setup_cpu_target = mvebu_mbus_dove_setup_cpu_target,
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.show_cpu_target = mvebu_sdram_debug_show_dove,
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};
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@ -604,6 +655,7 @@ static const struct mvebu_mbus_soc_data orion5x_4win_mbus_data = {
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.num_wins = 8,
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.num_remappable_wins = 4,
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.win_cfg_offset = orion_mbus_win_offset,
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.save_cpu_target = mvebu_mbus_default_save_cpu_target,
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.setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
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.show_cpu_target = mvebu_sdram_debug_show_orion,
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};
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@ -612,6 +664,7 @@ static const struct mvebu_mbus_soc_data orion5x_2win_mbus_data = {
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.num_wins = 8,
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.num_remappable_wins = 2,
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.win_cfg_offset = orion_mbus_win_offset,
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.save_cpu_target = mvebu_mbus_default_save_cpu_target,
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.setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
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.show_cpu_target = mvebu_sdram_debug_show_orion,
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};
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@ -620,6 +673,7 @@ static const struct mvebu_mbus_soc_data mv78xx0_mbus_data = {
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.num_wins = 14,
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.num_remappable_wins = 8,
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.win_cfg_offset = mv78xx0_mbus_win_offset,
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.save_cpu_target = mvebu_mbus_default_save_cpu_target,
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.setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
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.show_cpu_target = mvebu_sdram_debug_show_orion,
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};
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@ -804,6 +858,8 @@ static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus,
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return -ENOMEM;
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}
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mbus->sdramwins_phys_base = sdramwins_phys_base;
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if (mbusbridge_phys_base) {
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mbus->mbusbridge_base = ioremap(mbusbridge_phys_base,
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mbusbridge_size);
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@ -61,6 +61,7 @@ static inline const struct mbus_dram_target_info *mv_mbus_dram_info(void)
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}
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#endif
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int mvebu_mbus_save_cpu_target(u32 *store_addr);
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void mvebu_mbus_get_pcie_mem_aperture(struct resource *res);
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void mvebu_mbus_get_pcie_io_aperture(struct resource *res);
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int mvebu_mbus_add_window_remap_by_id(unsigned int target,
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