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MIPS: Alchemy: clock framework integration of onchip clocks

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This patch introduces common clock framework integration for all
configurable on-chip clocks on Alchemy chips:

- 2 or 3 PLLs which generate integer multiples of the root rate 12MHz,
- 6 dividers which take one of the 3 PLLs as input and divide their
  rate by either multiples of 2 or 1 (Au1300).
- another bank of up to 6 muxes which take either one of the 6
  above dividers or one of the PLLs directly and divide their rate
  further by 1, 2, 3 or 4.
- a few other sources which are used by onchip peripherals and are
  informational.

This implementation will take the clock tree as it was set up
by boot firmware: all in-kernel boards should continue to work
without having to set up the clock tree in board code.

CLK_IGNORE_DISABLED will be removed once all drivers have been
converted.

Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/7466/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Manuel Lauss 2014-07-23 16:36:48 +02:00 committed by Ralf Baechle
parent 2f73bfbe08
commit 474402291a
4 changed files with 1115 additions and 2 deletions
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1
arch/mips/Kconfig
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@ -72,6 +72,7 @@ config MIPS_ALCHEMY
select SYS_SUPPORTS_APM_EMULATION
select ARCH_REQUIRE_GPIOLIB
select SYS_SUPPORTS_ZBOOT
select COMMON_CLK
config AR7
bool "Texas Instruments AR7"

4
arch/mips/alchemy/common/Makefile
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@ -5,8 +5,8 @@
# Makefile for the Alchemy Au1xx0 CPUs, generic files.
#
obj-y += prom.o time.o clocks.o platform.o power.o setup.o \
sleeper.o dma.o dbdma.o vss.o irq.o usb.o
obj-y += prom.o time.o clock.o clocks.o platform.o power.o \
setup.o sleeper.o dma.o dbdma.o vss.o irq.o usb.o
# optional gpiolib support
ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),)

1096
arch/mips/alchemy/common/clock.c Normal file
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File diff suppressed because it is too large Load Diff

16
arch/mips/include/asm/mach-au1x00/au1000.h
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@ -47,6 +47,21 @@
#define ALCHEMY_GPIC_INT_NUM 128
#define ALCHEMY_GPIC_INT_LAST (ALCHEMY_GPIC_INT_BASE + ALCHEMY_GPIC_INT_NUM - 1)
/* common clock names, shared among all variants. AUXPLL2 is Au1300 */
#define ALCHEMY_ROOT_CLK "root_clk"
#define ALCHEMY_CPU_CLK "cpu_clk"
#define ALCHEMY_AUXPLL_CLK "auxpll_clk"
#define ALCHEMY_AUXPLL2_CLK "auxpll2_clk"
#define ALCHEMY_SYSBUS_CLK "sysbus_clk"
#define ALCHEMY_PERIPH_CLK "periph_clk"
#define ALCHEMY_MEM_CLK "mem_clk"
#define ALCHEMY_LR_CLK "lr_clk"
#define ALCHEMY_FG0_CLK "fg0_clk"
#define ALCHEMY_FG1_CLK "fg1_clk"
#define ALCHEMY_FG2_CLK "fg2_clk"
#define ALCHEMY_FG3_CLK "fg3_clk"
#define ALCHEMY_FG4_CLK "fg4_clk"
#define ALCHEMY_FG5_CLK "fg5_clk"
/* Au1300 peripheral interrupt numbers */
#define AU1300_FIRST_INT (ALCHEMY_GPIC_INT_BASE)
@ -523,6 +538,7 @@
#define AU1000_SYS_CPUPLL 0x60
#define AU1000_SYS_AUXPLL 0x64
#define AU1300_SYS_AUXPLL2 0x68
/**********************************************************************/