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ASoC: TWL6040: Fix playback with 19.2 Mhz MCLK

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When using MCLK is configured for 19.2 Mhz, clock slicer should be
enabled and HPPLL should be bypassed in clock path.

Signed-off-by: Jorge Eduardo Candelaria <jorge.candelaria@ti.com>
Signed-off-by: Margarita Olaya Cabrera <magi.olaya@ti.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
This commit is contained in:
Jorge Eduardo Candelaria 2010-05-20 17:53:07 -05:00 committed by Liam Girdwood
parent ad8332c130
commit 44ebaa5de1
1 changed files with 1 additions and 1 deletions
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sound/soc/codecs/twl6040.c
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@ -928,7 +928,7 @@ static int twl6040_set_dai_sysclk(struct snd_soc_dai *codec_dai,
case 19200000: case 19200000:
/* mclk input, pll disabled */ /* mclk input, pll disabled */
hppllctl |= TWL6040_MCLK_19200KHZ | hppllctl |= TWL6040_MCLK_19200KHZ |
TWL6040_HPLLSQRBP | TWL6040_HPLLSQRENA |
TWL6040_HPLLBP; TWL6040_HPLLBP;
break; break;
case 26000000: case 26000000: