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ASoC: TWL6040: Fix playback with 19.2 Mhz MCLK
When using MCLK is configured for 19.2 Mhz, clock slicer should be enabled and HPPLL should be bypassed in clock path. Signed-off-by: Jorge Eduardo Candelaria <jorge.candelaria@ti.com> Signed-off-by: Margarita Olaya Cabrera <magi.olaya@ti.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
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@ -928,7 +928,7 @@ static int twl6040_set_dai_sysclk(struct snd_soc_dai *codec_dai,
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case 19200000:
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/* mclk input, pll disabled */
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hppllctl |= TWL6040_MCLK_19200KHZ |
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TWL6040_HPLLSQRBP |
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TWL6040_HPLLSQRENA |
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TWL6040_HPLLBP;
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break;
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case 26000000:
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